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1. 发明申请

US20160004292A1 MICROCONTROLLER WITH MULTIPLE POWER MODES 有权
标题翻译：具有多种功率模式的微控制器
公开(公告)号：US20160004292A1
公开(公告)日：2016-01-07
申请号：US14321838
申请日：2014-07-02
申请人： Garima Sharda , Carl Culshaw , Alan Devine , Akshay K. Pathak , Alistair P. Robertson
发明人： Garima Sharda , Carl Culshaw , Alan Devine , Akshay K. Pathak , Alistair P. Robertson
IPC分类号： G06F1/32 , G06F13/40
CPC分类号： G06F1/3243 , G06F1/3203 , G06F1/324 , G06F1/3293 , G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： A microcontroller operable in a high power mode and a low power unit (LPU) run mode includes primary and LPU domains, primary and LPU mode controllers, and primary and LPU clock generator modules. The primary domain includes a first set of circuits and a first set of cores. The LPU domain includes second and third sets of circuits, a second set of cores, and a switching module. In the high power mode, the switching module connects the first and second sets of cores to at least one of the first, second and third sets of circuits, while in the LPU run mode, the switching module isolates the LPU domain from the primary domain and activates a small microcontroller system (SMS) that includes the LPU domain, the LPU mode controller and the LPU clock generator module. The SMS has further low power modes within the LPU run mode.
摘要翻译：在高功率模式和低功率单元（LPU）运行模式下可操作的微控制器包括主和LPU域，主和LPU模式控制器以及主和LPU时钟发生器模块。主域包括第一组电路和第一组核心。 LPU域包括第二组和第三组电路，第二组磁芯和开关模块。在高功率模式下，交换模块将第一和第二组核心连接到第一组，第二组和第三组电路中的至少一个，而在LPU运行模式下，交换模块将LPU域与主域隔离开并激活包括LPU域，LPU模式控制器和LPU时钟发生器模块的小型微控制器系统（SMS）。在LPU运行模式下，SMS还具有进一步的低功耗模式。

2. 发明申请

US20150309730A1 SYSTEM PERFORMANCE CONTROL COMPONENT AND METHOD THEREFOR 有权
标题翻译：系统性能控制组件及其方法
公开(公告)号：US20150309730A1
公开(公告)日：2015-10-29
申请号：US14261589
申请日：2014-04-25
申请人： MARK MAIOLANI , GORDON JAMES CAMPBELL , CARL CULSHAW , ALISTAIR JAMES GORMAN , DAVID MCMENAMIN
发明人： MARK MAIOLANI , GORDON JAMES CAMPBELL , CARL CULSHAW , ALISTAIR JAMES GORMAN , DAVID MCMENAMIN
IPC分类号： G06F3/06
CPC分类号： G06F3/0604 , G06F1/32 , G06F1/3206 , G06F1/324 , G06F1/3296 , G06F3/0629 , G06F3/0673 , G06F9/00 , G06F11/34 , G06F11/3648 , G06F13/00 , Y02D10/126 , Y02D10/172
摘要： A system performance control component, and method therefor, for configuring at least one system performance parameter within a signal processing system. The system performance control component is arranged to receive an indication of an address of a memory access performed by at least one signal processing component, compare the received indication of an address of a memory access to at least one address value, and configure at least one system performance parameter based at least partly on the comparison of the received indication of an address of a memory access to at least one address value.
摘要翻译：一种系统性能控制部件及其方法，用于在信号处理系统内配置至少一个系统性能参数。系统性能控制部件被布置为接收由至少一个信号处理部件执行的存储器访问的地址的指示，将接收到的存储器访问的指示与至少一个地址值进行比较，并配置至少一个系统性能参数至少部分地基于存储器访问的地址的接收指示与至少一个地址值的比较。

3. 发明授权

US09448811B2 Microprocessor device, and method of managing reset events therefor 有权
标题翻译：微处理器装置以及管理其复位事件的方法
公开(公告)号：US09448811B2
公开(公告)日：2016-09-20
申请号：US14354005
申请日：2011-11-23
申请人： Carl Culshaw , Thomas Luedeke , Nicolas Grossier
发明人： Carl Culshaw , Thomas Luedeke , Nicolas Grossier
IPC分类号： G06F1/24 , G06F9/44 , G06F9/445 , G06F11/07
CPC分类号： G06F9/442 , G06F1/24 , G06F9/44505 , G06F11/0721 , G06F11/076
摘要： A microprocessor device comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event comprising a first reset level, determine if at least one reset condition has been met upon detection of the reset event comprising the first reset level, and cause a reset of a second reset level upon determining that the at least one reset condition has been met.
摘要翻译：微处理器设备包括至少一个复位管理模块。所述至少一个复位管理模块被布置成检测包括第一复位电平的复位事件，确定在检测到包括第一复位电平的复位事件时是否满足了至少一个复位条件，并且引起第二复位的复位确定已经满足至少一个复位条件。

4. 发明授权

US09311206B2 Method and apparatus for monitoring general purpose input output, GPIO, signals 有权
标题翻译：用于监视通用输入输出，GPIO，信号的方法和装置
公开(公告)号：US09311206B2
公开(公告)日：2016-04-12
申请号：US14253399
申请日：2014-04-15
申请人： Carl Culshaw , Mark Maiolani , Robert F. Moran
发明人： Carl Culshaw , Mark Maiolani , Robert F. Moran
IPC分类号： H03M13/00 , G06F11/30 , G11C29/42 , G11C29/02 , G11C29/04
CPC分类号： G06F11/3027 , G11C29/022 , G11C29/42 , G11C2029/0409
摘要： An apparatus and method for monitoring general purpose input output, GPIO, signals at GPIO pins of a GPIO port of a system on chip, SoC. The apparatus comprises a first checksum generation unit adapted to generate a first checksum on the basis of GPIO bits stored in GPIO registers of the SoC, being connected via corresponding input output, IO, pad circuits to provide analog GPIO signals at the GPIO pins. A second checksum generation unit is adapted to generate a second checksum on the basis of the analog GPIO signals at the GPIO pins representing the GPIO bits. Checker logic is adapted to compare the first checksum generated by the first checksum generation unit with a second checksum generated by the second checksum generation unit.
摘要翻译：用于监视芯片系统的GPIO端口的GPIO引脚上的通用输入输出GPIO的信号的装置和方法，SoC。该装置包括第一校验和生成单元，其适于基于存储在SoC的GPIO寄存器中的GPIO位产生第一校验和，其通过相应的输入输出IO，焊盘电路连接，以在GPIO引脚处提供模拟GPIO信号。第二校验和生成单元适于基于表示GPIO位的GPIO引脚处的模拟GPIO信号产生第二校验和。检查器逻辑适于将由第一校验和生成单元生成的第一校验和与由第二校验和生成单元生成的第二校验和进行比较。

5. 发明申请

US20160085279A1 METHOD FOR RESETTING AN ELECTRONIC DEVICE HAVING INDEPENDENT DEVICE DOMAINS 有权
标题翻译：用于复位具有独立设备域的电子设备的方法
公开(公告)号：US20160085279A1
公开(公告)日：2016-03-24
申请号：US14492711
申请日：2014-09-22
申请人： CARL CULSHAW , SUNNY GUPTA , THOMAS HENRY LUEDEKE , DEBOLEENA SAKALLEY
发明人： CARL CULSHAW , SUNNY GUPTA , THOMAS HENRY LUEDEKE , DEBOLEENA SAKALLEY
IPC分类号： G06F1/24
CPC分类号： G06F1/24 , G06F11/0724 , G06F11/14
摘要： A reset state control circuit adapted to reset independent device domains of an electronic device, said reset state control circuit comprising a capturing unit adapted to capture reset events; and a reset shaping logic adapted to change dynamically a reset control flow to reset device domains of said electronic device depending on a sequence of the reset events captured by said capturing unit.
摘要翻译：一种复位状态控制电路，其适于重置电子设备的独立设备域，所述复位状态控制电路包括适于捕获复位事件的捕获单元; 以及复位整形逻辑，其适于根据由所述捕获单元捕获的所述复位事件的顺序动态地改变复位控制流以重置所述电子设备的设备域。

6. 发明申请

US20160033560A1 MODE-CONTROLLED VOLTAGE EXCURSION DETECTOR APPARATUS AND A METHOD OF OPERATING THEREOF 有权
标题翻译：模式控制电压检测装置及其操作方法
公开(公告)号：US20160033560A1
公开(公告)日：2016-02-04
申请号：US14445679
申请日：2014-07-29
申请人： Manfred THANNER , Carl CULSHAW , Sunny GUPTA
发明人： Manfred THANNER , Carl CULSHAW , Sunny GUPTA
IPC分类号： G01R19/165 , G01R19/00
CPC分类号： G01R19/16552
摘要： The present application relates to a mode-controlled voltage excursion detector apparatus for monitoring a supply voltage of a power supply applied to a load and a method of operating thereof. A voltage monitor is configured to detect an excursion event if the supply voltage exceeds or falls below at least one defined threshold, to generate an excursion event signal upon detection of the excursion event and to provide the generated excursion event signal to the excursion event output for being outputted via an excursion event output. A sensitivity control module is configured to receive a signal indicative of potential voltage excursions. A sensitivity control module is further operatively coupled to the sensitivity control input and configured to disable the outputting of an excursion event signal generated during a defined period of time in response to the reception of the signal, which triggers the disabling of the outputting.
摘要翻译：本申请涉及一种用于监视施加到负载的电源的电源电压的模式控制的电压偏移检测器装置及其操作方法。电压监视器被配置为如果电源电压超过或低于至少一个定义的阈值，则检测偏移事件，以便在检测到偏移事件时产生偏移事件信号，并将生成的偏移事件信号提供给偏移事件输出通过偏移事件输出输出。灵敏度控制模块被配置为接收指示潜在电压偏移的信号。灵敏度控制模块进一步可操作地耦合到灵敏度控制输入，并且被配置为响应于触发禁止输出的信号的接收而禁止在限定的时间段内产生的偏移事件信号的输出。

7. 发明申请

US20150293829A1 METHOD AND APPARATUS FOR MONITORING GENERAL PURPOSE INPUT OUTPUT, GPIO, SIGNALS 有权
标题翻译：监控一般用途输入输出，GPIO，信号的方法和装置
公开(公告)号：US20150293829A1
公开(公告)日：2015-10-15
申请号：US14253399
申请日：2014-04-15
申请人： CARL CULSHAW , MARK MAIOLANI , ROBERT F. MORAN
发明人： CARL CULSHAW , MARK MAIOLANI , ROBERT F. MORAN
IPC分类号： G06F11/30 , G11C29/42
CPC分类号： G06F11/3027 , G11C29/022 , G11C29/42 , G11C2029/0409
摘要： An apparatus and method for monitoring general purpose input output, GPIO, signals at GPIO pins of a GPIO port of a system on chip, SoC. The apparatus comprises a first checksum generation unit adapted to generate a first checksum on the basis of GPIO bits stored in GPIO registers of the SoC, being connected via corresponding input output, IO, pad circuits to provide analog GPIO signals at the GPIO pins. A second checksum generation unit is adapted to generate a second checksum on the basis of the analog GPIO signals at the GPIO pins representing the GPIO bits. Checker logic is adapted to compare the first checksum generated by the first checksum generation unit with a second checksum generated by the second checksum generation unit.
摘要翻译：用于监视芯片系统的GPIO端口的GPIO引脚上的通用输入输出GPIO的信号的装置和方法，SoC。该装置包括第一校验和生成单元，其适于基于存储在SoC的GPIO寄存器中的GPIO位产生第一校验和，其通过相应的输入输出IO，焊盘电路连接，以在GPIO引脚处提供模拟GPIO信号。第二校验和生成单元适于基于表示GPIO位的GPIO引脚处的模拟GPIO信号产生第二校验和。检查器逻辑适于将由第一校验和生成单元生成的第一校验和与由第二校验和生成单元生成的第二校验和进行比较。

8. 发明申请

US20130229737A1 INTEGRATED CIRCUIT DEVICE AND METHOD FOR DETECTING AN EXCESSIVE VOLTAGE STATE 有权
标题翻译：集成电路装置和检测过电压状态的方法
公开(公告)号：US20130229737A1
公开(公告)日：2013-09-05
申请号：US13880193
申请日：2010-11-22
申请人： Alistair Robertson , Carl Culshaw , Alan Devine
发明人： Alistair Robertson , Carl Culshaw , Alan Devine
IPC分类号： H02H3/20 , G01R19/00 , H03M1/12
CPC分类号： H02H3/20 , G01R19/0084 , G01R19/165 , H03M1/12 , H03M1/129
摘要： An integrated circuit device comprising at least one analogue to digital converter. The at least one ADC comprises at least one input operably coupled to at least one external contact of the integrated circuit device. The integrated circuit device further comprises detection circuitry comprising at least one detection module. The at least one detection module being arranged to receive at a first input thereof an indication of a voltage level at the at least one input of the at least one ADC, compare the received indication to a threshold value, and if the received indication exceeds the threshold value, output an indication that an excessive voltage state at the at least one input of the at least one ADC has been detected.
摘要翻译：一种包括至少一个模数转换器的集成电路装置。至少一个ADC包括可操作地耦合到集成电路器件的至少一个外部触点的至少一个输入。集成电路装置还包括检测电路，其包括至少一个检测模块。所述至少一个检测模块被布置为在其第一输入处接收所述至少一个ADC的至少一个输入端的电压电平的指示，将所接收的指示与阈值进行比较，并且如果所接收的指示超过输出在至少一个ADC的至少一个输入处已经检测到过电压状态的指示。

9. 发明授权

US09846663B2 Method of controlling direct memory access of a peripheral memory of a peripheral by a master, an associated circuitry, an associated device and an associated computer program product 有权
公开(公告)号：US09846663B2
公开(公告)日：2017-12-19
申请号：US14778115
申请日：2013-03-22
申请人： Alistair Roberston , Carl Culshaw , Alan Devine
发明人： Alistair Roberston , Carl Culshaw , Alan Devine
IPC分类号： G06F13/28 , G06F13/364 , G06F13/42
CPC分类号： G06F13/28 , G06F13/364 , G06F13/4282
摘要： A method of controlling direct memory access of a peripheral memory of a peripheral by a master is described. The method includes checking whether there is a pending request from the peripheral for a direct memory access service, establishing whether an access condition is satisfied in dependence on at least whether there is a pending request, and, if the access condition is satisfied, granting access to the master. Also, an associated device and an associated computer program product are described.

10. 发明授权

US09823296B2 Built-in self test system, system on a chip and method for controlling built-in self tests 有权
公开(公告)号：US09823296B2
公开(公告)日：2017-11-21
申请号：US14402949
申请日：2012-06-07
申请人： Manfred Thanner , Carl Culshaw , Juergen Frank , Michael Staudenmaier
发明人： Manfred Thanner , Carl Culshaw , Juergen Frank , Michael Staudenmaier
IPC分类号： G01R31/3187 , G01R31/28 , G01R31/317
CPC分类号： G01R31/2856 , G01R31/31701 , G01R31/31721
摘要： A built-in self test system comprises an integrated circuit device comprising a plurality of functional units coupled to built-in self test circuitry; a low power control unit operable to switch the integrated circuit device into a low power mode and to generate a BIST wake-up signal during or before entering the low power mode; and a built-in self test control unit coupled to the built-in self test circuitry and the low power control unit and arranged to initiate a built-in self test when receiving the BIST wake-up signal.

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