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1. 发明授权

US10489612B2 Memory controller to verify authenticity of data 有权
公开(公告)号：US10489612B2
公开(公告)日：2019-11-26
申请号：US14784038
申请日：2013-04-29
申请人： Juergen Frank , Michael Staudenmaier , Manfred Thanner
发明人： Juergen Frank , Michael Staudenmaier , Manfred Thanner
IPC分类号： G06F21/79 , G06F21/57 , G06F12/02 , G06F12/14 , G06F21/44 , G06F21/62 , G06F21/64
CPC分类号： G06F21/79 , G06F12/0246 , G06F12/1458 , G06F21/44 , G06F21/572 , G06F21/6218 , G06F21/64 , G06F2212/1052
摘要： A memory controller is used to verify authenticity of data stored in a first memory unit, and includes a secure memory unit which stores a pre-stored value representative of the authenticity of the data to be written in the first memory unit. A processing system calculates a value representative of the data in the first memory unit after a write cycle. The calculation of the calculated value is triggered by the write cycle. The calculated value is compared with the pre-stored value to verify whether the data stored in the first memory unit after the write cycle has been altered in accordance with the authenticity. By comparing the calculated value with the pre-stored value, authenticity of the data stored in the first memory unit after the write cycle is verified, thus preventing the memory controller from operating if the data written to the first memory unit is not authentic.

2. 发明授权

US09894084B2 Illegal message destroyer 有权
公开(公告)号：US09894084B2
公开(公告)日：2018-02-13
申请号：US14898779
申请日：2013-07-18
申请人： Juergen Frank , Michael Staudenmaier , Manfred Thanner
发明人： Juergen Frank , Michael Staudenmaier , Manfred Thanner
IPC分类号： H04L29/06 , H04L12/40 , G06F21/60
CPC分类号： H04L63/1416 , G06F21/606 , H04L12/40032 , H04L12/40169 , H04L63/10 , H04L63/12 , H04L63/1466 , H04L2012/40215 , H04L2012/40273
摘要： A communication apparatus for preventing the broadcasting of unauthorized messages on a broadcast bus network, the communication apparatus comprising: a first memory adapted to store first information; a second memory adapted to store second information; a monitoring unit adapted to: monitor the bus for processing messages being broadcasted on the bus, and output a third information and fourth information a comparing unit adapted to compare the first information with the third information and the second information with the fourth information; and, a message destroyer adapted to: when: the first information matches with the third information, and the second information does not match with the fourth information, causing the body of the current message to be altered while the current message is being broadcasted on the bus.

3. 发明授权

US09798901B2 Device having a security module 有权
公开(公告)号：US09798901B2
公开(公告)日：2017-10-24
申请号：US14786558
申请日：2013-04-30
申请人： Juergen Frank , Michael Staudenmaier , Manfred Thanner
发明人： Juergen Frank , Michael Staudenmaier , Manfred Thanner
IPC分类号： H04L29/00 , G06F21/79 , G06F21/85 , G06F12/14 , G06F12/02
CPC分类号： G06F21/79 , G06F12/0223 , G06F12/1408 , G06F21/85 , G06F2212/1052
摘要： A device securely accesses data in a memory via an addressing unit which provides a memory interface for interfacing to a memory, a core interface for interfacing to a core processor and a first and second security interface. The device includes a security processor HSM for performing at least one security operation on the data and a remapping unit MMAP. The remapping unit enables the security processor to be accessed by the core processor via the first security interface and to access the memory device via the second security interface according to a remapping structure for making accessible processed data based on memory data. The device provides a clear view on encrypted memory data without requiring system memory for storing the clear data.

4. 发明申请

US20160149934A1 ILLEGAL MESSAGE DESTROYER 有权
标题翻译：非法消息破坏者
公开(公告)号：US20160149934A1
公开(公告)日：2016-05-26
申请号：US14898779
申请日：2013-07-18
申请人： Juergen FRANK , Michael STAUDEN-MAIER , Manfred THANNER , FREESCALE SEMICONDUCTOR, INC.
发明人： JUERGEN FRANK , MICHAEL STAUDENMAIER , MANFRED THANNER
IPC分类号： H04L29/06
CPC分类号： H04L63/1416 , G06F21/606 , H04L12/40032 , H04L12/40169 , H04L63/10 , H04L63/12 , H04L63/1466 , H04L2012/40215 , H04L2012/40273
摘要： A communication apparatus for preventing the broadcasting of unauthorised messages on a broadcast bus network, the communication apparatus comprising: a first memory adapted to store first information; a second memory adapted to store second information; a monitoring unit adapted to: monitor the bus for processing messages being broadcasted on the bus, and output a third information and fourth information a comparing unit adapted to compare the first information with the third information and the second information with the fourth information; and, a message destroyer adapted to: when: the first information matches with the third information, and the second information does not match with the fourth information, causing the body of the current message to be altered while the current message is being broadcasted on the bus.
摘要翻译：一种用于防止在广播总线网络上广播未经授权的消息的通信装置，所述通信装置包括：适于存储第一信息的第一存储器; 适于存储第二信息的第二存储器; 监视单元，适于：监视总线，以处理在总线上广播的消息，并输出第三信息和第四信息;比较单元，适于将第一信息与第三信息和第二信息与第四信息进行比较; 以及消息驱逐器，其适于：何时：所述第一信息与所述第三信息匹配，并且所述第二信息与所述第四信息不匹配，导致当前消息的主体在当前消息在总线。

5. 发明授权

US09342258B2 Integrated circuit device and method for providing data access control 有权
标题翻译：用于提供数据访问控制的集成电路装置和方法
公开(公告)号：US09342258B2
公开(公告)日：2016-05-17
申请号：US14238495
申请日：2011-09-01
申请人： Manfred Thanner , Nancy Amedeo , Stephan Mueller , Anthony Reipold
发明人： Manfred Thanner , Nancy Amedeo , Stephan Mueller , Anthony Reipold
IPC分类号： G06F3/00 , G06F3/06 , G06F12/08 , G06F13/16
CPC分类号： G06F3/0656 , G06F3/0611 , G06F3/0671 , G06F12/0862 , G06F13/1673 , G06F2212/6022
摘要： An integrated circuit device comprising at least one memory interface module arranged to be operably coupled between at least one data storage device and a plurality of master devices within a data processing system. The at least one memory interface module comprises a plurality of buffers and at least one data access control module. The at least one data access control module being arranged to fetch data from the at least one data storage device in response to a received memory access request comprising a master device identifier, select at least one buffer based at least partly on the master device identifier of the received access request, and load the fetched data into the selected at least one buffer.
摘要翻译：一种集成电路装置，包括至少一个存储器接口模块，其布置成可操作地耦合在数据处理系统内的至少一个数据存储设备和多个主设备之间。所述至少一个存储器接口模块包括多个缓冲器和至少一个数据访问控制模块。所述至少一个数据访问控制模块被布置成响应于包括主设备标识符的接收到的存储器访问请求从所述至少一个数据存储设备提取数据，至少部分地基于所述主设备标识符来选择至少一个缓冲器所接收的访问请求，并将获取的数据加载到所选择的至少一个缓冲器中。

6. 发明授权

US08589737B2 Memory system with redundant data storage and error correction 有权
标题翻译：具有冗余数据存储和纠错的存储系统
公开(公告)号：US08589737B2
公开(公告)日：2013-11-19
申请号：US12995297
申请日：2008-06-20
申请人： Michael Rohleder , Gary Hay , Stephan Mueller , Manfred Thanner
发明人： Michael Rohleder , Gary Hay , Stephan Mueller , Manfred Thanner
IPC分类号： G06F11/00
CPC分类号： G06F11/167 , G11C29/74 , G11C2029/0411
摘要： A system comprises at least two random access memory (RAM) elements arranged to store data redundantly. The system further comprises RAM routing logic comprising comparison logic operably coupled to the at least two RAM elements and arranged to compare redundant data read from the at least two RAM elements, and check and validation logic, independent of the RAM routing logic, operably coupled to the at least two RAM elements and arranged to additionally detect an error in the redundant data read from the at least two RAM elements and provide an error indication signal to the RAM routing logic in response thereto. The RAM routing logic further comprises selection logic arranged to dynamically select redundant data from one of the at least two RAM elements based on the comparison of the redundant data and the error indication signal.
摘要翻译：系统包括被布置为冗余地存储数据的至少两个随机存取存储器（RAM）元件。所述系统还包括RAM路由逻辑，其包括可操作地耦合到所述至少两个RAM元件的比较逻辑，并且被布置为比较从所述至少两个RAM元素读取的冗余数据，以及独立于所述RAM路由逻辑的检查和验证逻辑，其可操作地耦合到所述至少两个RAM元件并且被布置为附加地检测从所述至少两个RAM元素读取的冗余数据中的错误，并且响应于此向RAM路由逻辑提供错误指示信号。 RAM路由逻辑还包括选择逻辑，其被布置为基于冗余数据和错误指示信号的比较来动态地从至少两个RAM元素中的一个RAM元素中选择冗余数据。

7. 发明申请

US20100287443A1 PROCESSOR BASED SYSTEM HAVING ECC BASED CHECK AND ACCESS VALIDATION INFORMATION MEANS 有权
标题翻译：基于ECC的基于处理器的系统检查和访问验证信息手段
公开(公告)号：US20100287443A1
公开(公告)日：2010-11-11
申请号：US12811454
申请日：2008-01-16
申请人： Michael Rohleder , Gary Hay , Stephan Mueller , Manfred Thanner
发明人： Michael Rohleder , Gary Hay , Stephan Mueller , Manfred Thanner
IPC分类号： H03M13/09 , G06F13/40
CPC分类号： G06F11/1645 , G06F11/10 , G06F11/1654 , G06F2201/845
摘要： A system comprises a first master element; and at least one shared communication element arranged to operably couple the first master element to at least one slave element. The system further comprises at least one validation element located on at least one further validation path located between the first master element and the at least one slave element, wherein the at least one validation element is arranged to validate at least one of: at least one access request by the first master element; and a response to an access request from the at least one slave element.
摘要翻译：一种系统包括第一主元件; 以及布置成将第一主元件可操作地耦合到至少一个从属元件的至少一个共享通信元件。所述系统还包括位于位于所述第一主元件和所述至少一个从属元件之间的至少一个另外的验证路径上的至少一个验证元件，其中所述至少一个验证元件被布置成验证以下至少一个：至少一个由第一个主元素访问请求; 以及对来自所述至少一个从属单元的访问请求的响应。

8. 发明申请

US20160033560A1 MODE-CONTROLLED VOLTAGE EXCURSION DETECTOR APPARATUS AND A METHOD OF OPERATING THEREOF 有权
标题翻译：模式控制电压检测装置及其操作方法
公开(公告)号：US20160033560A1
公开(公告)日：2016-02-04
申请号：US14445679
申请日：2014-07-29
申请人： Manfred THANNER , Carl CULSHAW , Sunny GUPTA
发明人： Manfred THANNER , Carl CULSHAW , Sunny GUPTA
IPC分类号： G01R19/165 , G01R19/00
CPC分类号： G01R19/16552
摘要： The present application relates to a mode-controlled voltage excursion detector apparatus for monitoring a supply voltage of a power supply applied to a load and a method of operating thereof. A voltage monitor is configured to detect an excursion event if the supply voltage exceeds or falls below at least one defined threshold, to generate an excursion event signal upon detection of the excursion event and to provide the generated excursion event signal to the excursion event output for being outputted via an excursion event output. A sensitivity control module is configured to receive a signal indicative of potential voltage excursions. A sensitivity control module is further operatively coupled to the sensitivity control input and configured to disable the outputting of an excursion event signal generated during a defined period of time in response to the reception of the signal, which triggers the disabling of the outputting.
摘要翻译：本申请涉及一种用于监视施加到负载的电源的电源电压的模式控制的电压偏移检测器装置及其操作方法。电压监视器被配置为如果电源电压超过或低于至少一个定义的阈值，则检测偏移事件，以便在检测到偏移事件时产生偏移事件信号，并将生成的偏移事件信号提供给偏移事件输出通过偏移事件输出输出。灵敏度控制模块被配置为接收指示潜在电压偏移的信号。灵敏度控制模块进一步可操作地耦合到灵敏度控制输入，并且被配置为响应于触发禁止输出的信号的接收而禁止在限定的时间段内产生的偏移事件信号的输出。

9. 发明申请

US20150310229A1 SYSTEM ON CHIP 有权
标题翻译：芯片系统
公开(公告)号：US20150310229A1
公开(公告)日：2015-10-29
申请号：US14647089
申请日：2012-11-23
申请人： ROHLEDER MICHAEL , Stefan SINGER , Manfred THANNER
发明人： MICHAEL ROHLEDER , STEFAN SINGER , MANFRED THANNER
IPC分类号： G06F21/71 , G06F21/62
CPC分类号： G06F21/71 , G06F21/6218 , G06F21/74 , G06F21/78 , G06F2217/66 , H04L63/105
摘要： A system on chip having two or more responder units and two or more protection units is provided. Each of the responder units comprises a set of responder elements. Each of the protection units is associated with and protects one of the responder units and is arranged to provide a group mapping. The group mapping assigns one or more group identifiers to each of the responder elements of the respective responder unit.
摘要翻译：提供了具有两个或更多个响应器单元和两个或更多个保护单元的片上系统。每个响应者单元包括一组响应者元素。每个保护单元与响应器单元中的一个相关联并且保护其中的一个，并且被布置成提供组映射。组映射将一个或多个组标识符分配给各个响应器单元的每个应答器元件。

10. 发明授权

US09152511B2 System for dynamically distributing an available memory resource to redundant and non-redundant storage areas using RAM routing logic 有权
标题翻译：使用RAM路由逻辑将可用内存资源动态分配到冗余和非冗余存储区域的系统
公开(公告)号：US09152511B2
公开(公告)日：2015-10-06
申请号：US12995317
申请日：2008-06-20
申请人： Michael Rohleder , Gary Hay , Stephan Mueller , Manfred Thanner
发明人： Michael Rohleder , Gary Hay , Stephan Mueller , Manfred Thanner
IPC分类号： G06F11/16 , G11C29/26 , G11C29/00 , G11C7/10 , G11C29/04
CPC分类号： G06F11/1666 , G06F11/1629 , G06F11/167 , G06F2201/845 , G11C7/1075 , G11C29/74 , G11C2029/0411
摘要： A system for distributing an available memory resource comprising at least two random access memory (RAM) elements and RAM routing logic. The RAM routing logic comprises configuration logic to dynamically distribute the available memory resource into a first memory area providing redundant memory storage and a second memory area providing non-redundant memory storage. The system may further comprise bus access ports which support at least one of concurrent access by a bus access port to access redundantly stored data or non-redundantly stored data, or concurrent access by at least two bus access ports to respective RAM elements to access redundantly stored data or to a respective one of the RAM elements to access non-redundantly stored data. Comparison logic and error detection or correction logic may be provided to detect or correct errors in information read from the RAM elements.
摘要翻译：一种用于分发包括至少两个随机存取存储器（RAM）元件和RAM路由逻辑的可用存储器资源的系统。 RAM路由逻辑包括用于动态地将可用存储器资源分配到提供冗余存储器存储器的第一存储器区域和提供非冗余存储器存储器的第二存储器区域的配置逻辑。该系统还可以包括总线访问端口，其支持总线访问端口的并发访问中的至少一个以访问冗余存储的数据或非冗余存储的数据，或者由至少两个总线访问端口到相应的RAM元件的并发访问以冗余访问存储数据或RAM元素中的相应一个以访问非冗余存储的数据。可以提供比较逻辑和错误检测或校正逻辑来检测或纠正从RAM元件读取的信息中的错误。

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