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1. 发明授权

US09417795B2 System performance control component and method therefor 有权
标题翻译：系统性能控制组件及其方法
公开(公告)号：US09417795B2
公开(公告)日：2016-08-16
申请号：US14261589
申请日：2014-04-25
申请人： Mark Maiolani , Gordon James Campbell , Carl Culchaw , Alistair James Gorman , David McMenamin
发明人： Mark Maiolani , Gordon James Campbell , Carl Culchaw , Alistair James Gorman , David McMenamin
IPC分类号： G06F3/06
CPC分类号： G06F3/0604 , G06F1/32 , G06F1/3206 , G06F1/324 , G06F1/3296 , G06F3/0629 , G06F3/0673 , G06F9/00 , G06F11/34 , G06F11/3648 , G06F13/00 , Y02D10/126 , Y02D10/172
摘要： A system performance control component, and method therefor, for configuring at least one system performance parameter within a signal processing system. The system performance control component is arranged to receive an indication of an address of a memory access performed by at least one signal processing component, compare the received indication of an address of a memory access to at least one address value, and configure at least one system performance parameter based at least partly on the comparison of the received indication of an address of a memory access to at least one address value.
摘要翻译：一种系统性能控制部件及其方法，用于在信号处理系统内配置至少一个系统性能参数。系统性能控制部件被布置为接收由至少一个信号处理部件执行的存储器访问的地址的指示，将接收到的存储器访问的指示与至少一个地址值进行比较，并配置至少一个系统性能参数至少部分地基于存储器访问的地址的接收指示与至少一个地址值的比较。

2. 发明授权

US6101125A Electrically programmable memory and method of programming 失效
标题翻译：电可编程存储器和编程方法
公开(公告)号：US6101125A
公开(公告)日：2000-08-08
申请号：US82213
申请日：1998-05-20
申请人： Alistair James Gorman
发明人： Alistair James Gorman
IPC分类号： G11C11/56 , G11C16/10 , G11C16/24 , G11C16/34 , G11C16/04
CPC分类号： G11C16/3459 , G11C11/5621 , G11C11/5628 , G11C16/10 , G11C16/24 , G11C16/3454 , G11C2211/5621
摘要： An electrically programmable memory having floating gate FET cells (10.2) each having a drain electrode (10.10), and a source electrode (10.8); a first voltage source for applying simultaneously to one of the drain and source electrodes of a plurality of cells of the memory a first voltage (AGND)for a programming time, the first voltage being selectable so as to determine the multi-level value programmed into the cell, thereby allowing simultaneous multi-level programming of the plurality of cells; a voltage pluse source for applying to the other of the drain and source electrodes of the plurality of cells a succession of voltage pulses (Vpp) during the programming time; and a programming determiner for determining after each of the succession of the voltage pulses whether the cell is programmed to a desired value.
摘要翻译：一种电可编程存储器，具有分别具有漏电极（10.10）和源电极（10.8）的浮置FET FET单元（10.2）。第一电压源，用于同时施加存储器的多个单元的漏极和源极之一用于编程时间的第一电压（AGND），所述第一电压是可选择的，以便确定被编程为从而允许多个小区的同时多级编程; 用于在编程时间期间向多个单元的另一个漏极和源极施加一系列电压脉冲（Vpp）的电压源; 以及编程确定器，用于在所述一连串电压脉冲中的每一个之后确定所述单元是否被编程为期望值。

3. 发明授权

US09759765B2 Input/output cell, integrated circuit device and methods of providing on-chip test functionality 有权
公开(公告)号：US09759765B2
公开(公告)日：2017-09-12
申请号：US14288510
申请日：2014-05-28
申请人： Alistair James Gorman , Carl Culshaw , Josef Maria Joachim Kruecken
发明人： Alistair James Gorman , Carl Culshaw , Josef Maria Joachim Kruecken
IPC分类号： G01R31/28 , H03K17/687 , G01R31/317
CPC分类号： G01R31/2856 , G01R31/31715 , H03K17/687 , H03K2217/0063 , H03K2217/0072
摘要： An I/O cell comprising a first set of driver stages comprising, each driver stage of the first set comprising a high side switch controllable to couple an I/O node of the I/O cell to a first high voltage supply node and a low side switch controllable to couple the I/O node of the I/O cell to a first low voltage supply node. The I/O cell further comprising a second set of driver stages, each driver stage of the second set comprising a high side switch controllable to couple the I/O node of the I/O cell to a second high voltage supply node and a low side switch controllable to couple the I/O node of the I/O cell to a second low voltage supply node. The switches of the first set of driver stages are controllable independently of the switches of the second set of driver stages.

4. 发明申请

US20150346274A1 INPUT/OUTPUT CELL, INTEGRATED CIRCUIT DEVICE AND METHODS OF PROVIDING ON-CHIP TEST FUNCTIONALITY 有权
标题翻译：输入/输出单元，集成电路设备及提供芯片测试功能的方法
公开(公告)号：US20150346274A1
公开(公告)日：2015-12-03
申请号：US14288510
申请日：2014-05-28
申请人： ALISTAIR JAMES GORMAN , CARL CULSHAW , JOSEF MARIA JOACHIM KRUECKEN
发明人： ALISTAIR JAMES GORMAN , CARL CULSHAW , JOSEF MARIA JOACHIM KRUECKEN
IPC分类号： G01R31/28 , H03K17/687
CPC分类号： G01R31/2856 , G01R31/31715 , H03K17/687 , H03K2217/0063 , H03K2217/0072
摘要： An I/O cell comprising a first set of driver stages comprising, each driver stage of the first set comprising a high side switch controllable to couple an I/O node of the I/O cell to a first high voltage supply node and a low side switch controllable to couple the I/O node of the I/O cell to a first low voltage supply node. The I/O cell further comprising a second set of driver stages, each driver stage of the second set comprising a high side switch controllable to couple the I/O node of the I/O cell to a second high voltage supply node and a low side switch controllable to couple the I/O node of the I/O cell to a second low voltage supply node. The switches of the first set of driver stages are controllable independently of the switches of the second set of driver stages.
摘要翻译：包括第一组驱动级的I / O单元，包括：第一组的每个驱动级包括可控制以将I / O单元的I / O节点耦合到第一高电压供应节点的高侧开关，以及低侧开关可控制以将I / O单元的I / O节点耦合到第一低电压电源节点。所述I / O单元还包括第二组驱动级，所述第二组的每个驱动级包括可控制以将所述I / O单元的I / O节点耦合到第二高电压供应节点的高侧开关和低侧开关可控制以将I / O单元的I / O节点耦合到第二低电压电源节点。第一组驱动级的开关可以独立于第二组驱动级的开关来控制。

5. 发明申请

US20150309730A1 SYSTEM PERFORMANCE CONTROL COMPONENT AND METHOD THEREFOR 有权
标题翻译：系统性能控制组件及其方法
公开(公告)号：US20150309730A1
公开(公告)日：2015-10-29
申请号：US14261589
申请日：2014-04-25
申请人： MARK MAIOLANI , GORDON JAMES CAMPBELL , CARL CULSHAW , ALISTAIR JAMES GORMAN , DAVID MCMENAMIN
发明人： MARK MAIOLANI , GORDON JAMES CAMPBELL , CARL CULSHAW , ALISTAIR JAMES GORMAN , DAVID MCMENAMIN
IPC分类号： G06F3/06
CPC分类号： G06F3/0604 , G06F1/32 , G06F1/3206 , G06F1/324 , G06F1/3296 , G06F3/0629 , G06F3/0673 , G06F9/00 , G06F11/34 , G06F11/3648 , G06F13/00 , Y02D10/126 , Y02D10/172
摘要： A system performance control component, and method therefor, for configuring at least one system performance parameter within a signal processing system. The system performance control component is arranged to receive an indication of an address of a memory access performed by at least one signal processing component, compare the received indication of an address of a memory access to at least one address value, and configure at least one system performance parameter based at least partly on the comparison of the received indication of an address of a memory access to at least one address value.
摘要翻译：一种系统性能控制部件及其方法，用于在信号处理系统内配置至少一个系统性能参数。系统性能控制部件被布置为接收由至少一个信号处理部件执行的存储器访问的地址的指示，将接收到的存储器访问的指示与至少一个地址值进行比较，并配置至少一个系统性能参数至少部分地基于存储器访问的地址的接收指示与至少一个地址值的比较。

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