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1. 发明申请

US20150293829A1 METHOD AND APPARATUS FOR MONITORING GENERAL PURPOSE INPUT OUTPUT, GPIO, SIGNALS 有权
标题翻译：监控一般用途输入输出，GPIO，信号的方法和装置
公开(公告)号：US20150293829A1
公开(公告)日：2015-10-15
申请号：US14253399
申请日：2014-04-15
申请人： CARL CULSHAW , MARK MAIOLANI , ROBERT F. MORAN
发明人： CARL CULSHAW , MARK MAIOLANI , ROBERT F. MORAN
IPC分类号： G06F11/30 , G11C29/42
CPC分类号： G06F11/3027 , G11C29/022 , G11C29/42 , G11C2029/0409
摘要： An apparatus and method for monitoring general purpose input output, GPIO, signals at GPIO pins of a GPIO port of a system on chip, SoC. The apparatus comprises a first checksum generation unit adapted to generate a first checksum on the basis of GPIO bits stored in GPIO registers of the SoC, being connected via corresponding input output, IO, pad circuits to provide analog GPIO signals at the GPIO pins. A second checksum generation unit is adapted to generate a second checksum on the basis of the analog GPIO signals at the GPIO pins representing the GPIO bits. Checker logic is adapted to compare the first checksum generated by the first checksum generation unit with a second checksum generated by the second checksum generation unit.
摘要翻译：用于监视芯片系统的GPIO端口的GPIO引脚上的通用输入输出GPIO的信号的装置和方法，SoC。该装置包括第一校验和生成单元，其适于基于存储在SoC的GPIO寄存器中的GPIO位产生第一校验和，其通过相应的输入输出IO，焊盘电路连接，以在GPIO引脚处提供模拟GPIO信号。第二校验和生成单元适于基于表示GPIO位的GPIO引脚处的模拟GPIO信号产生第二校验和。检查器逻辑适于将由第一校验和生成单元生成的第一校验和与由第二校验和生成单元生成的第二校验和进行比较。

2. 发明申请

US20150309730A1 SYSTEM PERFORMANCE CONTROL COMPONENT AND METHOD THEREFOR 有权
标题翻译：系统性能控制组件及其方法
公开(公告)号：US20150309730A1
公开(公告)日：2015-10-29
申请号：US14261589
申请日：2014-04-25
申请人： MARK MAIOLANI , GORDON JAMES CAMPBELL , CARL CULSHAW , ALISTAIR JAMES GORMAN , DAVID MCMENAMIN
发明人： MARK MAIOLANI , GORDON JAMES CAMPBELL , CARL CULSHAW , ALISTAIR JAMES GORMAN , DAVID MCMENAMIN
IPC分类号： G06F3/06
CPC分类号： G06F3/0604 , G06F1/32 , G06F1/3206 , G06F1/324 , G06F1/3296 , G06F3/0629 , G06F3/0673 , G06F9/00 , G06F11/34 , G06F11/3648 , G06F13/00 , Y02D10/126 , Y02D10/172
摘要： A system performance control component, and method therefor, for configuring at least one system performance parameter within a signal processing system. The system performance control component is arranged to receive an indication of an address of a memory access performed by at least one signal processing component, compare the received indication of an address of a memory access to at least one address value, and configure at least one system performance parameter based at least partly on the comparison of the received indication of an address of a memory access to at least one address value.
摘要翻译：一种系统性能控制部件及其方法，用于在信号处理系统内配置至少一个系统性能参数。系统性能控制部件被布置为接收由至少一个信号处理部件执行的存储器访问的地址的指示，将接收到的存储器访问的指示与至少一个地址值进行比较，并配置至少一个系统性能参数至少部分地基于存储器访问的地址的接收指示与至少一个地址值的比较。

3. 发明申请

US20160180891A1 SEMICONDUCTOR WAFER AND METHOD OF FABRICATING AN IC DIE 有权
标题翻译：半导体晶圆和制造IC芯片的方法
公开(公告)号：US20160180891A1
公开(公告)日：2016-06-23
申请号：US14574597
申请日：2014-12-18
申请人： ROBERT F. MORAN , DEREK BEATTIE , MARK MAIOLANI
发明人： ROBERT F. MORAN , DEREK BEATTIE , MARK MAIOLANI
IPC分类号： G11C5/02 , G11C8/10 , H01L23/528 , H01L21/82 , H01L27/02 , G11C5/06 , G11C7/10
CPC分类号： G11C5/025 , G11C5/066 , G11C7/10 , G11C7/1003 , H01L21/82 , H01L23/528 , H01L25/0657 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： There is provided a semiconductor wafer comprising a plurality of replicated IC modules. Each replicated IC module is capable of forming an individual IC die. The semiconductor wafer further comprises inter-module cross-wafer electrical connections, and the replicated IC modules are further arranged to be cut into IC dies comprising multiple replicated IC modules.There is further provided a method of fabricating an IC die. The method comprises fabricating such a semiconductor wafer, determining a required configuration of replicated IC modules, identifying inter-module boundaries along which to cut the semiconductor wafer to achieve the required configuration of replicated IC modules, and cutting the semiconductor wafer along the identified inter-module boundaries to produce at least one IC die comprising the required configuration of replicated IC modules.
摘要翻译：提供了包括多个复制IC模块的半导体晶片。每个复制的IC模块能够形成单个IC芯片。半导体晶片还包括模块间晶片间电连接，并且复制IC模块还被布置成被切割成包括多个复制IC模块的IC模具。还提供了一种制造IC芯片的方法。该方法包括制造这样的半导体晶片，确定复制IC模块的所需配置，识别沿其切割半导体晶片以实现复制IC模块所需配置的模块间边界，以及沿着所识别的间隔区切割半导体晶片，模块边界以产生至少一个包含复制IC模块所需配置的IC芯片。

4. 发明申请

US20160132093A1 METHOD AND APPARATUS FOR CONTROLLING AN OPERATING MODE OF A PROCESSING MODULE 有权
标题翻译：用于控制处理模块的操作模式的方法和装置
公开(公告)号：US20160132093A1
公开(公告)日：2016-05-12
申请号：US14899190
申请日：2013-07-09
申请人： Mark MAIOLANI , Joseph CELLO , Ray MARSHALL
发明人： MARK MAIOLANI , JOSEPH CIRCELLO , RAY MARSHALL
IPC分类号： G06F1/32 , G06F9/48 , G05B15/02
CPC分类号： G06F1/3234 , G05B15/02 , G06F1/3228 , G06F1/3287 , G06F1/329 , G06F1/3293 , G06F9/4893 , G06F13/14 , Y02D10/122 , Y02D10/171 , Y02D10/24 , Y02D50/20
摘要： A method of controlling an operating mode of at least one processing module. The method comprises receiving an indication of the execution of at least one background task by the at least one processing module, aggregating an execution duration for the at least one background task on the at least one processing module, and configuring a lower power mode for the at least one processing module when the at least one background task is allocated to the at least one processing module for execution thereon if the aggregated execution duration for the at least one background task exceeds a threshold duration within an evaluation period.
摘要翻译：一种控制至少一个处理模块的操作模式的方法。该方法包括：接收由至少一个处理模块执行至少一个后台任务的指示，在至少一个处理模块上聚合至少一个后台任务的执行持续时间，以及为该至少一个处理模块配置较低功率模式当所述至少一个后台任务的所述聚合的执行持续时间超过所述评估周期内的阈值持续时间时，所述至少一个后台任务被分配给所述至少一个处理模块以执行其上的至少一个处理模块。

5. 发明申请

US20150356016A1 METHOD OF ESTABLISHING PRE-FETCH CONTROL INFORMATION FROM AN EXECUTABLE CODE AND AN ASSOCIATED NVM CONTROLLER, A DEVICE, A PROCESSOR SYSTEM AND COMPUTER PROGRAM PRODUCTS 有权
标题翻译：从可执行代码和相关的NVM控制器，设备，处理器系统和计算机程序产品建立预控制信息的方法
公开(公告)号：US20150356016A1
公开(公告)日：2015-12-10
申请号：US14759206
申请日：2013-01-11
申请人： ALISTAIR ROBERTSON , NANCY AMEDEO , MARK MAIOLANI
发明人： ALISTAIR ROBERTSON , NANCY AMEDEO , MARK MAIOLANI
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G06F12/0862 , G06F9/30054 , G06F9/3802 , G06F9/3814 , G06F12/00 , G06F12/0246 , G06F12/0873 , G06F2212/461 , G06F2212/6026 , G06F2212/6028 , G06F2212/7201
摘要： A method of establishing pre-fetch control information from an executable code is described. The method comprises inspecting the executable code to find one or more instructions corresponding to an unconditional change in program flow during an execution of the executable code when the executable code is retrieved from a non-volatile memory [NVM] comprising a plurality of NVM lines. For each unconditional change of flow instruction in the executable code, the method comprises establishing a NVM line address of the NVM line containing said unconditional change of flow instruction; establishing a destination address associated with the unconditional change of flow instruction; determining whether the destination address is in an address range corresponding to a NVM-pre-fetch starting from said NVM line address; establishing a pre-fetch flag indicating whether the destination address is in the address range corresponding to a NVM-pre-fetch starting from said NVM line address; and recording the pre-fetch flag in a pre-fetch control information record. Also, a NVM controller, a device, a processor system and computer program products are described.
摘要翻译：描述了从可执行代码建立预取控制信息的方法。该方法包括：当从包括多个NVM线的非易失性存储器（NVM）检索可执行代码时，检查可执行代码以查找在执行可执行代码期间对应于程序流的无条件改变的一个或多个指令。对于可执行代码中的每个无条件改变流程指令，该方法包括建立包含所述无条件流动指令改变的NVM行的NVM行地址; 建立与无条件改变流程指令相关联的目标地址; 确定所述目的地址是否处于从所述NVM行地址开始的NVM预取对应的地址范围内; 建立指示目的地地址是否在与从NVM线地址开始的NVM预取相对应的地址范围内的预取标志; 并将预取标志记录在预取控制信息记录中。此外，还描述了NVM控制器，设备，处理器系统和计算机程序产品。

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