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1. 发明授权

US09024663B2 Clock glitch detection circuit 有权
标题翻译：时钟毛刺检测电路
公开(公告)号：US09024663B2
公开(公告)日：2015-05-05
申请号：US14015519
申请日：2013-08-30
申请人： Michael Rohleder , Thomas Koch , Vladimir Litovtchenko , Thomas Luedeke
发明人： Michael Rohleder , Thomas Koch , Vladimir Litovtchenko , Thomas Luedeke
IPC分类号： H03K5/19 , H03K9/06 , G06F1/04 , H03K5/1252
CPC分类号： G06F1/04 , H03K5/1252
摘要： In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least a particular number of clock edges. A comparator determines whether the difference between the master count and the slave count is at least a value of the incrementer times the particular number of clock edges.
摘要翻译：在用于检测时钟信号中的时钟毛刺的第一电路中，主计数器由时钟信号计时，并存储主计数。增量器将主计数递增一个增量。从计数器由时钟信号计时，并存储从计数。从计数相对于主计数延迟至少一定数量的时钟沿。比较器确定主计数和从计数之间的差是否至少是递增器的值乘以特定数量的时钟边沿。

2. 发明授权

US08214722B2 Method and system for signal error determination and correction in a flexray communication system 有权
标题翻译：柔性通信系统信号误差确定和校正的方法和系统
公开(公告)号：US08214722B2
公开(公告)日：2012-07-03
申请号：US12304192
申请日：2006-06-20
申请人： Thomas Luedeke
发明人： Thomas Luedeke
IPC分类号： H04L12/40
CPC分类号： H04L7/033
摘要： A signal error determination and correction system is provided which comprises an error correction value calculation means which processes a predetermined segment of a signal to calculate an error correction value, and a signal correction means and prediction which applies the error correction value to at least part of the signal to correct the part of the signal. The invention further provides a method of signal error determination and correction.
摘要翻译：提供一种信号误差确定和校正系统，其包括处理信号的预定段以计算误差校正值的误差校正值计算装置，以及将误差校正值应用于至少部分信号纠正信号的一部分。本发明还提供了一种信号误差确定和校正方法。

3. 发明申请

US20140298005A1 MICROPROCESSOR DEVICE, AND METHOD OF MANAGING RESET EVENTS THEREFOR 有权
标题翻译：微处理器装置及其重置事件的管理方法
公开(公告)号：US20140298005A1
公开(公告)日：2014-10-02
申请号：US14354005
申请日：2011-11-23
申请人： Carl Culshaw , Thomas Luedeke , Nicolas Grossier
发明人： Carl Culshaw , Thomas Luedeke , Nicolas Grossier
IPC分类号： G06F9/445
CPC分类号： G06F9/442 , G06F1/24 , G06F9/44505 , G06F11/0721 , G06F11/076
摘要： A microprocessor device comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event comprising a first reset level, determine if at least one reset condition has been met upon detection of the reset event comprising the first reset level, and cause a reset of a second reset level upon determining that the at least one reset condition has been met.
摘要翻译：微处理器设备包括至少一个复位管理模块。所述至少一个复位管理模块被布置成检测包括第一复位电平的复位事件，确定在检测到包括第一复位电平的复位事件时是否满足了至少一个复位条件，并且引起第二复位的复位确定已经满足至少一个复位条件。

4. 发明申请

US20140006841A1 CLOCK GLITCH DETECTION CIRCUIT 有权
标题翻译：时钟检测电路
公开(公告)号：US20140006841A1
公开(公告)日：2014-01-02
申请号：US14015519
申请日：2013-08-30
申请人： Michael Rohleder , Thomas Koch , Vladimir Litovtchenko , Thomas Luedeke
发明人： Michael Rohleder , Thomas Koch , Vladimir Litovtchenko , Thomas Luedeke
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , H03K5/1252
摘要： In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least a particular number of clock edges. A comparator determines whether the difference between the master count and the slave count is at least a value of the incrementer times the particular number of clock edges.
摘要翻译：在用于检测时钟信号中的时钟毛刺的第一电路中，主计数器由时钟信号计时，并存储主计数。增量器将主计数递增一个增量。从计数器由时钟信号计时，并存储从计数。从计数相对于主计数延迟至少一定数量的时钟沿。比较器确定主计数和从计数之间的差是否至少是递增器的值乘以特定数量的时钟边沿。

5. 发明授权

US09781120B2 System on chip and method therefor 有权
公开(公告)号：US09781120B2
公开(公告)日：2017-10-03
申请号：US14899338
申请日：2013-07-18
申请人： Michael Rohleder , Gary Hay , Thomas Luedeke , Stephan Mueller
发明人： Michael Rohleder , Gary Hay , Thomas Luedeke , Stephan Mueller
IPC分类号： G06F12/14 , G06F21/62 , G06F21/76 , H04L29/06 , G06F21/78 , G06F1/00 , G06F21/30 , G06F21/60 , G06F21/79 , G06F21/70 , G06F13/00
CPC分类号： H04L63/101 , G06F1/00 , G06F21/30 , G06F21/60 , G06F21/70 , G06F21/78 , G06F21/79 , H04L63/08
摘要： A system on chip comprises a responder unit comprising a set of responder elements and an access control unit associated with an authorization list and the responder unit. An entry of the authorization list defines a set of access requirements in relation to an address space identifying at least part of the responder unit. The access control unit is arranged to: receive a request for access to a target responder element among the responder elements of the responder unit, determine the corresponding set of access requirements for the received access request from the authorization list, and evaluate the request for access with respect to the determined set of access requirements and generate a first request evaluation result. A protection unit associated with the responder unit is arranged to: provide a group assignment assigning a group to each of the responder elements of the responder unit, provide a group authorization list, an entry of the group authorization list defining a set of group access requirements for the group assigned, receive the request for access to the target responder element, determine the group assigned to the target responder element from the group assignment and further determine the set of group access requirements from the group authorization list for the group assigned. The system-on-chip also evaluates the request with respect to the determined set of group access requirements and generates a second request evaluation result. Interaction with the target responder element is controlled in response to the first and/or second evaluation result.

6. 发明申请

US20160156632A1 SYSTEM ON CHIP AND METHOD THEREFOR 有权
标题翻译：芯片系统及其方法
公开(公告)号：US20160156632A1
公开(公告)日：2016-06-02
申请号：US14899338
申请日：2013-07-18
申请人： Michael ROHLEDER , Gary HAY , Thomas LUEDEKE , Stephan MUELLER
发明人： MICHAEL ROHLEDER , GARY HAY , THOMAS LUEDEKE , STEPHAN MUELLER
IPC分类号： H04L29/06 , G06F21/70
CPC分类号： H04L63/101 , G06F1/00 , G06F21/30 , G06F21/60 , G06F21/70 , G06F21/78 , G06F21/79 , H04L63/08
摘要： A system on chip comprises a responder unit comprising a set of responder elements and an access control unit 484 associated with an authorization list and the responder unit. An entry of the authorization list defines a set of access requirements in relation to an address space identifying at least part of the responder unit. The access control unit is arranged to: receive a request for access to a target responder element among the responder elements of the responder unit, determine the corresponding set of access requirements for the received access request from the authorization list, and evaluate the request for access with respect to the determined set of access requirements and generate a first request evaluation result. A protection unit associated with the responder unit is arranged to: provide a group assignment assigning a group to each of the responder elements of the responder unit, provide a group authorization list, an entry of the group authorization list defining a set of group access requirements for the group assigned, receive the request for access to the target responder element, determine the group assigned to the target responder element from the group assignment and further determine the set of group access requirements from the group authorization list for the group assigned. The system-on-chip also evaluates the request with respect to the determined set of group access requirements and generates a second request evaluation result. Interaction with the target responder element is controlled in response to the first and/or second evaluation result.
摘要翻译：片上系统包括响应器单元，其包括一组响应器元件和与授权列表相关联的访问控制单元484和响应器单元。授权列表的条目定义了与识别响应器单元的至少一部分的地址空间相关的一组访问要求。访问控制单元被设置为：在应答器单元的应答器元件中接收对目标响应器元素的访问请求，从授权列表确定接收到的访问请求的相应一组访问要求，并评估访问请求相对于确定的访问要求集合并生成第一请求评估结果。与响应器单元相关联的保护单元被布置为：向组响应器单元的每个应答器元件提供组分组，提供组授权列表，组授权列表的条目，该组授权列表定义一组组访问要求对于所分配的组，接收对目标响应者元素的访问请求，从组分配中确定分配给目标响应者元素的组，并且从分配的组的组授权列表中进一步确定组访问要求的集合。片上系统还针对所确定的组访问要求集合来评估请求，并生成第二请求评估结果。响应于第一和/或第二评估结果来控制与目标响应元件的交互。

7. 发明申请

US20110317802A1 CLOCK GLITCH DETECTION CIRCUIT 有权
标题翻译：时钟检测电路
公开(公告)号：US20110317802A1
公开(公告)日：2011-12-29
申请号：US13131349
申请日：2009-01-05
申请人： Michael Rohleder , Thomas Koch , Vladimir Litovtchenko , Thomas Luedeke
发明人： Michael Rohleder , Thomas Koch , Vladimir Litovtchenko , Thomas Luedeke
IPC分类号： H03K21/40 , H03K23/42
CPC分类号： G06F1/04 , H03K5/1252
摘要： In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least clock edges. A comparator determines whether the difference between the master count and the slave count is at least. In a related aspect, a synchronous circuit comprises a clock tree for transmitting a clock signal from a start point to one or more other points, the start point and the other points comprising a first point and second point. A first counter is clocked by the clock signal at the first point and memorizes a first count. A first incrementer advances the first count by one increment. A second counter is clocked by the clock signal at the second point and memorizes a second count. A second incrementer advances the second count by one increment. A comparator determines the difference between the first count and the second count, or determines whether the first count and the second count differ. The synchronous circuit may comprise the first circuit. A second circuit for detecting clock glitches in a clock signal is also provided. The second circuit is intended to be integrated in the synchronous circuit.
摘要翻译：在用于检测时钟信号中的时钟毛刺的第一电路中，主计数器由时钟信号计时，并存储主计数。增量器将主计数递增一个增量。从计数器由时钟信号计时，并存储从计数。从计数相对于主计数延迟至少是时钟沿。比较器确定主计数和从计数之间的差异是否至少为止。在相关方面，同步电路包括用于将时钟信号从起始点发送到一个或多个其他点的时钟树，起始点和包括第一点和第二点的其他点。第一计数器由第一点处的时钟信号计时，并记忆第一个计数。第一增量器将第一计数递增一个增量。第二计数器由第二点处的时钟信号计时，并存储第二计数。第二个递增器将第二个计数递增一个增量。比较器确定第一计数和第二计数之间的差，或者确定第一计数和第二计数是否不同。同步电路可以包括第一电路。还提供了用于检测时钟信号中的时钟毛刺的第二电路。第二个电路旨在集成在同步电路中。

8. 发明授权

US07958281B2 Method and apparatus for transmitting data in a flexray node 有权
标题翻译：用于在柔性节点中传输数据的方法和装置
公开(公告)号：US07958281B2
公开(公告)日：2011-06-07
申请号：US12305329
申请日：2006-06-20
申请人： Thomas Luedeke , Christian Steffen
发明人： Thomas Luedeke , Christian Steffen
IPC分类号： G06F13/14 , G06F13/00
CPC分类号： H04J3/0694
摘要： A method of transmitting data to a recipient comprising the steps of dividing the data into a plurality of groups, providing a synchronizing means for each of the groups, using the synchronizing means to synchronize the data in each group, and transmitting the data to a recipient characterized in that the data is divided in accordance with its synchronization requirements with the recipient.
摘要翻译：一种向接收方发送数据的方法，包括以下步骤：将数据划分成多个组，使用同步装置为每个组提供同步装置，以使每个组中的数据同步，并将数据发送到接收者其特征在于，数据根据其与接收者的同步要求而被划分。

9. 发明授权

US09733952B2 Microprocessor, and method of managing reset events therefor 有权
公开(公告)号：US09733952B2
公开(公告)日：2017-08-15
申请号：US14353999
申请日：2012-02-27
申请人： Thomas Luedeke , Markus Baumeister , Carl Culshaw
发明人： Thomas Luedeke , Markus Baumeister , Carl Culshaw
IPC分类号： G06F1/24 , G06F9/44 , G06F9/445 , G06F11/07
CPC分类号： G06F9/442 , G06F1/24 , G06F9/44505 , G06F11/0721 , G06F11/076
摘要： A microprocessor comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event, determine if at least one reset condition has been met upon detection of the reset event, and cause at least a part of the microprocessor to remain in a reset state upon determining that the at least one reset condition has been met.

10. 发明申请

US20140317395A1 MICROPROCESSOR, AND METHOD OF MANAGING RESET EVENTS THEREFOR 有权
标题翻译：微处理器及其管理重置事件的方法
公开(公告)号：US20140317395A1
公开(公告)日：2014-10-23
申请号：US14353999
申请日：2012-02-27
申请人： Thomas Luedeke , Markus Baumeister , Carl Culshaw
发明人： Thomas Luedeke , Markus Baumeister , Carl Culshaw
IPC分类号： G06F9/44
CPC分类号： G06F9/442 , G06F1/24 , G06F9/44505 , G06F11/0721 , G06F11/076
摘要： A microprocessor comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event, determine if at least one reset condition has been met upon detection of the reset event, and cause at least a part of the microprocessor to remain in a reset state upon determining that the at least one reset condition has been met.
摘要翻译：微处理器包括至少一个复位管理模块。所述至少一个复位管理模块被设置为检测复位事件，确定在检测到复位事件时是否满足了至少一个复位条件，并且在确定所述复位事件之后至少使所述微处理器的一部分保持在复位状态已满足至少一个复位条件。

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