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1. 发明申请

US20110084355A1 Isolation Structure For Semiconductor Device 审中-公开
标题翻译：半导体器件的隔离结构
公开(公告)号：US20110084355A1
公开(公告)日：2011-04-14
申请号：US12576818
申请日：2009-10-09
申请人： Hsien-Hsin Lin , Bor Chiuan Hsieh , Chen-Ping Chen
发明人： Hsien-Hsin Lin , Bor Chiuan Hsieh , Chen-Ping Chen
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76229 , H01L21/0237 , H01L21/02381 , H01L21/02639
摘要： A semiconductor device is provided. The semiconductor device includes a substrate, an isolation feature disposed on the substrate, and an active area disposed adjacent the isolation feature. The isolation feature may be a shallow trench isolation feature. The STI feature has a first width at the top of the feature and a second width at the bottom of the feature. The first width is less than the second width. Methods of fabricating a semiconductor device is also provided. A method includes forming shallow trench isolation features and then growing an epitaxial layer adjacent the STI features to form an active region.
摘要翻译：提供半导体器件。半导体器件包括衬底，设置在衬底上的隔离特征以及邻近隔离特征设置的有源区。隔离特征可以是浅沟槽隔离特征。 STI特征在特征顶部具有第一宽度，并且在特征底部具有第二宽度。第一宽度小于第二宽度。还提供了制造半导体器件的方法。一种方法包括形成浅沟槽隔离特征，然后生长与STI特征相邻的外延层以形成有源区。

2. 发明授权

US08048764B2 Dual etch method of defining active area in semiconductor device 有权
标题翻译：在半导体器件中限定有源区的双重蚀刻方法
公开(公告)号：US08048764B2
公开(公告)日：2011-11-01
申请号：US12570926
申请日：2009-09-30
申请人： Ming-Jie Huang , Chen-Ping Chen , Tung-Ying Lee
发明人： Ming-Jie Huang , Chen-Ping Chen , Tung-Ying Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/76232 , H01L21/3081
摘要： A method of forming a hardmask for defining shallow trench isolation regions in a semiconductor substrate layer includes the steps of: depositing a hardmask layer over the semiconductor substrate layer; depositing and patterning a first photoresist layer over the hardmask layer; etching the hardmask layer after patterning the first photoresist layer to form an interim hardmask layer having at least one line feature; depositing and patterning a second photoresist layer over the interim hardmask layer; and forming a hardmask, the forming step including etching the interim hardmask layer after patterning the second photoresist layer to define a line end of the at least one line feature.
摘要翻译：在半导体衬底层中形成用于限定浅沟槽隔离区的硬掩模的方法包括以下步骤：在半导体衬底层上沉积硬掩模层; 在硬掩模层上沉积和图案化第一光致抗蚀剂层; 在图案化第一光致抗蚀剂层之后蚀刻硬掩模层以形成具有至少一个线特征的临时硬掩模层; 在所述临时硬掩模层上沉积和图案化第二光致抗蚀剂层; 以及形成硬掩模，所述形成步骤包括在图案化所述第二光致抗蚀剂层之后蚀刻所述临时硬掩模层以限定所述至少一个线特征的线端。

3. 发明授权

US08563439B2 Method of pitch dimension shrinkage 有权
标题翻译：螺距尺寸收缩方法
公开(公告)号：US08563439B2
公开(公告)日：2013-10-22
申请号：US12842162
申请日：2010-07-23
申请人： Ming-Jie Huang , Chen-Ping Chen
发明人： Ming-Jie Huang , Chen-Ping Chen
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/0338 , H01L21/3088 , H01L21/31144
摘要： An embodiment of the disclosure includes a method of pitch reduction. A substrate is provided. A first material layer is formed over the substrate. A second material layer is formed on the first material layer. A hardmask layer is formed on the second material layer. A first imaging layer is formed on the hardmask layer. The first imaging layer is patterned to form a plurality of first features over the hardmask layer. The hardmask layer is etched utilizing the first imaging layer as a mask to form the first features in the hardmask layer. The first imaging layer is removed to expose the etched hardmask layer and a portion of a top surface of the second material layer. A second imaging layer is formed and the process is repeated, such that first and second features are alternating with a pitch substantially half the original pitch.
摘要翻译：本公开的一个实施例包括减小音调的方法。提供基板。第一材料层形成在衬底上。在第一材料层上形成第二材料层。硬掩模层形成在第二材料层上。第一成像层形成在硬掩模层上。图案化第一成像层以在硬掩模层上形成多个第一特征。使用第一成像层作为掩模蚀刻硬掩模层以形成硬掩模层中的第一特征。去除第一成像层以暴露蚀刻的硬掩模层和第二材料层的顶表面的一部分。形成第二成像层并且重复该过程，使得第一和第二特征以基本上相当于原始间距的一半的间距交替。

4. 发明授权

US09130058B2 Forming crown active regions for FinFETs 有权
标题翻译：形成FinFET的凸起有源区域
公开(公告)号：US09130058B2
公开(公告)日：2015-09-08
申请号：US12874039
申请日：2010-09-01
申请人： Chen-Ping Chen , Hui-Min Lin , Ming-Jie Huang , Tung Ying Lee
发明人： Chen-Ping Chen , Hui-Min Lin , Ming-Jie Huang , Tung Ying Lee
IPC分类号： H01L21/8234 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A device includes a plurality of intra-device insulation regions having a first height; and a plurality of semiconductor fins horizontally spaced apart from each other by the plurality of intra-device insulation regions. A portion of the plurality of semiconductor fins is disposed above the plurality of intra-device insulation regions. The device further includes a first inter-device insulation region and a second inter-device insulation region with the plurality of semiconductor fins disposed therebetween. The first and the second inter-device insulation regions have a second height greater than the first height.
摘要翻译：一种器件包括具有第一高度的多个器件内绝缘区域; 以及通过多个器件间绝缘区域彼此水平间隔开的多个半导体鳍片。多个半导体鳍片的一部分设置在多个器件内绝缘区域的上方。该装置还包括第一器件间绝缘区域和设置在其间的多个半导体鳍片的第二器件间绝缘区域。第一和第二器件间绝缘区域具有大于第一高度的第二高度。

5. 发明申请

US20120049294A1 Forming Crown Active Regions for FinFETs 有权
标题翻译：形成FinFET的Crown有源区域
公开(公告)号：US20120049294A1
公开(公告)日：2012-03-01
申请号：US12874039
申请日：2010-09-01
申请人： Chen-Ping Chen , Hui-Min Lin , Ming-Jie Huang , Tung Ying Lee
发明人： Chen-Ping Chen , Hui-Min Lin , Ming-Jie Huang , Tung Ying Lee
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A device includes a plurality of intra-device insulation regions having a first height; and a plurality of semiconductor fins horizontally spaced apart from each other by the plurality of intra-device insulation regions. A portion of the plurality of semiconductor fins is disposed above the plurality of intra-device insulation regions. The device further includes a first inter-device insulation region and a second inter-device insulation region with the plurality of semiconductor fins disposed therebetween. The first and the second inter-device insulation regions have a second height greater than the first height.
摘要翻译：一种器件包括具有第一高度的多个器件内绝缘区域; 以及通过多个器件间绝缘区域彼此水平间隔开的多个半导体鳍片。多个半导体鳍片的一部分设置在多个器件内绝缘区域的上方。该装置还包括第一器件间绝缘区域和设置在其间的多个半导体鳍片的第二器件间绝缘区域。第一和第二器件间绝缘区域具有大于第一高度的第二高度。

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