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1. 发明申请

US20030217234A1 System having address-based intranode coherency and data-based internode coherency 有权
标题翻译：具有基于地址的Intranode一致性和基于数据的节间一致性的系统
公开(公告)号：US20030217234A1
公开(公告)日：2003-11-20
申请号：US10270480
申请日：2002-10-11
申请人： Broadcom Corp.
发明人： Joseph B. Rowlands
IPC分类号： G06F012/00
CPC分类号： G06F12/0817 , Y10S707/99952
摘要： A system comprises a plurality of nodes, each node comprising one or more coherent agents coupled to an interconnect. Ownership of a coherency block accessed by a transaction on the interconnect is transferred responsive to transmission of the address on the interconnect. The system further includes a second interconnect to which the plurality of nodes are coupled, wherein ownership of a coherency block is transferred on the second interconnect responsive to a transmission of the data comprising the coherency block on the second interconnect. A first node of the plurality of nodes issues a coherency command on the second interconnect to fetch the coherency block in response to the transaction on the interconnect within the first node, whereby ownership transfers within the first node prior to ownership transferring from another one of the plurality of nodes to the first node.
摘要翻译：系统包括多个节点，每个节点包括耦合到互连的一个或多个相干代理。响应于互连上的地址的传输，传送由互连上的事务访问的一致性块的所有权。该系统还包括多个节点耦合到的第二互连，其中响应于包括第二互连上的一致性块的数据的传输，在第二互连上传送一致性块的所有权。所述多个节点中的第一节点在所述第二互连上发出相关命令以便响应于所述第一节点内的所述互连上的事务来获取所述一致性块，由此所有权转移在所述第一节点之内，从所述转移中的另一个多个节点到第一个节点。

2. 发明申请

US20030217233A1 Remote line directory which covers subset of shareable CC-NUMA memory space 失效
标题翻译：远程线路目录覆盖可共享CC-NUMA内存空间的子集
公开(公告)号：US20030217233A1
公开(公告)日：2003-11-20
申请号：US10269827
申请日：2002-10-11
申请人： Broadcom Corp.
发明人： Joseph B. Rowlands , James B. Keller
IPC分类号： G06F012/00
CPC分类号： G06F12/0817 , Y10S707/99952
摘要： A node is coupled to receive a coherency command and coupled to a memory, wherein the node includes a directory configured to track a state of a first number of coherency blocks less than a total number of the coherency blocks in the memory. The directory is configured to allocate a first entry to track the state of the first coherency block responsive to the coherency command. If the first entry is currently tracking the state of a second coherency block, the second node is configured to generate one or more coherency commands to invalidate the second coherency block in a plurality of nodes.
摘要翻译：耦合节点以接收相关命令并耦合到存储器，其中节点包括被配置为跟踪小于存储器中的一致性块的总数的第一数量的一致性块的状态的目录。该目录被配置为响应于一致性命令来分配第一条目以跟踪第一一致性块的状态。如果第一条目当前正在跟踪第二相关性块的状态，则第二节点被配置为生成一个或多个一致性命令以使多个节点中的第二一致性块无效。

3. 发明申请

US20030191926A1 Method and apparatus for performing addressing operations in a superscalar, superpipelined processor 有权
标题翻译：用于在超标量超级流水线处理器中执行寻址操作的方法和装置
公开(公告)号：US20030191926A1
公开(公告)日：2003-10-09
申请号：US10401170
申请日：2003-03-27
申请人： Broadcom Corp.
发明人： Dan Dobberpuhl , Robert Stepanian
IPC分类号： G06F009/00
CPC分类号： G06F9/3873 , G06F9/30167 , G06F9/3836 , G06F9/3867 , G06F9/3885
摘要： A method and apparatus for improving the performance of a superscalar, superpipelined processor by identifying and processing instructions for performing addressing operations is provided. The invention heuristically determines instructions likely to perform addressing operations and assigns those instructions to specialized pipes in a pipeline structure. The invention can assign such instructions to both an execute pipe and a load/store pipe to avoid the occurrence of nullbubblesnull in the event execution of the instruction requires the calculation capability of the execute pipe. The invention can also examine a sequence of instructions to identify an instruction for performing a calculation where the result of the calculation is used by a succeeding load or store instruction. In this case, the invention controls the pipeline to assure the result of the calculation is available for the succeeding load or store instruction even if both instructions are being processed concurrently.
摘要翻译：提供了一种用于通过识别和处理用于执行寻址操作的指令来改进超标量超管道处理器的性能的方法和装置。本发明启发式地确定可能执行寻址操作的指令，并将这些指令分配给管道结构中的专用管道。本发明可以将这样的指令分配给执行管道和加载/存储管道，以在执行指令需要执行管道的计算能力的情况下避免“气泡”的发生。本发明还可以检查用于识别用于执行计算的指令的指令序列，其中由后续加载或存储指令使用计算结果。在这种情况下，即使两个指令被同时处理，本发明控制流水线以确保计算结果可用于后续的加载或存储指令。

4. 发明申请

US20030097498A1 System having two or more packet interfaces, a switch, and a shared packet DMA circuit 有权
标题翻译：具有两个或多个分组接口的系统，交换机和共享分组DMA电路
公开(公告)号：US20030097498A1
公开(公告)日：2003-05-22
申请号：US10269666
申请日：2002-10-11
申请人： Broadcom Corp.
发明人： Barton J. Sano , Koray Oner , Laurent R. Moll , Manu Gulati
IPC分类号： G06F013/28
CPC分类号： H04L49/10 , H04L49/602
摘要： An apparatus includes a first interface circuit, a second interface circuit, a memory controller for configured to interface to a memory, and a packet DMA circuit. The first interface circuit is configured to couple to a first interface for receiving and transmitting packet data. Similarly, the second interface circuit is configured to couple to a second interface for receiving and transmitting packet data. The packet DMA circuit is coupled to receive a first packet from the first interface circuit and a second packet from the second interface circuit. The packet DMA circuit is configured to transmit the first packet and the second packet in write commands to the memory controller to be written to the memory. In some embodiments, a switch is coupled to the first interface circuit, the second interface circuit, and the packet DMA circuit.
摘要翻译：一种装置包括第一接口电路，第二接口电路，用于配置为与存储器接口的存储器控制器和分组DMA电路。第一接口电路被配置为耦合到用于接收和发送分组数据的第一接口。类似地，第二接口电路被配置为耦合到用于接收和发送分组数据的第二接口。分组DMA电路被耦合以从第一接口电路接收第一分组，并从第二接口电路接收第二分组。分组DMA电路被配置为以写入命令将第一分组和第二分组发送到存储器控制器以写入存储器。在一些实施例中，开关耦合到第一接口电路，第二接口电路和分组DMA电路。

5. 发明申请

US20030097467A1 System having configurable interfaces for flexible system configurations 有权
标题翻译：具有用于灵活系统配置的可配置接口的系统
公开(公告)号：US20030097467A1
公开(公告)日：2003-05-22
申请号：US10270014
申请日：2002-10-11
申请人： Broadcom Corp.
发明人： Barton J. Sano
IPC分类号： G06F015/173
CPC分类号： G06F12/0831
摘要： An apparatus includes a plurality of memories, a plurality of systems, and a switch interface circuit. Each of the plurality of systems includes a memory controller coupled to a respective one of the plurality of memories. Additionally, each of the plurality of systems is coupled to at least one other one of the plurality of systems. Each of the plurality of systems further includes one or more coherent agents configured to access the plurality of memories, and wherein the plurality of systems enforce coherency across the plurality of systems for at least some accesses. At least one of the plurality of systems is coupled to the switch interface circuit separate from the interconnection of the plurality of systems. The switch interface circuit is configured to interface the apparatus to a switch fabric.
摘要翻译：一种装置包括多个存储器，多个系统和开关接口电路。多个系统中的每一个包括耦合到多个存储器中的相应一个的存储器控制器。另外，多个系统中的每一个耦合到多个系统中的至少另一个系统。所述多个系统中的每一个还包括被配置为访问所述多个存储器的一个或多个相干代理，并且其中所述多个系统在所述多个系统中执行用于至少一些访问的一致性。多个系统中的至少一个耦合到与多个系统的互连分离的开关接口电路。开关接口电路被配置为将设备连接到交换结构。

6. 发明申请

US20030117186A1 Conditional clock buffer circuit 有权
公开(公告)号：US20030117186A1
公开(公告)日：2003-06-26
申请号：US10349473
申请日：2003-01-22
申请人： Broadcom Corp.
发明人： Daniel W. Dobberpuhl
IPC分类号： H03B001/00
CPC分类号： H03K19/0016 , G06F1/10
摘要： A conditional clock buffer circuit is disclosed. In one embodiment, a conditional clock buffer circuit includes a precharge circuit, a first transistor and a second transistor coupled to the precharge circuit via the first node and the second node, a third transistor coupled to the first transistor and the second transistor. The first transistor may be activated responsive to a condition external to the clock buffer circuit. When the first transistor is activated, an output clock signal driven by the clock buffer circuit may be inhibited.

7. 发明申请

US20030067335A1 Method and apparatus to ensure DLL locking at minimum delay 有权
公开(公告)号：US20030067335A1
公开(公告)日：2003-04-10
申请号：US10294372
申请日：2002-11-14
申请人： Broadcom Corp.
发明人： Vincent R. von Kaenel
IPC分类号： H03L007/06
CPC分类号： H03L7/095 , H03L7/0814
摘要： A method and apparatus to ensure DLL locking at a minimum delay is provided. In one embodiment, a DLL circuit includes a phase detector, a counter, a programmable delay line, and a counter control circuit. Upon initialization of the DLL circuit, the counter control circuit is configured to cause the counter to count increment, regardless of the phase relationship between a reference clock signal and the output clock signal. The counter continues incrementing, thereby changing the phase relationship between the reference clock signal and the output clock signal by adjusting the delay of the programmable delay line. This eventually results in a phase lock between the reference clock signal and the output clock signal at a minimum delay. Once the DLL achieves a phase lock between the reference clock signal and the output clock signal, the counter increments or decrements its count in order to maintain or re-acquire a lock.

8. 发明授权

US6411557B2 Memory architecture with single-port cell and dual-port (read and write) functionality 有权
标题翻译：具有单端口单元和双端口（读写）功能的内存架构
公开(公告)号：US6411557B2
公开(公告)日：2002-06-25
申请号：US77570101
申请日：2001-02-02
申请人： BROADCOM CORP
发明人： TERZIOGLU ESIN , AFGHAHI MORTEZA CYRUS
IPC分类号： G11C7/06 , G11C8/02 , G11C7/00
CPC分类号： G11C7/06
摘要： A single-port hierarchical memory structure including memory modules having memory cells; hierarchically-coupled local and global sense amplifiers; hierarchically-coupled local and global row decoders; and a predecoding circuit coupled with selected global row decoders. The predecoding circuit is disposed to provide predecoding at a speed substantially faster than the predetermined memory access speed of the memory structure, allowing access to a memory cell at least twice during the memory access period, thereby providing dual-port functionality. A WRITE-AFTER-READ operation without a separate, interposed PRECHARGE cycle, is completed within one memory access cycle of the hierarchical memory structure. The method includes locally selecting the first memory location of a first datum; locally sensing the first datum (i.e., the READ operation); globally selecting the second memory location; concurrently with the globally selecting, globally sensing the first datum at the first memory location; outputting the first data subsequent to the globally sensing; inputting the second datum substantially immediately subsequent to the outputting the first datum; locally selecting the second memory location; and storing the second datum (i.e., WRITE operation). Also, a WRITE-AFTER-WRITE operation similarly is accomplished by interposing a PRECHARGE operation between subsequent WRITE operations. A redundant group of memory cells, and techniques for assigning them to a memory location in a "FAULT" condition, also are provided.
摘要翻译：包括具有存储单元的存储器模块的单端口分层存储器结构; 分层耦合本地和全局读出放大器; 分层耦合本地和全局行解码器; 以及与所选择的全球行解码器耦合的预解码电路。预解码电路被设置为以比存储器结构的预定存储器访问速度快得多的速度提供预解码，允许在存储器访问周期期间至少访问存储器单元两次，从而提供双端口功能。在分层存储器结构的一个存储器访问周期内完成没有单独的插入的PRECHARGE周期的写入 - 后读取操作。该方法包括：本地选择第一数据的第一存储器位置; 本地感测第一基准（即READ操作）; 全局选择第二个内存位置; 与全球选择同时全球感测第一个存储单元的第一个数据; 在全局感测之后输出第一数据; 在输出第一数据之后基本上立即输入第二基准; 在本地选择第二存储器位置; 并存储第二基准（即WRITE操作）。此外，WRITE-AFTER-WRITE操作类似地通过在后续写操作之间插入PRECHARGE操作来实现。还提供冗余的存储器单元组以及用于将它们分配给“故障”状态的存储单元的技术。

9. 发明授权

US6400198B1 High speed flip-flop 有权
公开(公告)号：US6400198B1
公开(公告)日：2002-06-04
申请号：US73244400
申请日：2000-12-07
申请人： BROADCOM CORP
发明人： AFGHAHI MORTEZA CYRUS
IPC分类号： H03K3/356 , H03K3/3562 , H03K3/037
CPC分类号： H03K3/35625 , H03K3/356113 , H03K3/356156
摘要： A bistable device has first and second complementary input terminals and first and second bistable states that are determined by the polarity of the signal applied to one of the input terminals. A source of an uninverted binary input signal, preferably an uninverted data stream, has a first value or a second value. A source of an inverted binary input signal, preferably an inverted data stream, has a first value or a second value in complementary relationship to the values of the uninverted input signal. A first source of a trigger signal has one polarity. A second source of a trigger signal has the other polarity. The first trigger signal is applied to the first input terminal and the second trigger signal is applied to the second input terminal to drive the bistable device into the first stable state when the input signal has the first value. The first trigger signal is applied to the second input terminal and the second trigger signal is applied to the first input terminal to drive the bistable device into the second stable state when the input signal has the second value.

10. 发明申请

US20030095559A1 Systems including packet interfaces, switches, and packet DMA circuits for splitting and merging packet streams 有权
标题翻译：包括用于分组和合并分组流的分组接口，交换机和分组DMA电路的系统
公开(公告)号：US20030095559A1
公开(公告)日：2003-05-22
申请号：US10270016
申请日：2002-10-11
申请人： Broadcom Corp.
发明人： Barton J. Sano , Laurent R. Moll , Manu Gulati
IPC分类号： H04L012/28
CPC分类号： H04L47/40
摘要： An integrated circuit includes receive circuits for receiving packets, transmit circuits for transmitting packets, a packet DMA circuit for communicating packets to and from a memory controller, and a switch for selectively coupling the receive circuits to transmit circuits. The integrated circuit may flexibly merge and split the packet streams to provide for various packet processing/packet routing functions to be applied to different packets within the packet streams. An apparatus may include two or more of the integrated circuits, which may communicate packets between respective receive and transmit circuits.
摘要翻译：集成电路包括用于接收分组的接收电路，用于发送分组的发送电路，用于向存储器控制器传送分组的分组DMA电路和用于选择性地将接收电路耦合到发送电路的开关。集成电路可以灵活地合并和拆分分组流，以提供要应用于分组流内的不同分组的各种分组处理/分组路由功能。装置可以包括两个或更多个集成电路，其可以在相应的接收和发送电路之间传送分组。

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