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1. 发明授权

US6411557B2 Memory architecture with single-port cell and dual-port (read and write) functionality 有权
标题翻译：具有单端口单元和双端口（读写）功能的内存架构
公开(公告)号：US6411557B2
公开(公告)日：2002-06-25
申请号：US77570101
申请日：2001-02-02
申请人： BROADCOM CORP
发明人： TERZIOGLU ESIN , AFGHAHI MORTEZA CYRUS
IPC分类号： G11C7/06 , G11C8/02 , G11C7/00
CPC分类号： G11C7/06
摘要： A single-port hierarchical memory structure including memory modules having memory cells; hierarchically-coupled local and global sense amplifiers; hierarchically-coupled local and global row decoders; and a predecoding circuit coupled with selected global row decoders. The predecoding circuit is disposed to provide predecoding at a speed substantially faster than the predetermined memory access speed of the memory structure, allowing access to a memory cell at least twice during the memory access period, thereby providing dual-port functionality. A WRITE-AFTER-READ operation without a separate, interposed PRECHARGE cycle, is completed within one memory access cycle of the hierarchical memory structure. The method includes locally selecting the first memory location of a first datum; locally sensing the first datum (i.e., the READ operation); globally selecting the second memory location; concurrently with the globally selecting, globally sensing the first datum at the first memory location; outputting the first data subsequent to the globally sensing; inputting the second datum substantially immediately subsequent to the outputting the first datum; locally selecting the second memory location; and storing the second datum (i.e., WRITE operation). Also, a WRITE-AFTER-WRITE operation similarly is accomplished by interposing a PRECHARGE operation between subsequent WRITE operations. A redundant group of memory cells, and techniques for assigning them to a memory location in a "FAULT" condition, also are provided.
摘要翻译：包括具有存储单元的存储器模块的单端口分层存储器结构; 分层耦合本地和全局读出放大器; 分层耦合本地和全局行解码器; 以及与所选择的全球行解码器耦合的预解码电路。预解码电路被设置为以比存储器结构的预定存储器访问速度快得多的速度提供预解码，允许在存储器访问周期期间至少访问存储器单元两次，从而提供双端口功能。在分层存储器结构的一个存储器访问周期内完成没有单独的插入的PRECHARGE周期的写入 - 后读取操作。该方法包括：本地选择第一数据的第一存储器位置; 本地感测第一基准（即READ操作）; 全局选择第二个内存位置; 与全球选择同时全球感测第一个存储单元的第一个数据; 在全局感测之后输出第一数据; 在输出第一数据之后基本上立即输入第二基准; 在本地选择第二存储器位置; 并存储第二基准（即WRITE操作）。此外，WRITE-AFTER-WRITE操作类似地通过在后续写操作之间插入PRECHARGE操作来实现。还提供冗余的存储器单元组以及用于将它们分配给“故障”状态的存储单元的技术。

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