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1. 发明授权

US09121768B2 Thermal sensor device 有权
标题翻译：热传感器装置
公开(公告)号：US09121768B2
公开(公告)日：2015-09-01
申请号：US13328546
申请日：2011-12-16
申请人： Arijit Raychowdhury , Hasnain Lakdawala , Yee (William) Li , Greg Taylor , Soumyanath Krishnamurthy
发明人： Arijit Raychowdhury , Hasnain Lakdawala , Yee (William) Li , Greg Taylor , Soumyanath Krishnamurthy
IPC分类号： G01K7/00 , G01K7/01
CPC分类号： G01K7/015 , G01K2219/00
摘要： A thermal sensor is provided that includes a front-end component, an analog-to-digital converter and a digital backend. The front-end component including an array of current sources, a dynamic element matching (DEM) device, an analog chopper and two diodes to sense temperatures on the die. The front-end component to provide analog signals at two output nodes based on currents through the two diodes. The analog-to-digital converter to receive the analog signals from the front-end component and to provide an output signal. The digital backend to receive the output signal from the analog-to-digital converter and to provide a calculated temperature.
摘要翻译：提供了一种热传感器，其包括前端部件，模数转换器和数字后端。前端部件包括电流源阵列，动态元件匹配（DEM）器件，模拟斩波器和两个二极管，用于感测管芯上的温度。前端组件根据两个二极管的电流在两个输出节点提供模拟信号。模数转换器从前端组件接收模拟信号并提供输出信号。数字后端从模数转换器接收输出信号并提供计算温度。

2. 发明申请

US20150206564A1 METHODS AND SYSTEMS TO READ A MAGNETIC TUNNEL JUNCTION (MTJ) BASED MEMORY CELL BASED ON A PULSED READ CURRENT 有权
标题翻译：基于脉冲读取电流读取基于磁悬浮连接（MTJ）的存储单元的方法和系统
公开(公告)号：US20150206564A1
公开(公告)日：2015-07-23
申请号：US14350997
申请日：2012-03-25
申请人： Arijit Raychowdhury , David Kencke , Brian Doyle , Charles Kuo , James Tschanz , Fatih Hamzaoglu , Yih Wang , Roksana Golizadeh Mojarad
发明人： Arijit Raychowdhury , David Kencke , Brian Doyle , Charles Kuo , James Tschanz , Fatih Hamzaoglu , Yih Wang , Roksana Golizadeh Mojarad
IPC分类号： G11C11/16 , G11C5/12
CPC分类号： G11C11/165 , G11C5/12 , G11C11/1673 , G11C11/1693 , G11C2013/0052 , G11C2013/0071
摘要： Methods and systems to read a logic value stored in a magnetic tunnel junction (MTJ)-based memory cell based on a pulsed read current, with time between pulses to permit the MTJ to relax towards the magnetization orientation between the pulses, which may reduce build-up of momentum within the MTJ, and which may reduce and/or eliminate inadvertent re-alignment of a magnetization orientation. A sequence of symmetric and/or non-symmetric pulses may be applied to a wordline (WL) to cause a pre-charged bit line (BL) capacitance to discharge a pulsed read current through the MTJ, resulting in a corresponding sequence of voltage changes on the BL. The BL voltage changes may be integrated over the sequence of read current pulses, and a stored logic value may be determined based on the integrated voltage changes. The pre-charged BL capacitance may also serve as the voltage integrator.
摘要翻译：基于脉冲读取电流读取存储在基于磁隧道结（MTJ）的存储单元中的逻辑值的方法和系统，脉冲之间的时间允许MTJ朝向脉冲之间的磁化取向松弛，这可以减少构建 - MTJ内的动量，并且其可以减少和/或消除磁化取向的无意重新对准。对称和/或非对称脉冲的序列可以被施加到字线（WL），以使预充电位线（BL）电容放电通过MTJ的脉冲读取电流，从而产生相应的电压变化序列在BL上。可以在读取电流脉冲的序列上积分BL电压变化，并且可以基于积分的电压变化来确定存储的逻辑值。预充电的BL电容也可以用作电压积分器。

3. 发明授权

US08901819B2 Multi-supply sequential logic unit 有权
标题翻译：多电源顺序逻辑单元
公开(公告)号：US08901819B2
公开(公告)日：2014-12-02
申请号：US13992894
申请日：2011-12-14
申请人： Arijit Raychowdhury , Jaydeep P. Kulkarni , James W. Tschanz
发明人： Arijit Raychowdhury , Jaydeep P. Kulkarni , James W. Tschanz
IPC分类号： H03K19/0175
CPC分类号： H03K19/017509 , G06F1/10 , G06F1/3296 , Y02D10/172
摘要： Described herein are apparatus, method, and system for reducing clock-to-output delay of a sequential logic unit in a processor. The apparatus comprises a sequential unit including: a data path, to receive an input signal, including logic gates to operate on a first power supply level, the data path to generate an output signal; and a clock path including logic gates to operate on a second power supply level, the logic gates of the clock path to sample the input signal using a sampling signal to generate the output signal, wherein the second power supply level is higher than the first power supply level. The apparatus improves (i.e. reduces) setup time of the sequential unit and allows the processor to operate at minimum operating voltage (Vmin) without degrading performance of the sequential unit.
摘要翻译：这里描述了用于减少处理器中的顺序逻辑单元的时钟到输出延迟的装置，方法和系统。所述装置包括顺序单元，包括：数据路径，用于接收输入信号，包括在第一电源电平上操作的逻辑门，所述数据路径以产生输出信号; 以及时钟路径，包括用于在第二电源电平上操作的逻辑门，所述时钟路径的逻辑门使用采样信号对所述输入信号进行采样以产生所述输出信号，其中所述第二电源电平高于所述第一电力供应水平。该装置改善（即减少）顺序单元的建立时间，并允许处理器以最小工作电压（Vmin）运行，而不降低顺序单元的性能。

4. 发明申请

US20140035617A1 SPIN TRANSFER TORQUE BASED MEMORY ELEMENTS FOR PROGRAMMABLE DEVICE ARRAYS 有权
标题翻译：用于可编程器件阵列的基于转子扭矩的记忆元件
公开(公告)号：US20140035617A1
公开(公告)日：2014-02-06
申请号：US13997962
申请日：2012-03-30
申请人： Arijit Raychowdhury , James W. Tschanz , Vivek De
发明人： Arijit Raychowdhury , James W. Tschanz , Vivek De
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , G11C11/16 , H03K19/177
摘要： Disclosed herein are semiconductor device arrays, such as, Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Arrays (CPLAs) that use high-density Spin Transfer Torque (STT)-based memory elements. STT-based memory elements can either be stand-alone FPGAs/CPLAs, or can be embedded in microprocessors and/or digital signal processing (DSP) system-on-chip (SoC) to provide design flexibility for implementing low power, scalable, secure and reconfigurable hardware architecture. Because the configuration is stored on the FPGA/CPLA die itself, the need for loading the configuration from external storage every time is eliminated when the device is powered on. In addition to instant startup, eliminating configuration I/O traffic results in power savings and possible pin count reduction. Security is greatly improved by eliminating the need to store configuration data in an external memory.
摘要翻译：这里公开了使用基于高密度旋转转矩（STT）的存储器元件的半导体器件阵列，诸如现场可编程门阵列（FPGA）和复数可编程逻辑阵列（CPLAs）。基于STT的存储器元件可以是独立的FPGA / CPLAs，或者可以嵌入在微处理器和/或数字信号处理（DSP）片上系统（SoC）中，以提供设计灵活性，以实现低功率，可扩展，安全和可重构硬件架构。由于配置存储在FPGA / CPLA裸片本身，所以每次在外部存储器上加载配置的需求都将在设备通电时被消除。除了即时启动，消除配置I / O流量导致节电和可能的引脚数减少。通过消除将配置数据存储在外部存储器中的需要，安全性大大提高。

5. 发明申请

US20110317508A1 MEMORY WRITE OPERATION METHODS AND CIRCUITS 有权
标题翻译：存储器写操作方法和电路
公开(公告)号：US20110317508A1
公开(公告)日：2011-12-29
申请号：US12823642
申请日：2010-06-25
申请人： JAYDEEP P. KULKARNI , Muhammad M. Khellah , Bibiche M. Geuskens , Arijit Raychowdhury , Tanay Karnik , Vivek K. De
发明人： JAYDEEP P. KULKARNI , Muhammad M. Khellah , Bibiche M. Geuskens , Arijit Raychowdhury , Tanay Karnik , Vivek K. De
IPC分类号： G11C8/08
CPC分类号： G11C8/08 , G11C7/12 , G11C7/20 , G11C11/412 , G11C11/413
摘要： In some embodiments, write wordline boost may be obtained from wordline driver boost and/or from bit line access transistor boost.
摘要翻译：在一些实施例中，可以从字线驱动器升压和/或来自位线存取晶体管升压获得写入字线升压。

6. 发明申请

US20140236582A1 LOW POWER VOICE DETECTION 有权
标题翻译：低功率语音检测
公开(公告)号：US20140236582A1
公开(公告)日：2014-08-21
申请号：US13997070
申请日：2011-12-06
申请人： Arijit Raychowdhury , Willem M. Beltman , James W. Tschanz , Carlos Tokunaga , Michael E. Deisher , Thomas E. Walsh
发明人： Arijit Raychowdhury , Willem M. Beltman , James W. Tschanz , Carlos Tokunaga , Michael E. Deisher , Thomas E. Walsh
IPC分类号： G10L15/20 , G10L21/0232 , G10L15/22 , G10L21/0208
CPC分类号： G10L15/20 , G06F1/3234 , G06F17/142 , G10L15/22 , G10L15/285 , G10L21/0208 , G10L21/0232 , G10L25/18 , G10L25/84 , G10L2015/223 , G10L2021/02087
摘要： Methods of enabling voice processing with minimal power consumption includes recording time-domain audio signal at a first clock frequency and a first voltage, and performing Fast Fourier Transform (FFT) operations on the time-domain audio signal at a second clock frequency to generate frequency-domain audio signal. The frequency domain audio signal may be enhanced to obtain better signal to noise ratio, through one or multiple filtering and enhancing techniques. The enhanced audio signal may be used to generate the total signal energy and estimate the background noise energy. Decision logic may determine from the signal energy and the background noise, the presence or absence of the human voice. The first clock frequency may be different from the second clock frequency.
摘要翻译：以最小功耗实现语音处理的方法包括以第一时钟频率和第一电压记录时域音频信号，并且以第二时钟频率对时域音频信号执行快速傅立叶变换（FFT）操作以产生频率域音频信号。可以通过一个或多个滤波和增强技术来增强频域音频信号以获得更好的信噪比。增强音频信号可用于产生总信号能量并估计背景噪声能量。决策逻辑可以根据信号能量和背景噪声来确定人类语音的存在或不存在。第一时钟频率可以不同于第二时钟频率。

7. 发明授权

US08389976B2 Methods of forming carbon nanotube transistors for high speed circuit operation and structures formed thereby 失效
标题翻译：形成用于高速电路操作的碳纳米管晶体管的方法和由此形成的结构
公开(公告)号：US08389976B2
公开(公告)日：2013-03-05
申请号：US11648209
申请日：2006-12-29
申请人： Arijit Raychowdhury , Ali Keshavarzi , Juanita Kurtin , Vivek De
发明人： Arijit Raychowdhury , Ali Keshavarzi , Juanita Kurtin , Vivek De
IPC分类号： H01L29/06
CPC分类号： H01L29/0665 , B82Y10/00 , H01L27/283 , H01L29/0673 , H01L51/0048 , H01L51/0541 , H01L51/055 , H01L51/0558
摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming a channel region on a substrate, wherein the channel region comprises at least one CNT, forming at least one source/drain region adjacent the channel region, and then forming a gate electrode on the channel region, wherein a width of the gate electrode comprises about 50 percent to about 90 percent of a width of the contact region.
摘要翻译：描述形成微电子器件的方法和相关结构。这些方法可以包括在衬底上形成沟道区，其中沟道区包括至少一个CNT，形成与沟道区相邻的至少一个源/漏区，然后在沟道区上形成栅电极，其中宽度栅电极占接触区域宽度的约50％至约90％。

8. 发明申请

US20120087390A1 THERMAL SENSOR DEVICE 审中-公开
标题翻译：热传感器装置
公开(公告)号：US20120087390A1
公开(公告)日：2012-04-12
申请号：US13328546
申请日：2011-12-16
申请人： Arijit RAYCHOWDHURY , Hasnain Lakdawala , Yee (William) Li , Greg Taylor , Soumyanath Krishnamurthy
发明人： Arijit RAYCHOWDHURY , Hasnain Lakdawala , Yee (William) Li , Greg Taylor , Soumyanath Krishnamurthy
IPC分类号： G01K7/01
CPC分类号： G01K7/015 , G01K2219/00
摘要： A thermal sensor is provided that includes a front-end component, an analog-to-digital converter and a digital backend. The front-end component including an array of current sources, a dynamic element matching (DEM) device, an analog chopper and two diodes to sense temperatures on the die. The front-end component to provide analog signals at two output nodes based on currents through the two diodes. The analog-to-digital converter to receive the analog signals from the front-end component and to provide an output signal. The digital backend to receive the output signal from the analog-to-digital converter and to provide a calculated temperature.
摘要翻译：提供了一种热传感器，其包括前端部件，模数转换器和数字后端。前端部件包括电流源阵列，动态元件匹配（DEM）器件，模拟斩波器和两个二极管，用于感测管芯上的温度。前端组件根据两个二极管的电流在两个输出节点提供模拟信号。模数转换器从前端组件接收模拟信号并提供输出信号。数字后端从模数转换器接收输出信号并提供计算温度。

9. 发明申请

US20120004909A1 SPEECH AUDIO PROCESSING 有权
标题翻译：语音处理
公开(公告)号：US20120004909A1
公开(公告)日：2012-01-05
申请号：US12828195
申请日：2010-06-30
申请人： Willem M. Beltman , Matias Zanartu , Arijit Raychowdhury , Anand P. Rangarajan , Michael E. Deisher
发明人： Willem M. Beltman , Matias Zanartu , Arijit Raychowdhury , Anand P. Rangarajan , Michael E. Deisher
IPC分类号： G10L15/20
CPC分类号： G10L15/20 , G10L21/0224 , G10L21/0232 , G10L21/0264 , G10L25/03 , G10L25/93
摘要： A speech processing engine is provided that in some embodiments, employs Kalman filtering with a particular speaker's glottal information to clean up an audio speech signal for more efficient automatic speech recognition.
摘要翻译：提供语音处理引擎，在一些实施例中，使用具有特定扬声器的声门信息的卡尔曼滤波来清理音频语音信号以便更有效的自动语音识别。

10. 发明授权

US07298838B2 Adaptive cancellation network system and method for digital subscriber line 有权
标题翻译：数字用户线自适应消除网络系统及方法
公开(公告)号：US07298838B2
公开(公告)日：2007-11-20
申请号：US10234510
申请日：2002-09-03
申请人： Sandeep K. Oswal , Prakash Easwaran , Arijit Raychowdhury , Fernando A. Mujica
发明人： Sandeep K. Oswal , Prakash Easwaran , Arijit Raychowdhury , Fernando A. Mujica
IPC分类号： H04M1/00
CPC分类号： H04B3/23
摘要： A method for reducing transmit echo in a DSL modem comprises selecting at least one cancellation device of a plurality of cancellation devices. An attenuation signal is generated using the selected cancellation device. At least a portion of transmit echo is removed from a receive signal using the attenuation signal.
摘要翻译：一种用于减少DSL调制解调器中的发射回波的方法包括：选择多个取消装置的至少一个消除装置。使用所选择的取消装置产生衰减信号。使用衰减信号从接收信号中去除发射回波的至少一部分。

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