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1. 发明授权

US09121768B2 Thermal sensor device 有权
标题翻译：热传感器装置
公开(公告)号：US09121768B2
公开(公告)日：2015-09-01
申请号：US13328546
申请日：2011-12-16
申请人： Arijit Raychowdhury , Hasnain Lakdawala , Yee (William) Li , Greg Taylor , Soumyanath Krishnamurthy
发明人： Arijit Raychowdhury , Hasnain Lakdawala , Yee (William) Li , Greg Taylor , Soumyanath Krishnamurthy
IPC分类号： G01K7/00 , G01K7/01
CPC分类号： G01K7/015 , G01K2219/00
摘要： A thermal sensor is provided that includes a front-end component, an analog-to-digital converter and a digital backend. The front-end component including an array of current sources, a dynamic element matching (DEM) device, an analog chopper and two diodes to sense temperatures on the die. The front-end component to provide analog signals at two output nodes based on currents through the two diodes. The analog-to-digital converter to receive the analog signals from the front-end component and to provide an output signal. The digital backend to receive the output signal from the analog-to-digital converter and to provide a calculated temperature.
摘要翻译：提供了一种热传感器，其包括前端部件，模数转换器和数字后端。前端部件包括电流源阵列，动态元件匹配（DEM）器件，模拟斩波器和两个二极管，用于感测管芯上的温度。前端组件根据两个二极管的电流在两个输出节点提供模拟信号。模数转换器从前端组件接收模拟信号并提供输出信号。数字后端从模数转换器接收输出信号并提供计算温度。

2. 发明授权

US06366122B1 Tristate driver for integrated circuit in interconnects 失效
标题翻译：用于互连中集成电路的三态驱动器
公开(公告)号：US06366122B1
公开(公告)日：2002-04-02
申请号：US09696856
申请日：2000-10-26
申请人： Ram K. Krishnamurthy , Soumyanath Krishnamurthy
发明人： Ram K. Krishnamurthy , Soumyanath Krishnamurthy
IPC分类号： H03K1900
CPC分类号： H03K19/018507 , H03K5/151 , H03K19/09429
摘要： A signal driver circuit uses a single power supply to provide differential low voltage swing signals for use in an integrated circuit. The driver reduces interconnect voltage swing and power consumption, while improving the speed performance of the interconnect. The driver includes series coupled drive transistors to provide differential signals on integrated circuit interconnects. The driver circuit can include circuitry to place the interconnects in a tri-state condition to allow for shared interconnects. An integrated circuit, such as a processor, includes first and second differential interconnects, a receiver circuit connected to the first and second differential interconnects for detecting a differential voltage provided thereon, and a driver circuit connected to the first and second differential interconnects for providing the differential voltage.
摘要翻译：信号驱动器电路使用单个电源来提供用于集成电路的差分低电压摆幅信号。驱动器降低互连电压摆幅和功耗，同时提高互连的速度性能。驱动器包括串联耦合的驱动晶体管，以在集成电路互连上提供差分信号。驱动器电路可以包括将互连置于三态条件以允许共享互连的电路。诸如处理器的集成电路包括第一和第二差分互连，连接到第一和第二差分互连用于检测其上提供的差分电压的接收器电路，以及连接到第一和第二差分互连的驱动器电路，用于提供差分电压。

3. 发明授权

US06353342B1 Integrated circuit bus architecture including a full-swing, clocked, common-gate receiver for fast on-chip signal transmission 有权
标题翻译：集成电路总线架构，包括全频，时钟，共门接收器，用于快速片上信号传输
公开(公告)号：US06353342B1
公开(公告)日：2002-03-05
申请号：US09702121
申请日：2000-10-30
申请人： Atila Alvandpour , Soumyanath Krishnamurthy , Ram K. Krishnamurthy
发明人： Atila Alvandpour , Soumyanath Krishnamurthy , Ram K. Krishnamurthy
IPC分类号： G11C706
CPC分类号： H04L25/0292 , H04L25/0278 , H04L25/028
摘要： An integrated circuit (IC) bus architecture is disclosed. The bus architecture includes a receiver for fast on-chip signal transmission. The receiver includes a first gate device having one terminal connected to a voltage source and a gate terminal connectable to receive a sense signal. A second gate device includes one terminal connected to another terminal of the first gate device, a gate terminal connectable to receive the sense signal and another terminal serving as an input terminal of the receiver and connectable to an interconnect bus to receive input signals from other components on the IC chip. The receiver also includes a third gate device having one terminal connected to a voltage source and another terminal serving as an output terminal of the receiver and connected to the other terminal of the first gate device. The receiver further includes an inverter having an input terminal connected to the output of the receiver and having an output terminal connected to a gate terminal of the third gate device. The input of the receiver is capable of being pre-discharged to a low signal and the output of the receiver is capable of being pre-charged to a high signal for substantially instantaneous transmission of input signals received by the receiver.
摘要翻译：公开了一种集成电路（IC）总线架构。总线架构包括用于快速片上信号传输的接收器。接收机包括具有连接到电压源的一个端子和可连接以接收感测信号的栅极端子的第一栅极器件。第二栅极器件包括连接到第一栅极器件的另一个端子的一个端子，可连接的感测信号的栅极端子和用作接收器的输入端子的另一个端子，并且可连接到互连总线以从其它部件接收输入信号在IC芯片上。接收机还包括具有连接到电压源的一个端子和用作接收器的输出端的另一个端子并连接到第一门装置的另一端的第三门装置。接收机还包括一个反相器，其具有连接到接收器的输出的输入端，并且具有连接到第三门装置的栅极端的输出端。接收机的输入能够被预放电到低信号，并且接收机的输出能够被预充电到高信号，以便接收器接收的输入信号的基本瞬时传输。

4. 发明申请

US20090002086A1 Film bulk acoustic resonator calibration 失效
公开(公告)号：US20090002086A1
公开(公告)日：2009-01-01
申请号：US11823856
申请日：2007-06-28
申请人： Hasnain Lakdawala , Ofir Degani , Ashoke Ravi , Masoud Sajadieh , Soumyanath Krishnamurthy
发明人： Hasnain Lakdawala , Ofir Degani , Ashoke Ravi , Masoud Sajadieh , Soumyanath Krishnamurthy
IPC分类号： H03L1/00
CPC分类号： H03L1/026 , H03L7/1974
摘要： Film bulk acoustic resonators (FBARS) have resonant frequencies that vary with manufacturing variations, but tend to be matched when in proximity on an integrated circuit die. FBAR resonant frequency is determined using a fractional-N synthesizer and comparing phase/frequency of an output signal from the fractional-N synthesizer to a reference. The reference may be derived from a low frequency crystal oscillator, an external signal source, or a communications signal.

5. 发明申请

US20100079324A1 SIGMA-DELTA CONVERTER NOISE CANCELLATION 有权
标题翻译： SIGMA-DELTA转换器噪声消除
公开(公告)号：US20100079324A1
公开(公告)日：2010-04-01
申请号：US12239294
申请日：2008-09-26
申请人： Hasnain Lakdawala , Soumyanath Krishnamurthy
发明人： Hasnain Lakdawala , Soumyanath Krishnamurthy
IPC分类号： H03M3/00
CPC分类号： H03M3/344 , H03M3/46
摘要： Embodiments provide apparatuses, systems, and methods to convert an analog signal input into a sigma-delta digital output at a high sampling rate and correct for noise components of the digital output. An analog filter coupled to a sigma-delta converter accepts a noise-shaped analog signal from the sigma-delta converter to attenuate signal components of the noise-shaped analog signal at a plurality of folding frequencies associated with a sampling rate of a low-speed Analog-To-Digital (ADC) to produce a filtered output. The low-speed ADC is coupled to an output of the analog filter and samples the filtered output of the analog filter at a sampling rate slower than the high sample rate to output an ADC digital output. Other embodiments may be described and claimed.
摘要翻译：实施例提供了以高采样率将模拟信号输入转换成Σ-Δ数字输出并校正数字输出的噪声分量的装置，系统和方法。耦合到Σ-Δ转换器的模拟滤波器接收来自Σ-Δ转换器的噪声形模拟信号，以与低速采样率相关联的多个折叠频率衰减噪声形模拟信号的信号分量模数转换（ADC）产生滤波输出。低速ADC耦合到模拟滤波器的输出，并以低于采样率的采样速率对模拟滤波器的滤波后的输出采样，以输出ADC数字输出。可以描述和要求保护其他实施例。

6. 发明授权

US07609792B2 Multiple-input multiple-output multichip transceiver with correlated clock signals 失效
标题翻译：具有相关时钟信号的多输入多输出多芯片收发器
公开(公告)号：US07609792B2
公开(公告)日：2009-10-27
申请号：US11069172
申请日：2005-03-01
申请人： Georgios Palaskas , Ashoke Ravi , Soumyanath Krishnamurthy , Richard B. Nicholls , Keith A. Holt , Stanley K. Ling
发明人： Georgios Palaskas , Ashoke Ravi , Soumyanath Krishnamurthy , Richard B. Nicholls , Keith A. Holt , Stanley K. Ling
IPC分类号： H04B7/10
CPC分类号： H04L1/06
摘要： A multichip transceiver operates as part of a multiple-input multiple-output communication system. First receiver circuitry on a first integrated circuit processes radio-frequency (RF) signals received from a first signal source, and second receiver circuitry on a second integrated circuit processes RF signals received from a second signal source. Clock-signal generating circuitry provides clock signals through phase-matched paths to the first and second receiver circuitry.
摘要翻译：多芯片收发器作为多输入多输出通信系统的一部分而工作。第一集成电路上的第一接收器电路处理从第一信号源接收的射频（RF）信号，第二集成电路上的第二接收器电路处理从第二信号源接收的RF信号。时钟信号产生电路通过相位匹配的路径提供时钟信号到第一和第二接收器电路。

7. 发明授权

US07576621B2 Film bulk acoustic resonator calibration 失效
标题翻译：薄膜体声共振器校准
公开(公告)号：US07576621B2
公开(公告)日：2009-08-18
申请号：US11823856
申请日：2007-06-28
申请人： Hasnain Lakdawala , Ofir Degani , Ashoke Ravi , Masoud Sajadieh , Soumyanath Krishnamurthy
发明人： Hasnain Lakdawala , Ofir Degani , Ashoke Ravi , Masoud Sajadieh , Soumyanath Krishnamurthy
IPC分类号： H03L1/00
CPC分类号： H03L1/026 , H03L7/1974
摘要： Film bulk acoustic resonators (FBARS) have resonant frequencies that vary with manufacturing variations, but tend to be matched when in proximity on an integrated circuit die. FBAR resonant frequency is determined using a fractional-N synthesizer and comparing phase/frequency of an output signal from the fractional-N synthesizer to a reference. The reference may be derived from a low frequency crystal oscillator, an external signal source, or a communications signal.
摘要翻译：薄膜体声共振器（FBARS）具有随着制造变化而变化的谐振频率，但是当在集成电路芯片附近时，它们倾向于匹配。使用分数N合成器确定FBAR谐振频率，并将来自分数N合成器的输出信号的相位/频率与参考值进行比较。该参考可以从低频晶体振荡器，外部信号源或通信信号导出。

8. 发明申请

US20090161802A1 RECEIVER WITH ADAPTIVE POWER CONSUMPTION AND A METHOD IMPLEMENTED THEREIN 审中-公开
标题翻译：具有自适应功耗的接收器及其实现的方法
公开(公告)号：US20090161802A1
公开(公告)日：2009-06-25
申请号：US11963482
申请日：2007-12-21
申请人： Pukar Malla , Hasnain Lakdawala , Soumyanath Krishnamurthy
发明人： Pukar Malla , Hasnain Lakdawala , Soumyanath Krishnamurthy
IPC分类号： H04L27/08 , H04B1/10
CPC分类号： H04B1/1036 , H03G3/3068
摘要： A receiver and a method for controlling power consumption therein are disclosed. The receiver comprises at least one front-end module, an amplifier, an Analog to Digital Converter (ADC) module, a spectrum analyzer and a control module. The at least one front-module is configured to receive and process a RF signal to obtain an IF signal. The amplifier is configured to amplify the IF signal received from the at least one front-end module with a variable gain. The ADC module receives the amplified IF signal and converts into a digital signal. Further, the spectrum analyzer estimates a power level of a signal information and a power level of a noise in the digital signal. Thereafter, the control module controls a variable gain of the amplifier and a variable dynamic range of the ADC based on the power level of the signal information and the noise in the digital signal.
摘要翻译：公开了一种用于控制功耗的接收机和方法。接收器包括至少一个前端模块，放大器，模数转换器（ADC）模块，频谱分析器和控制模块。所述至少一个前模块被配置为接收和处理RF信号以获得IF信号。放大器被配置为以可变增益放大从至少一个前端模块接收的IF信号。 ADC模块接收放大的IF信号并转换为数字信号。此外，频谱分析仪估计数字信号中的信号信息的功率电平和噪声的功率电平。此后，控制模块基于信号信息的功率电平和数字信号中的噪声来控制放大器的可变增益和ADC的可变动态范围。

9. 发明申请

US20120087390A1 THERMAL SENSOR DEVICE 审中-公开
标题翻译：热传感器装置
公开(公告)号：US20120087390A1
公开(公告)日：2012-04-12
申请号：US13328546
申请日：2011-12-16
申请人： Arijit RAYCHOWDHURY , Hasnain Lakdawala , Yee (William) Li , Greg Taylor , Soumyanath Krishnamurthy
发明人： Arijit RAYCHOWDHURY , Hasnain Lakdawala , Yee (William) Li , Greg Taylor , Soumyanath Krishnamurthy
IPC分类号： G01K7/01
CPC分类号： G01K7/015 , G01K2219/00
摘要： A thermal sensor is provided that includes a front-end component, an analog-to-digital converter and a digital backend. The front-end component including an array of current sources, a dynamic element matching (DEM) device, an analog chopper and two diodes to sense temperatures on the die. The front-end component to provide analog signals at two output nodes based on currents through the two diodes. The analog-to-digital converter to receive the analog signals from the front-end component and to provide an output signal. The digital backend to receive the output signal from the analog-to-digital converter and to provide a calculated temperature.
摘要翻译：提供了一种热传感器，其包括前端部件，模数转换器和数字后端。前端部件包括电流源阵列，动态元件匹配（DEM）器件，模拟斩波器和两个二极管，用于感测管芯上的温度。前端组件根据两个二极管的电流在两个输出节点提供模拟信号。模数转换器从前端组件接收模拟信号并提供输出信号。数字后端从模数转换器接收输出信号并提供计算温度。

10. 发明授权

US07812750B2 Sigma-delta converter noise cancellation 有权
标题翻译： Sigma-delta转换器噪声消除
公开(公告)号：US07812750B2
公开(公告)日：2010-10-12
申请号：US12239294
申请日：2008-09-26
申请人： Hasnain Lakdawala , Soumyanath Krishnamurthy
发明人： Hasnain Lakdawala , Soumyanath Krishnamurthy
IPC分类号： H03M3/00
CPC分类号： H03M3/344 , H03M3/46
摘要： Embodiments provide apparatuses, systems, and methods to convert an analog signal input into a sigma-delta digital output at a high sampling rate and correct for noise components of the digital output. An analog filter coupled to a sigma-delta converter accepts a noise-shaped analog signal from the sigma-delta converter to attenuate signal components of the noise-shaped analog signal at a plurality of folding frequencies associated with a sampling rate of a low-speed Analog-To-Digital (ADC) to produce a filtered output. The low-speed ADC is coupled to an output of the analog filter and samples the filtered output of the analog filter at a sampling rate slower than the high sample rate to output an ADC digital output. Other embodiments may be described and claimed.
摘要翻译：实施例提供了以高采样率将模拟信号输入转换成Σ-Δ数字输出并校正数字输出的噪声分量的装置，系统和方法。耦合到Σ-Δ转换器的模拟滤波器接收来自Σ-Δ转换器的噪声形模拟信号，以与低速采样率相关联的多个折叠频率衰减噪声形模拟信号的信号分量模数转换（ADC）产生滤波输出。低速ADC耦合到模拟滤波器的输出，并以低于采样率的采样速率对模拟滤波器的滤波后的输出采样，以输出ADC数字输出。可以描述和要求保护其他实施例。

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