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1. 发明申请

US20110317508A1 MEMORY WRITE OPERATION METHODS AND CIRCUITS 有权
标题翻译：存储器写操作方法和电路
公开(公告)号：US20110317508A1
公开(公告)日：2011-12-29
申请号：US12823642
申请日：2010-06-25
申请人： JAYDEEP P. KULKARNI , Muhammad M. Khellah , Bibiche M. Geuskens , Arijit Raychowdhury , Tanay Karnik , Vivek K. De
发明人： JAYDEEP P. KULKARNI , Muhammad M. Khellah , Bibiche M. Geuskens , Arijit Raychowdhury , Tanay Karnik , Vivek K. De
IPC分类号： G11C8/08
CPC分类号： G11C8/08 , G11C7/12 , G11C7/20 , G11C11/412 , G11C11/413
摘要： In some embodiments, write wordline boost may be obtained from wordline driver boost and/or from bit line access transistor boost.
摘要翻译：在一些实施例中，可以从字线驱动器升压和/或来自位线存取晶体管升压获得写入字线升压。

2. 发明授权

US08467263B2 Memory write operation methods and circuits 有权
标题翻译：存储器写操作方法和电路
公开(公告)号：US08467263B2
公开(公告)日：2013-06-18
申请号：US12823642
申请日：2010-06-25
申请人： Jaydeep P. Kulkarni , Muhammad M. Khellah , Bibiche M. Geuskens , Arijit Raychowdhury , Tanay Karnik , Vivek K. De
发明人： Jaydeep P. Kulkarni , Muhammad M. Khellah , Bibiche M. Geuskens , Arijit Raychowdhury , Tanay Karnik , Vivek K. De
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C7/12 , G11C7/20 , G11C11/412 , G11C11/413
摘要： In some embodiments, write wordline boost may be obtained from wordline driver boost and/or from bit line access transistor boost.
摘要翻译：在一些实施例中，可以从字线驱动器升压和/或来自位线存取晶体管升压获得写入字线升压。

3. 发明申请

US20110085389A1 METHOD AND SYSTEM TO LOWER THE MINIMUM OPERATING VOLTAGE OF A MEMORY ARRAY 有权
标题翻译：降低存储器阵列最小工作电压的方法和系统
公开(公告)号：US20110085389A1
公开(公告)日：2011-04-14
申请号：US12576868
申请日：2009-10-09
申请人： Muhammad M. Khellah , Bibiche M. Geuskens , Arijit Raychowdhury
发明人： Muhammad M. Khellah , Bibiche M. Geuskens , Arijit Raychowdhury
IPC分类号： G11C7/00 , G11C8/00 , G11C5/14
CPC分类号： G11C11/4085 , G11C5/145 , G11C11/4074 , G11C11/417
摘要： A method and system to lower the minimum operating voltage of a memory array during read and/or write operations of the memory array. In one embodiment of the invention, the voltage of the read and/or write word line of the memory array is boosted or increased during read and/or write operations of the memory array. By doing so, the NMOS devices in the memory array are strengthened and the contention between the NMOS and PMOS devices are reduced during read and/or write operations of the memory array. This helps to lower or reduce the required VCCmin of the memory array during read and/or write operations of the memory array.
摘要翻译：一种在存储器阵列的读取和/或写入操作期间降低存储器阵列的最小工作电压的方法和系统。在本发明的一个实施例中，存储器阵列的读取和/或写入字线的电压在存储器阵列的读取和/或写入操作期间升高或增加。通过这样做，存储器阵列中的NMOS器件被加强，并且在存储器阵列的读取和/或写入操作期间NMOS和PMOS器件之间的争用被减小。这有助于在存储器阵列的读取和/或写入操作期间降低或减少存储器阵列所需的VCCmin。

4. 发明授权

US08094505B2 Method and system to lower the minimum operating voltage of a memory array 有权
标题翻译：降低存储器阵列的最小工作电压的方法和系统
公开(公告)号：US08094505B2
公开(公告)日：2012-01-10
申请号：US12576868
申请日：2009-10-09
申请人： Muhammad M. Khellah , Bibiche M. Geuskens , Arijit Raychowdhury
发明人： Muhammad M. Khellah , Bibiche M. Geuskens , Arijit Raychowdhury
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/4085 , G11C5/145 , G11C11/4074 , G11C11/417
摘要： A method and system to lower the minimum operating voltage of a memory array during read and/or write operations of the memory array. In one embodiment of the invention, the voltage of the read and/or write word line of the memory array is boosted or increased during read and/or write operations of the memory array. By doing so, the NMOS devices in the memory array are strengthened and the contention between the NMOS and PMOS devices are reduced during read and/or write operations of the memory array. This helps to lower or reduce the required VCCmin of the memory array during read and/or write operations of the memory array.
摘要翻译：一种在存储器阵列的读取和/或写入操作期间降低存储器阵列的最小工作电压的方法和系统。在本发明的一个实施例中，存储器阵列的读取和/或写入字线的电压在存储器阵列的读取和/或写入操作期间升高或增加。通过这样做，存储器阵列中的NMOS器件被加强，并且在存储器阵列的读取和/或写入操作期间NMOS和PMOS器件之间的争用被减小。这有助于在存储器阵列的读取和/或写入操作期间降低或减少存储器阵列所需的VCCmin。

5. 发明授权

US08901819B2 Multi-supply sequential logic unit 有权
标题翻译：多电源顺序逻辑单元
公开(公告)号：US08901819B2
公开(公告)日：2014-12-02
申请号：US13992894
申请日：2011-12-14
申请人： Arijit Raychowdhury , Jaydeep P. Kulkarni , James W. Tschanz
发明人： Arijit Raychowdhury , Jaydeep P. Kulkarni , James W. Tschanz
IPC分类号： H03K19/0175
CPC分类号： H03K19/017509 , G06F1/10 , G06F1/3296 , Y02D10/172
摘要： Described herein are apparatus, method, and system for reducing clock-to-output delay of a sequential logic unit in a processor. The apparatus comprises a sequential unit including: a data path, to receive an input signal, including logic gates to operate on a first power supply level, the data path to generate an output signal; and a clock path including logic gates to operate on a second power supply level, the logic gates of the clock path to sample the input signal using a sampling signal to generate the output signal, wherein the second power supply level is higher than the first power supply level. The apparatus improves (i.e. reduces) setup time of the sequential unit and allows the processor to operate at minimum operating voltage (Vmin) without degrading performance of the sequential unit.
摘要翻译：这里描述了用于减少处理器中的顺序逻辑单元的时钟到输出延迟的装置，方法和系统。所述装置包括顺序单元，包括：数据路径，用于接收输入信号，包括在第一电源电平上操作的逻辑门，所述数据路径以产生输出信号; 以及时钟路径，包括用于在第二电源电平上操作的逻辑门，所述时钟路径的逻辑门使用采样信号对所述输入信号进行采样以产生所述输出信号，其中所述第二电源电平高于所述第一电力供应水平。该装置改善（即减少）顺序单元的建立时间，并允许处理器以最小工作电压（Vmin）运行，而不降低顺序单元的性能。

6. 发明申请

US20140218069A1 MULTI-SUPPLY SEQUENTIAL LOGIC UNIT 有权
标题翻译：多供应序列逻辑单元
公开(公告)号：US20140218069A1
公开(公告)日：2014-08-07
申请号：US13992894
申请日：2011-12-14
申请人： Arijit Raychowdhury , Jaydeep P. Kulkarni , James W. Tschanz
发明人： Arijit Raychowdhury , Jaydeep P. Kulkarni , James W. Tschanz
IPC分类号： H03K19/0175
CPC分类号： H03K19/017509 , G06F1/10 , G06F1/3296 , Y02D10/172
摘要： Described herein are apparatus, method, and system for reducing clock-to-output delay of a sequential logic unit in a processor. The apparatus comprises a sequential unit including: a data path, to receive an input signal, including logic gates to operate on a first power supply level, the data path to generate an output signal; and a clock path including logic gates to operate on a second power supply level, the logic gates of the clock path to sample the input signal using a sampling signal to generate the output signal, wherein the second power supply level is higher than the first power supply level. The apparatus improves (i.e. reduces) setup time of the sequential unit and allows the processor to operate at minimum operating voltage (Vmin) without degrading performance of the sequential unit.
摘要翻译：这里描述了用于减少处理器中的顺序逻辑单元的时钟到输出延迟的装置，方法和系统。所述装置包括顺序单元，包括：数据路径，用于接收输入信号，包括在第一电源电平上操作的逻辑门，所述数据路径以产生输出信号; 以及时钟路径，包括用于在第二电源电平上操作的逻辑门，所述时钟路径的逻辑门使用采样信号对所述输入信号进行采样以产生所述输出信号，其中所述第二电源电平高于所述第一电力供应水平。该装置改善（即减少）顺序单元的建立时间，并允许处理器以最小工作电压（Vmin）运行，而不降低顺序单元的性能。

7. 发明授权

US07961498B2 Leakage compensation circuit for Dynamic Random Access Memory (DRAM) cells 有权
标题翻译：用于动态随机存取存储器（DRAM）单元的泄漏补偿电路
公开(公告)号：US07961498B2
公开(公告)日：2011-06-14
申请号：US12236302
申请日：2008-09-23
申请人： DiaaEldin S. Khalil , Arijit Raychowdhury , Muhammad M. Khellah , Ali Keshavarzi
发明人： DiaaEldin S. Khalil , Arijit Raychowdhury , Muhammad M. Khellah , Ali Keshavarzi
IPC分类号： G11C11/24
CPC分类号： G11C8/14 , G11C11/404 , G11C11/4085 , G11C11/4094
摘要： A Dynamic Random Access Memory (DRAM) cell comprising a leakage compensation circuit. The leakage compensation circuit allows a compensation current from a source to flow to the memory cell storage node of the DRAM cell to compensate the leakage current from the memory cell storage node of the DRAM cell to improve retention time.
摘要翻译：一种包括泄漏补偿电路的动态随机存取存储器（DRAM）单元。泄漏补偿电路允许来自源的补偿电流流向DRAM单元的存储单元存储节点，以补偿来自DRAM单元的存储单元存储节点的泄漏电流，以改善保持时间。

8. 发明授权

US09484917B2 Digital clamp for state retention 有权
标题翻译：数字钳位状态保持
公开(公告)号：US09484917B2
公开(公告)日：2016-11-01
申请号：US13718372
申请日：2012-12-18
申请人： Arijit Raychowdhury , Charles Augustine , James W. Tschanz , Vivek K. De
发明人： Arijit Raychowdhury , Charles Augustine , James W. Tschanz , Vivek K. De
IPC分类号： G05F1/10 , G05F1/59 , H03K19/00 , G05F1/46
CPC分类号： H03K19/0016 , G05F1/10 , G05F1/461 , G05F1/59 , G06F1/3287 , G06F1/3296 , H03K3/0377 , H03K19/0008
摘要： Described is an apparatus which comprises: a clamp coupled between a first power supply and a second power supply; and a circuit to operate with the second power supply, wherein the clamp is operable to adjust the second power supply when the apparatus enters a low power mode.
摘要翻译：描述了一种装置，其包括：耦合在第一电源和第二电源之间的夹具; 以及用于与第二电源操作的电路，其中当所述设备进入低功率模式时，所述钳位器可操作以调节所述第二电源。

9. 发明申请

US20140167813A1 DIGITAL CLAMP FOR STATE RETENTION 有权
标题翻译：用于国家保留的数字钳
公开(公告)号：US20140167813A1
公开(公告)日：2014-06-19
申请号：US13718372
申请日：2012-12-18
申请人： Arijit Raychowdhury , Charles Augustine , James W. Tschanz , Vivek K. De
发明人： Arijit Raychowdhury , Charles Augustine , James W. Tschanz , Vivek K. De
IPC分类号： H03K19/00
CPC分类号： H03K19/0016 , G05F1/10 , G05F1/461 , G05F1/59 , G06F1/3287 , G06F1/3296 , H03K3/0377 , H03K19/0008
摘要： Described is an apparatus which comprises: a clamp coupled between a first power supply and a second power supply; and a circuit to operate with the second power supply, wherein the clamp is operable to adjust the second power supply when the apparatus enters a low power mode.
摘要翻译：描述了一种装置，其包括：耦合在第一电源和第二电源之间的夹具; 以及用于与第二电源操作的电路，其中当所述设备进入低功率模式时，所述钳位器可操作以调节所述第二电源。

10. 发明授权

US09121768B2 Thermal sensor device 有权
标题翻译：热传感器装置
公开(公告)号：US09121768B2
公开(公告)日：2015-09-01
申请号：US13328546
申请日：2011-12-16
申请人： Arijit Raychowdhury , Hasnain Lakdawala , Yee (William) Li , Greg Taylor , Soumyanath Krishnamurthy
发明人： Arijit Raychowdhury , Hasnain Lakdawala , Yee (William) Li , Greg Taylor , Soumyanath Krishnamurthy
IPC分类号： G01K7/00 , G01K7/01
CPC分类号： G01K7/015 , G01K2219/00
摘要： A thermal sensor is provided that includes a front-end component, an analog-to-digital converter and a digital backend. The front-end component including an array of current sources, a dynamic element matching (DEM) device, an analog chopper and two diodes to sense temperatures on the die. The front-end component to provide analog signals at two output nodes based on currents through the two diodes. The analog-to-digital converter to receive the analog signals from the front-end component and to provide an output signal. The digital backend to receive the output signal from the analog-to-digital converter and to provide a calculated temperature.
摘要翻译：提供了一种热传感器，其包括前端部件，模数转换器和数字后端。前端部件包括电流源阵列，动态元件匹配（DEM）器件，模拟斩波器和两个二极管，用于感测管芯上的温度。前端组件根据两个二极管的电流在两个输出节点提供模拟信号。模数转换器从前端组件接收模拟信号并提供输出信号。数字后端从模数转换器接收输出信号并提供计算温度。

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