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1. 发明授权

US07298838B2 Adaptive cancellation network system and method for digital subscriber line 有权
标题翻译：数字用户线自适应消除网络系统及方法
公开(公告)号：US07298838B2
公开(公告)日：2007-11-20
申请号：US10234510
申请日：2002-09-03
申请人： Sandeep K. Oswal , Prakash Easwaran , Arijit Raychowdhury , Fernando A. Mujica
发明人： Sandeep K. Oswal , Prakash Easwaran , Arijit Raychowdhury , Fernando A. Mujica
IPC分类号： H04M1/00
CPC分类号： H04B3/23
摘要： A method for reducing transmit echo in a DSL modem comprises selecting at least one cancellation device of a plurality of cancellation devices. An attenuation signal is generated using the selected cancellation device. At least a portion of transmit echo is removed from a receive signal using the attenuation signal.
摘要翻译：一种用于减少DSL调制解调器中的发射回波的方法包括：选择多个取消装置的至少一个消除装置。使用所选择的取消装置产生衰减信号。使用衰减信号从接收信号中去除发射回波的至少一部分。

2. 发明申请

US20110128172A1 LOW POWER CONVERT AND SHUTDOWN SAR ADC ARCHITECTURE 有权
标题翻译：低功耗转换和关断SAR ADC架构
公开(公告)号：US20110128172A1
公开(公告)日：2011-06-02
申请号：US12776109
申请日：2010-05-07
申请人： Raghu N. Srinivasa , Sandeep K. Oswal
发明人： Raghu N. Srinivasa , Sandeep K. Oswal
IPC分类号： H03M1/00 , H03M1/12
CPC分类号： H03M1/002 , H03M1/14 , H03M1/468
摘要： With Successive Approximation Register (SAR) analog-to-digital converters (ADCs), there are several different architectures. One of these architectures is a “convert and shut down” architecture, where an internal amplifier is powered down during the sampling phase to reduce power consumption. This powering down comes at a price in that a portion of the convert phase is lost waiting for the amplifier to be powered back up. Here, an apparatus is provided that makes use of the entire convert phase by coarsely resolving a few bits during the period in which the amplifier is powering up to have an increased resolution over conventional SAR ADCs with “convert and shut down” architecture, while maintaining low power consumption.
摘要翻译：使用逐次近似寄存器（SAR）模数转换器（ADC），有几种不同的架构。这些架构之一是“转换和关闭”架构，其中内部放大器在采样阶段关闭以降低功耗。这种掉电的代价是，转换阶段的一部分丢失等待放大器被加电。这里，提供了一种装置，其通过在放大器上电时间段内粗略地分辨几比特以使其具有比具有“转换和关闭”架构的常规SAR ADC更高的分辨率，同时维持低功耗

3. 发明授权

US07948410B2 Multibit recyclic pipelined ADC architecture 有权
标题翻译：多位循环流水线ADC结构
公开(公告)号：US07948410B2
公开(公告)日：2011-05-24
申请号：US12639705
申请日：2009-12-16
申请人： Jagannathan Venkataraman , Visvesvaraya A. Pentakota , Sandeep K. Oswal , Samarth S. Modi , Shagun Dusad
发明人： Jagannathan Venkataraman , Visvesvaraya A. Pentakota , Sandeep K. Oswal , Samarth S. Modi , Shagun Dusad
IPC分类号： H03M1/00
CPC分类号： H03M1/0695 , H03M1/167
摘要： An apparatus is provided. The apparatus comprises a sample switch, a sampling capacitor, an amplifier, feedback branches, a second hold switch, an N-bit converter pair, a third hold switch, and an M-bit converter pair. The sample receives an input signal and is actuated by a sample signal. The sampling capacitor is coupled to the sample switch. The amplifier has a first input terminal that is coupled to the sampling capacitor. The feedback branches are coupled between the output terminal of the amplifier and the first input terminal of the amplifier, with each feedback branch including a feedback capacitor, and a first hold switch that is coupled to the feedback capacitor. The second hold switch is coupled to the sampling switch. The N-bit converter pair is coupled to the sampling switch and to the second hold switch. The third hold switch is coupled to at least one of the feedback branches, and the M-bit converter pair is coupled to the output terminal of the amplifier and to the third hold switch.
摘要翻译：提供了一种装置。该装置包括采样开关，采样电容器，放大器，反馈分支，第二保持开关，N位转换器对，第三保持开关和M位转换器对。样本接收输入信号并由样本信号启动。采样电容器耦合到采样开关。放大器具有耦合到采样电容器的第一输入端。反馈支路耦合在放大器的输出端和放大器的第一输入端之间，每个反馈支路包括反馈电容器，以及耦合到反馈电容器的第一保持开关。第二保持开关耦合到采样开关。 N位转换器对耦合到采样开关和第二保持开关。第三保持开关耦合到至少一个反馈支路，并且M位转换器对耦合到放大器的输出端和第三保持开关。

4. 发明申请

US20110012764A1 MULTIBIT RECYCLIC PIPELINED ADC ARCHITECTURE 有权
标题翻译：多重循环管道ADC架构
公开(公告)号：US20110012764A1
公开(公告)日：2011-01-20
申请号：US12639705
申请日：2009-12-16
申请人： Jagannathan Venkataraman , Visvesvaraya A. Pentakota , Sandeep K. Oswal , Samarth S. Modi , Shagun Dusad
发明人： Jagannathan Venkataraman , Visvesvaraya A. Pentakota , Sandeep K. Oswal , Samarth S. Modi , Shagun Dusad
IPC分类号： H03M1/00 , H03M1/12
CPC分类号： H03M1/0695 , H03M1/167
摘要： An apparatus is provided. The apparatus comprises a sample switch, a sampling capacitor, an amplifier, feedback branches, a second hold switch, an N-bit converter pair, a third hold switch, and an M-bit converter pair. The sample receives an input signal and is actuated by a sample signal. The sampling capacitor is coupled to the sample switch. The amplifier has a first input terminal that is coupled to the sampling capacitor. The feedback branches are coupled between the output terminal of the amplifier and the first input terminal of the amplifier, with each feedback branch including a feedback capacitor, and a first hold switch that is coupled to the feedback capacitor. The second hold switch is coupled to the sampling switch. The N-bit converter pair is coupled to the sampling switch and to the second hold switch. The third hold switch is coupled to at least one of the feedback branches, and the M-bit converter pair is coupled to the output terminal of the amplifier and to the third hold switch.
摘要翻译：提供了一种装置。该装置包括采样开关，采样电容器，放大器，反馈分支，第二保持开关，N位转换器对，第三保持开关和M位转换器对。样本接收输入信号并由样本信号启动。采样电容器耦合到采样开关。放大器具有耦合到采样电容器的第一输入端。反馈支路耦合在放大器的输出端和放大器的第一输入端之间，每个反馈支路包括反馈电容器，以及耦合到反馈电容器的第一保持开关。第二保持开关耦合到采样开关。 N位转换器对耦合到采样开关和第二保持开关。第三保持开关耦合到至少一个反馈支路，并且M位转换器对耦合到放大器的输出端和第三保持开关。

5. 发明授权

US06847321B1 Closed loop amplification with high throughput performance 有权
标题翻译：具有高吞吐量性能的闭环放大
公开(公告)号：US06847321B1
公开(公告)日：2005-01-25
申请号：US10706030
申请日：2003-11-13
申请人： Visvesvaraya A. Pentakota , Sandeep K. Oswal
发明人： Visvesvaraya A. Pentakota , Sandeep K. Oswal
IPC分类号： H03F1/34 , H03M1/06 , H03M1/10 , H03M1/12
CPC分类号： H03M1/0604
摘要： Using an operational amplifier with a low gain in a closed loop amplifier circuit, and correcting for errors (i.e., deviation from the output of an ideal closed loop amplifier using an operational amplifier with infinite gain) that would result from the use of the operational amplifier with low gain. In an embodiment implemented in relation to an analog to digital converter (ADC), a mathematical operation is performed on the digital code(s) generated by the ADC to generate a corrected code corresponding to an analog sample.
摘要翻译：在闭环放大器电路中使用具有低增益的运算放大器，并且通过使用运算放大器来校正误差（即，使用具有无限增益的运算放大器的理想闭环放大器的输出的偏差）低增益。在关于模数转换器（ADC）实现的实施例中，对由ADC生成的数字代码执行数学运算，以产生对应于模拟采样的校正代码。

6. 发明授权

US08159382B2 Low power converter and shutdown SAR ADC architecture 有权
标题翻译：低功耗转换器和关断SAR ADC架构
公开(公告)号：US08159382B2
公开(公告)日：2012-04-17
申请号：US12776109
申请日：2010-05-07
申请人： Raghu N. Srinivasa , Sandeep K. Oswal
发明人： Raghu N. Srinivasa , Sandeep K. Oswal
IPC分类号： H03M1/12
CPC分类号： H03M1/002 , H03M1/14 , H03M1/468
摘要： With Successive Approximation Register (SAR) analog-to-digital converters (ADCs), there are several different architectures. One of these architectures is a “convert and shut down” architecture, where an internal amplifier is powered down during the sampling phase to reduce power consumption. This powering down comes at a price in that a portion of the convert phase is lost waiting for the amplifier to be powered back up. Here, an apparatus is provided that makes use of the entire convert phase by coarsely resolving a few bits during the period in which the amplifier is powering up to have an increased resolution over conventional SAR ADCs with “convert and shut down” architecture, while maintaining low power consumption.
摘要翻译：使用逐次近似寄存器（SAR）模数转换器（ADC），有几种不同的架构。这些架构之一是“转换和关闭”架构，其中内部放大器在采样阶段关闭以降低功耗。这种掉电的代价是，转换阶段的一部分丢失等待放大器被加电。这里，提供了一种装置，其通过在放大器上电时间段内粗略地分辨几比特以使其具有比具有“转换和关闭”架构的常规SAR ADC更高的分辨率，同时维持低功耗

7. 发明授权

US07176749B2 Avoiding excessive cross-terminal voltages of low voltage transistors due to undesirable supply-sequencing in environments with higher supply voltages 有权
标题翻译：在较高电源电压的环境中，由于不合需要的电源顺序，避免了过低的低压晶体管电压
公开(公告)号：US07176749B2
公开(公告)日：2007-02-13
申请号：US10711532
申请日：2004-09-24
申请人： Bhupendra Sharma , Sudheer Prasad , Sandeep K. Oswal
发明人： Bhupendra Sharma , Sudheer Prasad , Sandeep K. Oswal
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F3/205
摘要： Ensuring sufficient bias current is provided to a portion of a circuit containing low voltage transistors operating with a high supply voltage. Such a sufficient bias current may be ensured by generating a primary bias current from a low supply voltage and a backup bias current from a high supply voltage, and providing the backup bias current as the bias current if the primary bias current is not present. The primary bias current may be provided as the bias current when the low supply voltage is available. Thus, the backup bias current is provided as bias current in case of undesirable supply sequencing.
摘要翻译：确保足够的偏置电流被提供给包含以高电源电压工作的低压晶体管的电路的一部分。可以通过从低电源电压和来自高电源电压的备用偏置电流产生初级偏置电流来确保这种足够的偏置电流，并且如果不存在初级偏置电流，则提供备用偏置电流作为偏置电流。当低电源电压可用时，初级偏置电流可以作为偏置电流提供。因此，在不期望的电源顺序的情况下，备用偏置电流被提供为偏置电流。

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