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1. 发明授权

US11688432B2 Disk drive and carrier assembly 有权
公开(公告)号：US11688432B2
公开(公告)日：2023-06-27
申请号：US17099288
申请日：2020-11-16
申请人： International Business Machines Corporation
发明人： Jonathan Oswaldo Lara Dominguez , Victor Arturo Tapia Jimenez , Luis Cruz Mejia , Oscar Eduardo Flores Pantoja , Jesus Ernesto Ibarra Hernandez
IPC分类号： G11B5/127 , H04R31/00 , G11B33/12 , G06F1/18 , G11C5/12
CPC分类号： G11B33/128 , G06F1/187 , G11C5/12 , Y10T29/53165
摘要： An approach for assembling a hard drive to a hard drive carrier is provided. The approach includes an ergonomic tool to aid with assembly. The ergonomic tool allows for a reduction in assembly time and prevents damage to the components. The ergonomic tool comprising of a base having a first surface and a first end open for receiving the components. The tool has a set of walls rising from the base, a first wall rising from the base proximate a second end opposite the first end and a pair of opposing side walls including voids rising from the first surface between the first end and the second end, to form a slot there between to receive the components within and adjacent the first surface. The tool has a releasable hold mechanism that aligns the components during assembly.

2. 发明授权

US07741204B2 Mixed-scale electronic interfaces 失效
标题翻译：混合电子接口
公开(公告)号：US07741204B2
公开(公告)日：2010-06-22
申请号：US11590492
申请日：2006-10-30
申请人： Zhiyong Li , Warren Robinett
发明人： Zhiyong Li , Warren Robinett
IPC分类号： H01L21/44
CPC分类号： G11C5/06 , B82B1/00 , B82B3/00 , B82Y10/00 , B82Y40/00 , G11C5/12 , G11C2213/81 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L51/0595 , Y10S977/762 , Y10S977/94
摘要： Certain embodiments of the present invention are directed to a method of fabricating a mixed-scale electronic interface. A substrate is provided with a first set of conductive elements. A first layer of nanowires may be formed over the first set of conductive elements. A number of channels may be formed, with each of the channels extending diagonally through a number of the nanowires of the first layer. A number of pads may be formed, each of which is electrically interconnected with an underlying conductive element of the first set of conductive elements and one or more adjacent nanowires of the first layer of nanowires. The pads and corresponding electrically interconnected nanowires define a number of pad-interconnected-nanowire-units. Additional embodiments are directed to a method of forming a nanoimprinting mold and a method of selectively programming nanowire-to-conductive element electrical connections.
摘要翻译：本发明的某些实施例涉及一种制造混合比例电子接口的方法。衬底设置有第一组导电元件。可以在第一组导电元件上形成第一层纳米线。可以形成多个通道，其中每个通道对角地延伸穿过第一层的多个纳米线。可以形成多个焊盘，每个焊盘与第一组导电元件的下面的导电元件和第一纳米线层的一个或多个相邻的纳米线电互连。焊盘和相应的电互连纳米线限定了多个衬垫互连的纳米线单元。另外的实施例涉及形成纳米压印模具的方法和选择性地编程纳米线至导电元件电连接的方法。

3. 发明授权

US06681271B2 Computer system for multi-type DRAM support 失效
标题翻译：用于多种DRAM支持的计算机系统
公开(公告)号：US06681271B2
公开(公告)日：2004-01-20
申请号：US09931946
申请日：2001-08-20
申请人： Tsai Chih-Hung , Li-Te Cheng , Wu Shun-Cheng , Kun-Feng Cheng , An-Chung Chen , Horng-Sheng Chen
发明人： Tsai Chih-Hung , Li-Te Cheng , Wu Shun-Cheng , Kun-Feng Cheng , An-Chung Chen , Horng-Sheng Chen
IPC分类号： G06F500
CPC分类号： G11C5/12 , G11C5/06
摘要： A computer system for multi-type DRAM support includes a first slot for receiving a first type DRAM, a second slot for receiving a second type DRAM, a north bridge chip, and a control circuit. The first slot includes a plurality of first slot pins, and each of them corresponds to a first pin assignment. The second slot includes a plurality of second slot pins, and each of them corresponds to a second pin assignment. The north bridge chip includes a plurality of chip pins, and each of them corresponds to a first and second pin assignment. When the control circuit generates a first control signal, the pin assignments of the chip pins are defined as the first pin assignments. When the control circuit generates a second control signal, the pin assignments of the chip pins are defined as the second pin assignments.
摘要翻译：用于多类型DRAM支持的计算机系统包括用于接收第一类型DRAM的第一时隙，用于接收第二类型DRAM的第二时隙，北桥芯片和控制电路。第一槽包括多个第一槽口销，并且它们中的每一个对应于第一销分配。第二槽包括多个第二槽销，并且它们中的每一个对应于第二销分配。北桥芯片包括多个芯片引脚，并且它们中的每一个对应于第一和第二引脚分配。当控制电路产生第一控制信号时，芯片引脚的引脚分配被定义为第一引脚分配。当控制电路产生第二控制信号时，芯片引脚的引脚分配被定义为第二引脚分配。

4. 发明授权

US3887904A Wire mass termination 失效
标题翻译：电线质量终止
公开(公告)号：US3887904A
公开(公告)日：1975-06-03
申请号：US39035773
申请日：1973-08-22
申请人： ELECTRONIC MEMORIES & MAGNETIC
发明人： KRAG NIELS
IPC分类号： G11C5/12 , G11C5/08 , H01F41/10
CPC分类号： G11C5/12 , Y10T29/49069 , Y10T29/49162 , Y10T29/49165
摘要： Electrical wires extending through magnetic cores on a circuit board are fixed near their ends to the board by projecting portions of the wires through holes in the board to form wire loops in the holes, and retaining the loops in place temporarily prior to soldering them in place. Temporary retention of the wire loops can be accomplished with retainers mounted on the lower side of the board, each retainer being a sheet-like portion of conductive material with a large diameter central hole and a pair of narrow slits extending in opposite directions from the central hole. A plunger forces the wires down through the holes in the board and the central hole in the retainer, while the wires are maintained in tension, so that the wires enter the slits in the retainer and are captured therein. In another method, the wire loops are held by adhesive or are bent over to temporarily hold them in place.
摘要翻译：通过电路板上的磁芯延伸的电线通过将电线的一部分突出通过板上的孔而突出地固定在它们的端部附近，从而在孔中形成线环，并且在将它们焊接到位之前暂时保持环。线环的暂时保持可以通过安装在板的下侧的保持器来实现，每个保持器是具有大直径中心孔的导电材料的片状部分和从中心向相反方向延伸的一对狭窄狭缝孔。柱塞将电线向下推动通过电路板上的孔和保持器中的中心孔，同时电线保持张力，使得电线进入保持器中的狭缝并被捕获在其中。在另一种方法中，线环由粘合剂保持或弯曲以暂时保持在适当的位置。

5. 发明授权

US3875659A Method and apparatus for successive delivery and positioning of pole cores and device for effecting same 失效
标题翻译：用于连续输送和定位圆角的方法和装置以及用于影响其的装置
公开(公告)号：US3875659A
公开(公告)日：1975-04-08
申请号：US42215073
申请日：1973-12-06
申请人： BURKIN JURY ALEXANDROVICH , SELEZNEV JURY EMELYANOVICH
发明人： BURKIN JURY ALEXANDROVICH , SELEZNEV JURY EMELYANOVICH
IPC分类号： G11C5/12 , H01F7/06
CPC分类号： G11C5/12 , Y10T29/49069 , Y10T29/49838 , Y10T29/53165 , Y10T29/53691 , Y10T29/53696
摘要： A method for successive delivery and positioning of pole cores. The pole cores are strung in a stack upon a wire, the stack being prevented from sliding down along the wire by means of a stop. The lower pole core in the stack is pressed against an additional member, and the upper portion of the wire with the stack is bent along the profile of the additional member so that the lower pole core is delivered, in an oriented position, for threading, counting or checking, the lower pole core being removed following a completion of one of said operations. A device for effecting the above method comprises a wire with pole cores strung in a stack thereon, movable wire holders, a stop disposed under the stack, and an additional member which is a profiled prism-shaped strip.

6. 发明授权

US3859720A Method of manufacturing memory stacks 失效
标题翻译：制造存储堆栈的方法
公开(公告)号：US3859720A
公开(公告)日：1975-01-14
申请号：US42886073
申请日：1973-12-27
申请人： BURKIN JURY ALEXANDROVICH , SELEZNEV JURY EMELYANOVICH
发明人： BURKIN JURY ALEXANDROVICH , SELEZNEV JURY EMELYANOVICH
IPC分类号： G11C5/08 , G11C5/12 , H01F7/06
CPC分类号： G11C5/08 , G11C5/12 , Y10T29/49069 , Y10T29/49812 , Y10T29/49838 , Y10T29/49881 , Y10T29/53691
摘要： A method for manufacturing memory stacks, whereby pole cores are strung in piles upon wires and the pole core piles thus formed are arranged in a row so as to be parallel and equidistant to one another, upon an adhesive elastic substrate. The substrate is then stretched, thus separating the pole cores in the piles from one another this operation is followed by threading the pole cores with a coiled wire and subsequently straightening the coiled wire, to produce a memory matrix row to be stacked in the memory stack being manufactured.
摘要翻译：一种用于制造存储堆叠的方法，其中极芯在电线上被堆叠在一起，并且由此形成的极芯堆叠被布置成彼此平行和等距的粘合弹性基底。然后将基板拉伸，从而将桩中的极芯彼此分开，然后用线圈螺纹使磁极芯螺纹连接，随后矫直线圈，以产生要堆叠在存储器堆叠中的存储矩阵行被制造。

7. 发明授权

US3858294A Device for making memory storage matrices 失效
标题翻译：用于制作存储存储矩阵的设备
公开(公告)号：US3858294A
公开(公告)日：1975-01-07
申请号：US38841473
申请日：1973-08-15
申请人： BURKIN JURY ALEXANDROVICH , SELEZNEV JURY EMELYANOVICH
发明人： BURKIN JURY ALEXANDROVICH , SELEZNEV JURY EMELYANOVICH
IPC分类号： G11C5/12 , H01F3/10 , H01F7/06
CPC分类号： G11C5/12 , H01F3/10 , Y10T29/49069 , Y10T29/53165
摘要： A device for making memory storage matrices comprising a wire tensioning means for Y drive wires provided with individual weights for each pair of the Y axis drive wires, each weight taking the form of a plate and having a recess disposed in the proximity to the upper edge of the weight which accommodates a pulley gripping the middle of a Y axis drive wire with cores strung at both of its ends, making it possible to increase the supply of core-stringing the wires, which considerably improves the uniformity of wire tensioning and provides for a more reliable checking of the electrical characteristics of the cores during the threading thereof.
摘要翻译：一种用于制造存储器存储矩阵的装置，包括用于Y驱动线的线张紧装置，所述Y驱动线为每对Y轴驱动线提供单独的重物，每个重量采取板的形式，并且具有设置在靠近上边缘的重量，其容纳夹着Y轴驱动线的中心的皮带，其中两个端部具有芯，使得可以增加芯线的引线供应，这显着地改善了线张紧的均匀性，并且提供核心在其线程期间的电特性的更可靠的检查。

8. 发明授权

US3520052A Method of manufacturing matrix arrangements 失效
标题翻译：制造矩阵布置方法
公开(公告)号：US3520052A
公开(公告)日：1970-07-14
申请号：US3520052D
申请日：1966-03-08
申请人： PHILIPS CORP
发明人： HOFFMANN HANS
IPC分类号： G11C5/02 , G11C5/04 , G11C5/12 , G11C11/14 , G11C11/15 , G11C11/34 , H01J7/06
CPC分类号： G11C11/15 , G11C5/02 , G11C5/04 , G11C5/12 , G11C11/14 , G11C11/34 , Y10S148/085 , Y10T29/49069 , Y10T29/49124

9. 发明授权

US3391396A Magnetic wire memory and core access switch array 失效
标题翻译：磁线存储器和核心存取开关阵列
公开(公告)号：US3391396A
公开(公告)日：1968-07-02
申请号：US35995064
申请日：1964-04-15
申请人： BELL TELEPHONE LABOR INC
发明人： MCALEXANDER JR JOSEPH C
IPC分类号： G11C5/02 , G11C5/12 , G11C11/06
CPC分类号： G11C5/12 , G11C5/02 , G11C11/06 , Y10T29/49069

10. 发明授权

US09455011B2 Methods and systems to read a magnetic tunnel junction (MTJ) based memory cell based on a pulsed read current 有权
标题翻译：基于脉冲读取电流读取基于磁隧道结（MTJ）的存储单元的方法和系统
公开(公告)号：US09455011B2
公开(公告)日：2016-09-27
申请号：US14350997
申请日：2012-03-25
申请人： Arijit Raychowdhury , David Kencke , Brian Doyle , Charles Kuo , James Tschanz , Fatih Hamzaoglu , Yih Wang , Roksana Golizadeh Mojarad
发明人： Arijit Raychowdhury , David Kencke , Brian Doyle , Charles Kuo , James Tschanz , Fatih Hamzaoglu , Yih Wang , Roksana Golizadeh Mojarad
IPC分类号： G11C11/00 , G11C11/16 , G11C5/12 , G11C13/00
CPC分类号： G11C11/165 , G11C5/12 , G11C11/1673 , G11C11/1693 , G11C2013/0052 , G11C2013/0071
摘要： Methods and systems to read a logic value stored in a magnetic tunnel junction (MTJ)-based memory cell based on a pulsed read current, with time between pulses to permit the MTJ to relax towards the magnetization orientation between the pulses, which may reduce build-up of momentum within the MTJ, and which may reduce and/or eliminate inadvertent re-alignment of a magnetization orientation. A sequence of symmetric and/or non-symmetric pulses may be applied to a wordline (WL) to cause a pre-charged bit line (BL) capacitance to discharge a pulsed read current through the MTJ, resulting in a corresponding sequence of voltage changes on the BL. The BL voltage changes may be integrated over the sequence of read current pulses, and a stored logic value may be determined based on the integrated voltage changes. The pre-charged BL capacitance may also serve as the voltage integrator.
摘要翻译：基于脉冲读取电流读取存储在基于磁隧道结（MTJ）的存储单元中的逻辑值的方法和系统，脉冲之间的时间允许MTJ朝向脉冲之间的磁化取向松弛，这可以减少构建 - MTJ内的动量，并且其可以减少和/或消除磁化取向的无意重新对准。对称和/或非对称脉冲的序列可以被施加到字线（WL），以使预充电位线（BL）电容放电通过MTJ的脉冲读取电流，从而产生相应的电压变化序列在BL上。可以在读取电流脉冲的序列上积分BL电压变化，并且可以基于积分的电压变化来确定存储的逻辑值。预充电的BL电容也可以用作电压积分器。

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