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1. 发明申请

US20090063666A1 Network and Method for the Configuration Thereof 有权
标题翻译：网络及其配置方法
公开(公告)号：US20090063666A1
公开(公告)日：2009-03-05
申请号：US12190960
申请日：2008-08-13
申请人： Frank Scholz , Dirk Bolte , Friedrich Michael Welter , Martin Kuenzel , Friedemann Baitinger , Andreas Bieswanger , Juergen Saalmueller , Andreas Arnez
发明人： Frank Scholz , Dirk Bolte , Friedrich Michael Welter , Martin Kuenzel , Friedemann Baitinger , Andreas Bieswanger , Juergen Saalmueller , Andreas Arnez
IPC分类号： G06F15/177
CPC分类号： H04L41/26 , H04L41/0803 , H04L41/12
摘要： A method and corresponding apparatus is provided for determining the location of a configuration server being connected to a totally symmetric network infrastructure that does not exhibit any symmetry breakers on network level. The configuration server reaches a decision to determine its network-wide unique configuration in order to be able to serve controllers. This decision depends on the plug position of the configuration server under consideration and the assumption of plugging rules governing a “good” network infrastructure. The controllers periodically send network packets that will be marked if they traverse specific connection elements in the network. The origin and the path of a network packet can be determined. The decision making is based on a majority function based on the packets received by the configuration server. If a decision cannot be made, then errors in the cabling structure can be detected.
摘要翻译：提供了一种方法和相应的装置，用于确定连接到在网络级别上不呈现任何对称断路器的完全对称网络基础设施的配置服务器的位置。配置服务器决定确定其全网络唯一配置，以便能够为控制器提供服务。该决定取决于正在考虑的配置服务器的插头位置，以及管理“良好”网络基础设施的插拔规则的假设。控制器周期性地发送网络数据包，如果它们遍历网络中的特定连接元素，它们将被标记。可以确定网络分组的来源和路径。决策是基于配置服务器接收到的数据包的多数功能。如果不能作出决定，则可以检测布线结构中的错误。

2. 发明授权

US07089450B2 Apparatus and method for process recovery in an embedded processor system 失效
标题翻译：嵌入式处理器系统中的处理恢复装置和方法
公开(公告)号：US07089450B2
公开(公告)日：2006-08-08
申请号：US10422688
申请日：2003-04-24
申请人： Gary D. Anderson , Andreas Arnez , Joshua W. Boyer , Gerald G. Kreissig , Paul Edward Movall , Ward R. Nelson
发明人： Gary D. Anderson , Andreas Arnez , Joshua W. Boyer , Gerald G. Kreissig , Paul Edward Movall , Ward R. Nelson
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0715
摘要： A recovery process for embedded processors monitors other processes in the system. Each process may specify a recovery policy residing in nonvolatile electronic memory that preferably includes a recovery count, a recovery time, and a recovery action. If a process terminates unexpectedly, the recovery process determines whether the process had a corresponding recovery policy. If not, the recovery process does not recover the process. If the process has a corresponding recovery policy, the recovery process determines whether it can recover the process by examining the recovery count and recovery time specified in the recovery policy. If the process can be recovered, the recovery process performs the recovery action specified in the corresponding recovery policy. If the process cannot be recovered, the recovery process resets the system. In this manner, a single process may be recovered by the recovery process without user intervention and without affecting other processes running on the system, and without performing a reset of the entire system.
摘要翻译：嵌入式处理器的恢复过程监视系统中的其他进程。每个进程可以指定驻留在非易失性电子存储器中的恢复策略，其优选地包括恢复计数，恢复时间和恢复动作。如果进程意外终止，则恢复进程将确定进程是否具有相应的恢复策略。如果没有，则恢复过程不会恢复该过程。如果进程具有相应的恢复策略，则恢复进程将通过检查恢复策略中指定的恢复计数和恢复时间来确定是否可以恢复进程。如果可以恢复进程，则恢复进程将执行相应恢复策略中指定的恢复操作。如果进程无法恢复，恢复过程将重置系统。以这种方式，可以通过恢复过程来恢复单个进程，而无需用户干预，而不影响在系统上运行的其他进程，并且不执行整个系统的重置。

3. 发明授权

US07409539B2 System design and code update strategy to implement a self-healing, self-verifying system 失效
标题翻译：系统设计和代码更新策略，实现自我修复，自我验证系统
公开(公告)号：US07409539B2
公开(公告)日：2008-08-05
申请号：US11197568
申请日：2005-08-04
申请人： Andreas Arnez , Joern Engel , Frank Haverkamp
发明人： Andreas Arnez , Joern Engel , Frank Haverkamp
IPC分类号： G06F9/445 , G06F15/177
CPC分类号： G06F11/1417 , G06F11/1658 , G06F11/1666
摘要： The present invention relates to boot code processing of a computer system, and in particular to a method and respective system for managing boot code of a computer system, wherein the system comprises at least a first and a redundant second boot memory portion, and wherein the system is booted from one of said portions, referred to as the active booting portion, the other boot portion being in a stand-by mode and being referred to as inactive boot portion. In order to increase the robustness of a computer system against failures due to errors in boot code updates it is proposed to perform the steps of: a) booting the system from said first one (default) of said two boot memory portions; b) verifying the correctness of the boot procedure, if not correct; c1) re-booting from said second boot portion, and c2) replicating the boot code from the active boot memory portion to the non-active boot memory portion, if correct; d) replicating the boot code from the active boot memory portion to the non-active boot memory portion; e) run normal operation mode.
摘要翻译：本发明涉及计算机系统的引导代码处理，特别涉及用于管理计算机系统的引导代码的方法和相应的系统，其中该系统至少包括第一和第二引导存储器部分，并且其中，系统从被称为主动引导部分的所述部分之一引导，另一个引导部分处于待机模式，并被称为非活动引导部分。为了增加计算机系统对由于引导代码更新中的错误而引起的故障的鲁棒性，建议执行以下步骤：a）从所述两个引导存储器部分的第一个（默认）引导系统; b）验证引导程序的正确性，如果不正确; c1）从所述第二引导部分重新引导，以及c2）如果正确，将所述引导代码从所述主动引导存储器部分复制到所述非活动引导存储器部分; d）将所述启动代码从所述主动引导存储器部分复制到所述非活动引导存储器部分; e）运行正常运行模式。

4. 发明申请

US20070033387A1 System design and code update strategy to implement a self-healing, self-verifying system 失效
标题翻译：系统设计和代码更新策略，实现自我修复，自我验证系统
公开(公告)号：US20070033387A1
公开(公告)日：2007-02-08
申请号：US11197568
申请日：2005-08-04
申请人： Andreas Arnez , Joern Engel , Frank Haverkamp
发明人： Andreas Arnez , Joern Engel , Frank Haverkamp
IPC分类号： G06F9/00
CPC分类号： G06F11/1417 , G06F11/1658 , G06F11/1666
摘要： The present invention relates to boot code processing of a computer system, and in particular to a method and respective system for managing boot code of a computer system, wherein the system comprises at least a first and a redundant second boot memory portion, and wherein the system is booted from one of said portions, referred to as the active booting portion, the other boot portion being in a stand-by mode and being referred to as inactive boot portion. In order to increase the robustness of a computer system against failures due to errors in boot code updates it is proposed to perform the steps of: a) booting the system from said first one (default) of said two boot memory portions; b) verifying the correctness of the boot procedure, if not correct; c1) re-booting from said second boot portion, and c2) replicating the boot code from the active boot memory portion to the non-active boot memory portion, if correct; d) replicating the boot code from the active boot memory portion to the non-active boot memory portion; e) run normal operation mode.
摘要翻译：本发明涉及计算机系统的引导代码处理，特别涉及用于管理计算机系统的引导代码的方法和相应的系统，其中该系统至少包括第一和第二引导存储器部分，并且其中，系统从被称为主动引导部分的所述部分之一引导，另一个引导部分处于待机模式，并被称为非活动引导部分。为了提高计算机系统由于引导代码更新中的错误导致的故障的鲁棒性，建议执行以下步骤：a）从所述两个引导存储器部分的第一个（默认）引导系统; b）验证引导程序的正确性，如果不正确; c1）从所述第二引导部分重新引导，以及c2）如果正确，将所述引导代码从所述主动引导存储器部分复制到所述非活动引导存储器部分; d）将所述启动代码从所述主动引导存储器部分复制到所述非活动引导存储器部分; e）运行正常运行模式。

5. 发明授权

US07376887B2 Method for fast ECC memory testing by software including ECC check byte 有权
标题翻译：通过软件快速ECC内存测试的方法，包括ECC校验字节
公开(公告)号：US07376887B2
公开(公告)日：2008-05-20
申请号：US11013678
申请日：2004-12-16
申请人： Andreas Arnez , Joerg-Stephan Vogt
发明人： Andreas Arnez , Joerg-Stephan Vogt
IPC分类号： G11C29/00
CPC分类号： H03M13/096 , G11C29/42
摘要： The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors when the ECC-bits cannot be accessed directly for a read or write process. The system and process employs the selection of data patterns that produce check bits that are all ones to ferret out errors in the ECC circuitry.
摘要翻译：本发明涉及计算机硬件存储器逻辑的架构和操作，特别涉及用于验证硬件存储器逻辑的方法和相应系统，其中纠错码（ECC）用于校正单位或多位错误当ECC位不能直接访问读或写进程时。系统和过程采用产生校验位的数据模式的选择，这些校验位都是ECC电路中的错误。

6. 发明申请

US20050149824A1 Method for fast ECC memory testing by software including ECC check byte 有权
标题翻译：通过软件快速ECC内存测试的方法，包括ECC校验字节
公开(公告)号：US20050149824A1
公开(公告)日：2005-07-07
申请号：US11013678
申请日：2004-12-16
申请人： Andreas Arnez , Joerg-Stephan Vogt
发明人： Andreas Arnez , Joerg-Stephan Vogt
IPC分类号： G11C29/00 , G11C29/42 , H03M13/00 , H03M13/09
CPC分类号： H03M13/096 , G11C29/42
摘要： The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors, and wherein the ECC-bits cannot be accessed directly for a read or write process. In order to improve ECC testing, an ECC verification is proposed.
摘要翻译：本发明涉及计算机硬件存储器逻辑的架构和操作，特别涉及用于验证硬件存储器逻辑的方法和相应系统，其中纠错码（ECC）用于校正单位或多位错误，并且其中ECC位不能被直接访问用于读或写处理。为了改进ECC测试，提出了ECC验证。

7. 发明授权

US07809810B2 Network and method for the configuration thereof 有权
标题翻译：网络及其配置方法
公开(公告)号：US07809810B2
公开(公告)日：2010-10-05
申请号：US12190960
申请日：2008-08-13
申请人： Frank Scholz , Dirk Bolte , Friedrich Michael Welter , Martin Kuenzel , Friedemann Baitinger , Andreas Bieswanger , Juergen Saalmueller , Andreas Arnez
发明人： Frank Scholz , Dirk Bolte , Friedrich Michael Welter , Martin Kuenzel , Friedemann Baitinger , Andreas Bieswanger , Juergen Saalmueller , Andreas Arnez
IPC分类号： G06F15/16
CPC分类号： H04L41/26 , H04L41/0803 , H04L41/12
摘要： A method and corresponding apparatus is provided for determining the location of a configuration server being connected to a totally symmetric network infrastructure that does not exhibit any symmetry breakers on network level. The configuration server reaches a decision to determine its network-wide unique configuration in order to be able to serve controllers. This decision depends on the plug position of the configuration server under consideration and the assumption of plugging rules governing a “good” network infrastructure. The controllers periodically send network packets that will be marked if they traverse specific connection elements in the network. The origin and the path of a network packet can be determined. The decision making is based on a majority function based on the packets received by the configuration server. If a decision cannot be made, then errors in the cabling structure can be detected.
摘要翻译：提供了一种方法和相应的装置，用于确定连接到在网络级别上不呈现任何对称断路器的完全对称网络基础设施的配置服务器的位置。配置服务器决定确定其全网络唯一配置，以便能够为控制器提供服务。该决定取决于正在考虑的配置服务器的插头位置，以及管理“良好”网络基础设施的插拔规则的假设。控制器周期性地发送网络数据包，如果它们遍历网络中的特定连接元素，它们将被标记。可以确定网络分组的来源和路径。决策是基于基于配置服务器接收的数据包的多数功能。如果不能作出决定，则可以检测布线结构中的错误。

8. 发明申请

US20080104614A1 METHOD AND APPARATUS FOR MULTIPLE SLAVES TO RECEIVE DATA FROM MULTIPLE MASTERS IN A DATA PROCESSING SYSTEM 审中-公开
标题翻译：用于在数据处理系统中从多个主体接收数据的多个SLAVES的方法和装置
公开(公告)号：US20080104614A1
公开(公告)日：2008-05-01
申请号：US11970250
申请日：2008-01-07
申请人： ANDREAS ARNEZ , Douglas Boecker , Stephan Broyles , Hemlata Nellimarla
发明人： ANDREAS ARNEZ , Douglas Boecker , Stephan Broyles , Hemlata Nellimarla
IPC分类号： G06F13/00 , G06F13/10 , G06F13/14 , G06F13/36
CPC分类号： G06F9/544 , G06F9/545
摘要： A method, apparatus, and computer instructions for managing requests for data by processes in a data processing system. Requests for data from the processes in slave mode are tracked. Data received by a device driver is stored, wherein the data may originate from multiple masters. The data is sent to the processes, wherein the device driver is not required to handle requests for the processes in slave mode.
摘要翻译：一种用于通过数据处理系统中的进程来管理数据请求的方法，装置和计算机指令。跟踪从从模式进程的数据请求。存储由设备驱动器接收的数据，其中数据可以源自多个主器件。将数据发送到进程，其中不需要设备驱动程序来处理从属模式下进程的请求。

9. 发明授权

US08145961B2 Fast ECC memory testing by software including ECC check byte 有权
标题翻译：通过软件快速ECC内存测试，包括ECC校验字节
公开(公告)号：US08145961B2
公开(公告)日：2012-03-27
申请号：US12122753
申请日：2008-05-19
申请人： Andreas Arnez , Joerg-Stephan Vogt
发明人： Andreas Arnez , Joerg-Stephan Vogt
IPC分类号： G01R31/28
CPC分类号： H03M13/096 , G11C29/42
摘要： The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors when the ECC-bits cannot be accessed directly for a read or write process. The system and process employs the selection of data patterns that produce check bits that are all ones to ferret out errors in the ECC circuitry.
摘要翻译：本发明涉及计算机硬件存储器逻辑的架构和操作，特别涉及用于验证硬件存储器逻辑的方法和相应系统，其中纠错码（ECC）用于校正单位或多位错误当ECC位不能直接访问读或写进程时。系统和过程采用产生校验位的数据模式的选择，这些校验位都是ECC电路中的错误。

10. 发明申请

US20080229176A1 METHOD FOR FAST ECC MEMORY TESTING BY SOFTWARE INCLUDING ECC CHECK BYTE 有权
标题翻译：用于通过软件进行快速ECC记忆测试的方法，包括ECC检查字节
公开(公告)号：US20080229176A1
公开(公告)日：2008-09-18
申请号：US12122753
申请日：2008-05-19
申请人： Andreas Arnez , Joerg-Stephan Vogt
发明人： Andreas Arnez , Joerg-Stephan Vogt
IPC分类号： G06F11/07 , G11C29/00 , G06F17/10
CPC分类号： H03M13/096 , G11C29/42
摘要： The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors when the ECC-bits cannot be accessed directly for a read or write process. The system and process employs the selection of data patterns that produce check bits that are all ones to ferret out errors in the ECC circuitry.
摘要翻译：本发明涉及计算机硬件存储器逻辑的架构和操作，特别涉及用于验证硬件存储器逻辑的方法和相应系统，其中纠错码（ECC）用于校正单位或多位错误当ECC位不能直接访问读或写进程时。系统和过程采用产生校验位的数据模式的选择，这些校验位都是ECC电路中的错误。

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