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1. 发明申请

US20060095629A1 System, method and storage medium for providing a service interface to a memory system 有权
标题翻译：用于向存储器系统提供服务接口的系统，方法和存储介质
公开(公告)号：US20060095629A1
公开(公告)日：2006-05-04
申请号：US10977921
申请日：2004-10-29
申请人： Kevin Gower , Warren Maule , Juergen Saalmueller
发明人： Kevin Gower , Warren Maule , Juergen Saalmueller
IPC分类号： G06F13/14
CPC分类号： G06F13/4243
摘要： A cascaded interconnect system for providing a service interface to a memory system. The cascaded interconnect system includes a master service interface module, a service interface bus, and one or more slave service interface modules. The master service interface module and the slave interface modules are cascade interconnected via the service interface bus. Each slave service interface module is in communication with a corresponding memory module for providing a service to the memory module.
摘要翻译：用于向存储器系统提供服务接口的级联互连系统。级联互联系统包括主服务接口模块，业务接口总线以及一个或多个从业务接口模块。主服务接口模块和从接口模块通过业务接口总线级联互联。每个从业务接口模块与相应的存储器模块通信，用于向存储器模块提供服务。

2. 发明授权

US08056037B2 Method for validating logical function and timing behavior of a digital circuit decision 有权
标题翻译：用于验证数字电路决策的逻辑功能和时序特性的方法
公开(公告)号：US08056037B2
公开(公告)日：2011-11-08
申请号：US12233169
申请日：2008-09-18
申请人： Juergen Koehl , Walter Pietschmann , Juergen Saalmueller , Norbert Schumacher , Volker Urban , Joerg Walter
发明人： Juergen Koehl , Walter Pietschmann , Juergen Saalmueller , Norbert Schumacher , Volker Urban , Joerg Walter
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： The present invention relates to a method for validating the correct logical function and timing behavior of a digital circuit design within a cycle-based verification environment. The method comprises the steps of providing a VHDL description of the digital circuit design, performing a logic synthesis, wherein the VHDL description is turned into a design implementation in terms of logic gates, and creating a netlist including the elements of the digital circuit design and the connections between said elements. The method comprises the further steps of providing a transformation script with at least one transparent storage element, wherein said transparent storage element represents a path delay within the digital circuit design, creating a new netlist with the at least one transparent storage elements, running a verification, and checking if the new netlist is clean from a logical and timing point of view.
摘要翻译：本发明涉及一种在基于周期的验证环境中验证数字电路设计的正确逻辑功能和定时特性的方法。该方法包括以下步骤：提供数字电路设计的VHDL描述，执行逻辑合成，其中将VHDL描述转变为逻辑门的设计实现，以及创建包括数字电路设计的元件的网表，以及所述元件之间的连接。该方法包括以下步骤：向至少一个透明存储元件提供变换脚本，其中所述透明存储元件表示所述数字电路设计内的路径延迟，用所述至少一个透明存储元件创建新的网表，运行验证，并从逻辑和定时的角度检查新的网表是否干净。

3. 发明申请

US20090083684A1 Method for Violating the Logical Function and Timing Behavior of a Digital Circuit Decision 有权
标题翻译：违反数字电路决策的逻辑功能和定时行为的方法
公开(公告)号：US20090083684A1
公开(公告)日：2009-03-26
申请号：US12233169
申请日：2008-09-18
申请人： Juergen Koehl , Walter Pietschmann , Juergen Saalmueller , Norbert Schumacher , Volker Urban , Joerg Walter
发明人： Juergen Koehl , Walter Pietschmann , Juergen Saalmueller , Norbert Schumacher , Volker Urban , Joerg Walter
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： The present invention relates to a method for validating the correct logical function and timing behavior of a digital circuit design within a cycle-based verification environment. Said method comprises the steps of providing (10) a VHDL description of the digital circuit design, performing (12) a logic synthesis, wherein the VHDL description is turned into a design implementation in terms of logic gates, and creating (14) a netlist including the elements of the digital circuit design and the connections between said elements. Said method comprises the further steps of providing (28) a transformation script with at least one transparent storage element (40; 54), wherein said transparent storage element (40; 54) represents a path delay within the digital circuit design, creating (30) a new netlist with the at least one transparent storage elements (40; 54), running (20) a verification, and checking, if the new netlist is clean from a logical and timing point of view.
摘要翻译：本发明涉及一种在基于周期的验证环境中验证数字电路设计的正确逻辑功能和定时特性的方法。所述方法包括以下步骤：提供（10）数字电路设计的VHDL描述，执行（12）逻辑合成，其中VHDL描述在逻辑门方面变成设计实现，并且创建（14）网表包括数字电路设计的元件和所述元件之间的连接。所述方法包括以下步骤：提供具有至少一个透明存储元件（40; 54）的转换脚本（28），其中所述透明存储元件（40; 54）表示数字电路设计内的路径延迟，创建（30 ）具有至少一个透明存储元件（40; 54）的新网表，运行（20）验证，并且如果所述新网表从逻辑和定时观点清洁，则检查。

4. 发明授权

US07809810B2 Network and method for the configuration thereof 有权
标题翻译：网络及其配置方法
公开(公告)号：US07809810B2
公开(公告)日：2010-10-05
申请号：US12190960
申请日：2008-08-13
申请人： Frank Scholz , Dirk Bolte , Friedrich Michael Welter , Martin Kuenzel , Friedemann Baitinger , Andreas Bieswanger , Juergen Saalmueller , Andreas Arnez
发明人： Frank Scholz , Dirk Bolte , Friedrich Michael Welter , Martin Kuenzel , Friedemann Baitinger , Andreas Bieswanger , Juergen Saalmueller , Andreas Arnez
IPC分类号： G06F15/16
CPC分类号： H04L41/26 , H04L41/0803 , H04L41/12
摘要： A method and corresponding apparatus is provided for determining the location of a configuration server being connected to a totally symmetric network infrastructure that does not exhibit any symmetry breakers on network level. The configuration server reaches a decision to determine its network-wide unique configuration in order to be able to serve controllers. This decision depends on the plug position of the configuration server under consideration and the assumption of plugging rules governing a “good” network infrastructure. The controllers periodically send network packets that will be marked if they traverse specific connection elements in the network. The origin and the path of a network packet can be determined. The decision making is based on a majority function based on the packets received by the configuration server. If a decision cannot be made, then errors in the cabling structure can be detected.
摘要翻译：提供了一种方法和相应的装置，用于确定连接到在网络级别上不呈现任何对称断路器的完全对称网络基础设施的配置服务器的位置。配置服务器决定确定其全网络唯一配置，以便能够为控制器提供服务。该决定取决于正在考虑的配置服务器的插头位置，以及管理“良好”网络基础设施的插拔规则的假设。控制器周期性地发送网络数据包，如果它们遍历网络中的特定连接元素，它们将被标记。可以确定网络分组的来源和路径。决策是基于基于配置服务器接收的数据包的多数功能。如果不能作出决定，则可以检测布线结构中的错误。

5. 发明申请

US20080313374A1 SERVICE INTERFACE TO A MEMORY SYSTEM 失效
标题翻译：与记忆系统的服务接口
公开(公告)号：US20080313374A1
公开(公告)日：2008-12-18
申请号：US12198201
申请日：2008-08-26
申请人： Kevin C. Gower , Warren E. Maule , Juergen Saalmueller
发明人： Kevin C. Gower , Warren E. Maule , Juergen Saalmueller
IPC分类号： G06F13/40
CPC分类号： G06F13/4243
摘要： A cascaded interconnect system for providing a service interface to a memory system. The cascaded interconnect system includes a master service interface module, a service interface bus, and one or more slave service interface modules. The master service interface module and the slave interface modules are cascade interconnected via the service interface bus. Each slave service interface module is in communication with a corresponding memory module for providing a service to the memory module.
摘要翻译：用于向存储器系统提供服务接口的级联互连系统。级联互联系统包括主服务接口模块，业务接口总线以及一个或多个从业务接口模块。主服务接口模块和从接口模块通过业务接口总线级联互联。每个从业务接口模块与相应的存储器模块通信，用于向存储器模块提供服务。

6. 发明申请

US20080065874A1 SYSTEM AND METHOD FOR DYNAMIC DETERMINATION OF SYSTEM TOPOLOGY IN A MULTIPLE BUILDING BLOCK SERVER SYSTEM 审中-公开
标题翻译：用于动态确定多个建筑块服务器系统中的系统拓扑的系统和方法
公开(公告)号：US20080065874A1
公开(公告)日：2008-03-13
申请号：US11470700
申请日：2006-09-07
申请人： Andrew Geissler , Andreas Bieswanger , Gary Anderson , Herwig Elfering , Hye-Young McCreary , Juergen Saalmueller , Kanisha Patel
发明人： Andrew Geissler , Andreas Bieswanger , Gary Anderson , Herwig Elfering , Hye-Young McCreary , Juergen Saalmueller , Kanisha Patel
IPC分类号： G06F15/177
CPC分类号： G06F15/177
摘要： A system and method for an initial boot of a system before adding or removing drawers to a system without requiring an n-level cable. Standby power is applied after all cables have been connected to the system. All available expansion ports for an SMP cable are searched. A unique ID is sent over and received by all plugged SMP cables. A list of each controller and its connected controllers is created, and a master controller is assigned. A plugging table of each controller is sent to the master controller. The master controller compares all received plugging tables to plugging rules. Errors are reported in cable plugging errors and system configuration is reported to platform management service.
摘要翻译：一种系统和方法，用于在向系统添加或删除抽屉之前对系统进行初始启动，而不需要n级电缆。所有电缆都连接到系统后，应用待机电源。搜索所有可用的SMP电缆扩展端口。所有插入的SMP电缆都发送并接收唯一的ID。创建每个控制器及其连接的控制器的列表，并分配主控制器。每个控制器的插入表发送到主控制器。主控制器将所有接收的插件表与插入规则进行比较。电缆堵塞错误报告错误，系统配置报告给平台管理服务。

7. 发明授权

US06625176B1 Method and apparatus for adjustment of time delays in synchronous clocked bus systems 失效
标题翻译：用于调整同步时钟总线系统中的时间延迟的方法和装置
公开(公告)号：US06625176B1
公开(公告)日：2003-09-23
申请号：US09301821
申请日：1999-04-29
申请人： Eberhard Amann , Helga Hermann , Juergen Saalmueller
发明人： Eberhard Amann , Helga Hermann , Juergen Saalmueller
IPC分类号： B41M524
CPC分类号： H04L25/14 , H04L69/14 , H04Q2213/13036 , H04Q2213/13103 , H04Q2213/13106 , H04Q2213/13208 , H04Q2213/13209 , H04Q2213/13213 , H04Q2213/13216 , H04Q2213/1329 , H04Q2213/1331 , H04Q2213/1332 , H04Q2213/1336 , H04Q2213/13362 , H04Q2213/13389
摘要： A method is provided to adjust time delays and sequence ordering of data channels in synchronous clocked bus systems. In particular, the invention relates to a method to re-synchronize data in respective channels which have a relative delay to each other caused by different path lengths, etc., on the way from sender to receiver. Still more specifically, the invention relates to an apparatus used to eliminate those delays in order to make data usable again on the receiver side. The method can be carried out using standard microprocessors without the need for special hardware implementations. Thus the use of costly and performance intensive ASICs and signal processors can be avoided.
摘要翻译：提供了一种方法来调整同步时钟总线系统中数据通道的时间延迟和序列排序。具体地，本发明涉及一种在从发送方到接收方的方式上，在各个信道中重新同步数据的方法，该方法具有由不同的路径长度等引起的彼此之间的相对延迟。更具体地，本发明涉及一种用于消除那些延迟以便使数据在接收机侧再次可用的装置。该方法可以使用标准微处理器进行，而不需要特殊的硬件实现。因此，可以避免使用昂贵且性能强大的ASIC和信号处理器。

8. 发明授权

US07610423B2 Service interface to a memory system 失效
标题翻译：与内存系统的服务接口
公开(公告)号：US07610423B2
公开(公告)日：2009-10-27
申请号：US12198201
申请日：2008-08-26
申请人： Kevin C. Gower , Warren E. Maule , Juergen Saalmueller
发明人： Kevin C. Gower , Warren E. Maule , Juergen Saalmueller
IPC分类号： G06F13/00
CPC分类号： G06F13/4243
摘要： A cascaded interconnect system for providing a service interface to a memory system. The cascaded interconnect system includes a master service interface module, a service interface bus, and one or more slave service interface modules. The master service interface module and the slave interface modules are cascade interconnected via the service interface bus. Each slave service interface module is in communication with a corresponding memory module for providing a service to the memory module.
摘要翻译：用于向存储器系统提供服务接口的级联互连系统。级联互联系统包括主服务接口模块，业务接口总线以及一个或多个从业务接口模块。主服务接口模块和从接口模块通过业务接口总线级联互联。每个从业务接口模块与相应的存储器模块通信，用于向存储器模块提供服务。

9. 发明申请

US20090063666A1 Network and Method for the Configuration Thereof 有权
标题翻译：网络及其配置方法
公开(公告)号：US20090063666A1
公开(公告)日：2009-03-05
申请号：US12190960
申请日：2008-08-13
申请人： Frank Scholz , Dirk Bolte , Friedrich Michael Welter , Martin Kuenzel , Friedemann Baitinger , Andreas Bieswanger , Juergen Saalmueller , Andreas Arnez
发明人： Frank Scholz , Dirk Bolte , Friedrich Michael Welter , Martin Kuenzel , Friedemann Baitinger , Andreas Bieswanger , Juergen Saalmueller , Andreas Arnez
IPC分类号： G06F15/177
CPC分类号： H04L41/26 , H04L41/0803 , H04L41/12
摘要： A method and corresponding apparatus is provided for determining the location of a configuration server being connected to a totally symmetric network infrastructure that does not exhibit any symmetry breakers on network level. The configuration server reaches a decision to determine its network-wide unique configuration in order to be able to serve controllers. This decision depends on the plug position of the configuration server under consideration and the assumption of plugging rules governing a “good” network infrastructure. The controllers periodically send network packets that will be marked if they traverse specific connection elements in the network. The origin and the path of a network packet can be determined. The decision making is based on a majority function based on the packets received by the configuration server. If a decision cannot be made, then errors in the cabling structure can be detected.
摘要翻译：提供了一种方法和相应的装置，用于确定连接到在网络级别上不呈现任何对称断路器的完全对称网络基础设施的配置服务器的位置。配置服务器决定确定其全网络唯一配置，以便能够为控制器提供服务。该决定取决于正在考虑的配置服务器的插头位置，以及管理“良好”网络基础设施的插拔规则的假设。控制器周期性地发送网络数据包，如果它们遍历网络中的特定连接元素，它们将被标记。可以确定网络分组的来源和路径。决策是基于配置服务器接收到的数据包的多数功能。如果不能作出决定，则可以检测布线结构中的错误。

10. 发明授权

US07441060B2 System, method and storage medium for providing a service interface to a memory system 有权
标题翻译：用于向存储器系统提供服务接口的系统，方法和存储介质
公开(公告)号：US07441060B2
公开(公告)日：2008-10-21
申请号：US10977921
申请日：2004-10-29
申请人： Kevin C. Gower , Warren E. Maule , Juergen Saalmueller
发明人： Kevin C. Gower , Warren E. Maule , Juergen Saalmueller
IPC分类号： G06F13/00
CPC分类号： G06F13/4243
摘要： A cascaded interconnect system for providing a service interface to a memory system. The cascaded interconnect system includes a master service interface module, a service interface bus, and one or more slave service interface modules. The master service interface module and the slave interface modules are cascade interconnected via the service interface bus. Each slave service interface module is in communication with a corresponding memory module for providing a service to the memory module.
摘要翻译：用于向存储器系统提供服务接口的级联互连系统。级联互联系统包括主服务接口模块，业务接口总线以及一个或多个从业务接口模块。主服务接口模块和从接口模块通过业务接口总线级联互联。每个从业务接口模块与相应的存储器模块通信，用于向存储器模块提供服务。

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