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1. 发明授权

US07089414B2 Method and apparatus for updating a microcode image in a memory 失效
标题翻译：用于更新存储器中的微码图像的方法和装置
公开(公告)号：US07089414B2
公开(公告)日：2006-08-08
申请号：US10411414
申请日：2003-04-10
申请人： John Steven Langford , Michael Youhour Lim , Paul Edward Movall , Thomas Joseph Warne
发明人： John Steven Langford , Michael Youhour Lim , Paul Edward Movall , Thomas Joseph Warne
IPC分类号： G06F9/00
CPC分类号： H04L67/34 , G06F11/0766 , H04L69/329
摘要： A method, apparatus, and computer instructions for determining validity of and updating a microcode image. Responsive to initiation of an update process, a first validity indicator is checked to determine whether a first microcode image in the memory is valid. In response to the first microcode image being valid, a second validity indicator is set indies, to indicate that a second microcode image is invalid, and the update process is allowed to update the second microcode image to form an updated microcode image. A determination is made as to whether the updated microcode image is valid. The second validity indicator is set to indicate that the updated microcode is valid if the updated image is valid. The second validity indicator is checked during booting of a data processing system. If the second validity indicator is valid, the updated microcode will be loaded.
摘要翻译：一种用于确定微码图像的有效性和更新的方法，装置和计算机指令。响应于启动更新处理，检查第一有效性指示符以确定存储器中的第一微代码图像是否有效。响应于第一微码图像有效，第二有效性指示符被设置为指示第二微码图像无效，并且允许更新处理更新第二微码图像以形成更新的微码图像。确定更新的微码图像是否有效。第二有效性指示符被设置为指示更新的微码在更新的图像有效时是有效的。在数据处理系统引导期间检查第二个有效性指示符。如果第二个有效性指示符有效，则更新的微代码将被加载。

2. 发明授权

US6085277A Interrupt and message batching apparatus and method 失效
标题翻译：中断和消息批处理设备和方法
公开(公告)号：US6085277A
公开(公告)日：2000-07-04
申请号：US950755
申请日：1997-10-15
申请人： Gregory Michael Nordstrom , Shawn Michael Lambeth , Paul Edward Movall , Daniel Frank Moertl , Charles Scott Graham , William Joseph Armstrong , Thomas Rembert Sand
发明人： Gregory Michael Nordstrom , Shawn Michael Lambeth , Paul Edward Movall , Daniel Frank Moertl , Charles Scott Graham , William Joseph Armstrong , Thomas Rembert Sand
IPC分类号： G06F9/46 , G06F13/00
CPC分类号： G06F9/546
摘要： An interrupt and message batching apparatus and method reduces the number and frequency of processor interrupts and resulting context switches by grouping I/O completion events together with a single processor interrupt in a manner that balances I/O operation latency requirements with processor utilization requirements to optimize overall computer system performance. The invention sends a message from a processor complex to an I/O adapter on an I/O bus commanding an I/O device connected to the I/O adapter to perform a function. Upon completion of the commanded function, the message processor in the I/O adapter generates a message and sends it to the processor complex on the I/O bus. The message is enqueued in the message queue of the memory, a message count is updated, and processor complex interrupt is signalled if and when the message count exceeds a message pacing count. A signalling timer may also be programmed with a fast response time value if the message has a relatively high latency or with a slow response time value if the message has a relatively low latency. The signalling timer is started when the message is enqueued and the processor complex interrupt is then signalled when the message count exceeds the message pacing count or when the signalling timer has elapsed.
摘要翻译：中断和消息批处理设备和方法通过将I / O完成事件与单个处理器中断分组，以使I / O操作等待时间要求与处理器利用率要求平衡来优化，从而减少处理器中断和结果上下文切换的数量和频率整体计算机系统性能。本发明在I / O总线上从处理器复合体向I / O适配器发送消息，命令连接到I / O适配器的I / O设备执行功能。完成命令功能后，I / O适配器中的消息处理器会生成一条消息，并将其发送到I / O总线上的处理器复合体。该消息在存储器的消息队列中排队，消息计数被更新，并且当消息计数超过消息步调计数时以及何时发送处理器复杂中断。如果消息具有相对较高的延迟，或者如果消息具有相对低的延迟，则信令定时器也可以被编程为具有快速的响应时间值。当消息排入队列时，启动信令定时器，然后当消息计数超过消息起搏计数或信令定时器过去时，信号通知处理器复杂中断。

3. 发明授权

US07254815B2 Method and apparatus for implementing distributed event management in an embedded support processor computer system 有权
标题翻译：在嵌入式支持处理器计算机系统中实现分布式事件管理的方法和装置
公开(公告)号：US07254815B2
公开(公告)日：2007-08-07
申请号：US10422659
申请日：2003-04-24
申请人： Clinton Gene Laschkewitsch , Paul Edward Movall , Ward Ray Nelson
发明人： Clinton Gene Laschkewitsch , Paul Edward Movall , Ward Ray Nelson
IPC分类号： G06F9/46
CPC分类号： G06F9/542
摘要： Distributed event management in an embedded support processor computer system includes an embedded support processor having an event distribution agent used to communicate with local processes internal to the embedded support processor. A process communicates with the event distribution agent of the embedded support processor and registers for one or more events. Another process signals an event to the event distribution agent of the embedded support processor. The event distribution agent of the embedded support processor notifies each registered process of the signaled event. The event distribution agent of the embedded support processor is used to communicate with a peer event distribution agent included in a main processor of the embedded support processor computer system, and to communicate over a network with a peer event distribution agent included in an attached device, such as a personal computer.
摘要翻译：嵌入式支持处理器计算机系统中的分布式事件管理包括具有用于与嵌入式支持处理器内部的本地进程通信的事件分发代理的嵌入式支持处理器。进程与嵌入式支持处理器的事件分发代理进行通信，并为一个或多个事件注册。另一个过程将事件发送给嵌入式支持处理器的事件分发代理。嵌入式支持处理器的事件分发代理通知每个注册的进程信号事件。嵌入式支持处理器的事件分发代理用于与嵌入式支持处理器计算机系统的主处理器中包括的对等事件分发代理进行通信，并且通过网络与包括在附加的设备中的对等事件分发代理进行通信，如个人电脑。

4. 发明授权

US5983292A Message transport mechanisms and methods 失效
标题翻译：消息传输机制和方法
公开(公告)号：US5983292A
公开(公告)日：1999-11-09
申请号：US950593
申请日：1997-10-15
申请人： Gregory Michael Nordstrom , Shawn Michael Lambeth , Paul Edward Movall , Daniel Frank Moertl , Charles Scott Graham , Thomas Rembert Sand
发明人： Gregory Michael Nordstrom , Shawn Michael Lambeth , Paul Edward Movall , Daniel Frank Moertl , Charles Scott Graham , Thomas Rembert Sand
IPC分类号： G06F13/12 , G06F13/10 , G06F13/14
CPC分类号： G06F13/126
摘要： An I/O system including a processor complex and system main memory connected to I/O adapters via I/O adapters and I/O bus. A message transport mechanism and method stores an upstream message queue and a downstream message queue in system main memory. Queue addresses are stored both in system main memory and designated registers of I/O adapters. The I/O adapters utilize the queue addresses to manage the transfer of downstream command messages and to send upstream response messages to the system main memory via direct memory access across the I/O bus.
摘要翻译：一个I / O系统，包括一个处理器复合体和通过I / O适配器和I / O总线连接到I / O适配器的系统主存储器。消息传送机制和方法将上游消息队列和下游消息队列存储在系统主存储器中。队列地址存储在系统主存储器和I / O适配器的指定寄存器中。 I / O适配器利用队列地址来管理下游命令消息的传输，并通过跨I / O总线的直接存储器访问将上行响应消息发送到系统主存储器。

5. 发明授权

US07069206B2 Method and apparatus for abstraction of physical hardware implementation to logical software drivers 失效
标题翻译：将物理硬件实现抽象到逻辑软件驱动程序的方法和装置
公开(公告)号：US07069206B2
公开(公告)日：2006-06-27
申请号：US10422687
申请日：2003-04-24
申请人： Paul Edward Movall , Shaun Allan Wetzstein
发明人： Paul Edward Movall , Shaun Allan Wetzstein
IPC分类号： G06F9/455 , G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00
CPC分类号： G06F13/102
摘要： A method and apparatus are provided for abstraction of a physical hardware implementation to logical software drivers. An operating system kernel includes a device driver layer, an enhanced I/O abstraction layer and physical hardware implementation details layer. The physical hardware implementation details layer encapsulates hardware details for the physical hardware implementation. The enhanced I/O abstraction layer abstracts the hardware details for the device driver layer and creates unique logical I/O device structures for each embedded function in the physical hardware implementation. By using the enhanced I/O abstraction layer, device drivers maintain their independence from the physical hardware implementation. Using the enhanced I/O abstraction layer also enables a single driver with one binary image to support embedded functions spread out across multiple chip implementations, and multiple instances of an embedded function on one or multiple chips.
摘要翻译：提供了一种用于将物理硬件实现抽象到逻辑软件驱动器的方法和装置。操作系统内核包括设备驱动程序层，增强型I / O抽象层和物理硬件实现细节层。物理硬件实现细节层封装了物理硬件实现的硬件细节。增强型I / O抽象层提取了设备驱动程序层的硬件细节，并为物理硬件实现中的每个嵌入式功能创建了独特的逻辑I / O设备结构。通过使用增强型I / O抽象层，设备驱动程序保持与物理硬件实现的独立性。使用增强型I / O抽象层还可以使具有一个二进制图像的单个驱动器支持跨多个芯片实现分布的嵌入式功能，以及一个或多个芯片上的嵌入式功能的多个实例。

6. 发明授权

US6023736A System for dynamically configuring I/O device adapters where a function configuration register contains ready/not ready flags corresponding to each I/O device adapter 失效
标题翻译：用于动态配置I / O设备适配器的系统，其中功能配置寄存器包含与每个I / O设备适配器对应的就绪/未就绪标志
公开(公告)号：US6023736A
公开(公告)日：2000-02-08
申请号：US995157
申请日：1997-12-19
申请人： Shawn Michael Lambeth , Charles Scott Graham , Daniel Frank Moertl , Paul Edward Movall , Gregory Michael Nordstrom
发明人： Shawn Michael Lambeth , Charles Scott Graham , Daniel Frank Moertl , Paul Edward Movall , Gregory Michael Nordstrom
IPC分类号： G06F13/10
CPC分类号： G06F13/102
摘要： An apparatus, system and method permitting dynamic configuration of I/O device adapters connected to a bus utilizes a function configuration register to store a READY/NOT READY status for each of the I/O device adapters. Upon the occurrence of a reset condition, dynamic configuration decision logic detects which I/O device adapters are connected to the bus, determines configuration parameters for each connected I/O device adapter, initializes the configuration space for each connected I/O device adapter, and then sets a corresponding flag in the function configuration register to indicate ready status. An I/O device driver interrupts a configuration process to examine the function configuration register. If ready status can be confirmed from this function configuration register within a time out period, then the configuration process may proceed; otherwise, a device error recovery process is initiated.
摘要翻译：允许动态配置连接到总线的I / O设备适配器的设备，系统和方法利用功能配置寄存器来存储每个I / O设备适配器的READY / NOT READY状态。在发生复位条件时，动态配置决策逻辑检测哪个I / O设备适配器连接到总线，确定每个连接的I / O设备适配器的配置参数，初始化每个连接的I / O设备适配器的配置空间，然后在功能配置寄存器中设置相应的标志，以指示就绪状态。 I / O设备驱动程序中断配置过程以检查功能配置寄存器。如果可以在超时期内从该功能配置寄存器确认就绪状态，则可以进行配置处理; 否则，启动设备错误恢复过程。

7. 发明授权

US06742139B1 Service processor reset/reload 失效
标题翻译：服务处理器重置/重新加载
公开(公告)号：US06742139B1
公开(公告)日：2004-05-25
申请号：US09692339
申请日：2000-10-19
申请人： Stephanie Maria Forsman , Brent William Jacobs , Kevin Gene Kehne , Paul Edward Movall
发明人： Stephanie Maria Forsman , Brent William Jacobs , Kevin Gene Kehne , Paul Edward Movall
IPC分类号： G06F1120
CPC分类号： G06F11/0724 , G06F11/0793
摘要： A method, system, and apparatus for reestablishing communications between a host and a service processor after the service processor has ceased to function correctly is provided. In one embodiment, the host exchanges heartbeat signals with the service processor. The heartbeat signals indicate that the service processor is active and functioning. In response to a failure to receive a heartbeat signal or in response to some other indication that the service processor is not performing correctly, the host causes a hard reset of the service processor. In addition, the service processor can detect a failure within itself and initiate a hard reset to itself. After the hard reset, the service processor returns to a monitoring mode without performing initial tests of the data processing system. Furthermore, the data processing system remains active and is not shut down during the hard reset of the service processor.
摘要翻译：提供了一种用于在服务处理器不能正常工作之后重新建立主机与服务处理器之间的通信的方法，系统和装置。在一个实施例中，主机与服务处理器交换心跳信号。心跳信号表示服务处理器处于活动状态并且正常运行。响应于不能接收心跳信号或响应于服务处理器不能正确执行的某些其它指示，主机引起服务处理器的硬复位。此外，服务处理器可以检测自身内的故障，并对自身进行硬复位。在硬复位之后，服务处理器返回到监视模式，而不执行数据处理系统的初始测试。此外，数据处理系统保持活动状态，并且在服务处理器的硬复位期间不被关闭。

8. 发明授权

US06542939B1 Method and apparatus for storing volumetric vital product data (VPD) in memory associated with a connector or connector board 失效
标题翻译：用于在与连接器或连接器板相关联的存储器中存储体积重要产品数据（VPD）的方法和装置
公开(公告)号：US06542939B1
公开(公告)日：2003-04-01
申请号：US09371506
申请日：1999-08-10
申请人： Thomas James Osten , Paul Edward Movall , Neil Clair Berglund , Nancy Marie Uthke-Schmucki , Patrick Allen Buckland , David Lee Dosch , Stephen Peter Mroz , David G. Lund
发明人： Thomas James Osten , Paul Edward Movall , Neil Clair Berglund , Nancy Marie Uthke-Schmucki , Patrick Allen Buckland , David Lee Dosch , Stephen Peter Mroz , David G. Lund
IPC分类号： G06F1314
CPC分类号： G11B33/125 , G06F13/409
摘要： In an electrical system having a connector board with at least one electrical connector thereon for receiving an electrical device therein, volumetric vital product parametric data is stored in memory associated with the connector board. The stored volumetric vital product parametric data can be accessed with the electrical system to check for available space for a proposed electrical device, for example. The stored data may include information about dimensional characteristics of the connector board and the at least one electrical connector. This data can be compared with corresponding data for the electrical device to determine compatibility, for example.
摘要翻译：在具有连接器板的电气系统中，其上具有用于接收电气装置的至少一个电连接器，容积重要的产品参数数据被存储在与连接器板相关联的存储器中。可以使用电气系统访问存储的体积重要产品参数数据，以检查例如所提出的电气设备的可用空间。存储的数据可以包括关于连接器板和至少一个电连接器的尺寸特性的信息。该数据可以与电气设备的相应数据进行比较，以确定兼容性。

9. 发明授权

US06233641B1 Apparatus and method of PCI routing in a bridge configuration 失效
标题翻译：在桥接配置中PCI路由的装置和方法允许独立使用总线
公开(公告)号：US06233641B1
公开(公告)日：2001-05-15
申请号：US09093441
申请日：1998-06-08
申请人： Charles Scott Graham , Shawn Michael Lambeth , Daniel Frank Moertl , Paul Edward Movall
发明人： Charles Scott Graham , Shawn Michael Lambeth , Daniel Frank Moertl , Paul Edward Movall
IPC分类号： G06F1338
CPC分类号： G06F13/4022 , G06F13/4045
摘要： A primary PCI bus and multiple secondary PCI busses of a PCI expansion card interface, are interconnected by a routing circuit. The routing circuit functions as a switched bridge between the primary PCI bus and each of the secondary PCI busses, respectively, by associating each secondary PCI bus with an address range, and forwarding a command received from the primary PCI bus to a secondary PCI bus mapped to an address range including the address of the command. Furthermore, the routing circuit forwards commands intended for the primary PCI bus from the secondary PCI busses. In addition, the routing circuit directly routes commands between the secondary PCI busses, when commands received from one secondary PCI bus are intended for another PCI bus, without use of the primary bus. As a result, traffic and latency on the primary PCI bus is reduced and efficiency is increased.
摘要翻译： PCI扩展卡接口的主PCI总线和多个辅助PCI总线通过路由电路互连。路由电路通过将每个辅助PCI总线与地址范围相关联并将从主PCI总线接收的命令转发到辅助PCI总线映射，分别用作主PCI总线和每个辅助PCI总线之间的交换桥到包括命令地址的地址范围。此外，路由电路从辅助PCI总线转发用于主PCI总线的命令。此外，当从一个辅助PCI总线接收的命令用于另一个PCI总线时，路由电路直接在辅助PCI总线之间路由命令，而不使用主总线。因此，主PCI总线上的流量和延迟降低，效率提高。

10. 发明授权

US6101557A Method and system for remote function control and delegation within multifunction bus supported devices 失效
标题翻译：在多功能总线支持的设备中进行远程功能控制和授权的方法和系统
公开(公告)号：US6101557A
公开(公告)日：2000-08-08
申请号：US87637
申请日：1998-05-29
申请人： Paul Edward Movall , Charles Scott Graham , Shawn M. Lambeth , Daniel Frank Moertl
发明人： Paul Edward Movall , Charles Scott Graham , Shawn M. Lambeth , Daniel Frank Moertl
IPC分类号： G06F13/14 , G06F13/36 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4068
摘要： A method, device and system for configuring multifunction I/O device adapters connected to a bus utilizes a slot owner configuration register to identify the ownership of each function slot within the multi-function I/O device adapter. An intelligent I/O device adapter or controller within the multi-function I/O device adapter may control other I/O adapters located in other function slots through the information provided in the slot owner configuration register. Ownership of each slot is initially set, upon power up, to the host unit or processor complex. Thereafter, each intelligent I/O device adapter or controller determines the presence of adapters at other function slots to be controlled, and records this information in the slot owner configuration register.
摘要翻译：用于配置连接到总线的多功能I / O设备适配器的方法，设备和系统利用插槽所有者配置寄存器来识别多功能I / O设备适配器内的每个功能插槽的所有权。多功能I / O设备适配器中的智能I / O设备适配器或控制器可以通过插槽所有者配置寄存器中提供的信息来控制位于其他功能插槽中的其他I / O适配器。每个插槽的所有权在上电时初始设置为主机单元或处理器组合。此后，每个智能I / O设备适配器或控制器确定在要控制的其他功能插槽中存在适配器，并将该信息记录在插槽所有者配置寄存器中。

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