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1. 发明授权

US08145961B2 Fast ECC memory testing by software including ECC check byte 有权
标题翻译：通过软件快速ECC内存测试，包括ECC校验字节
公开(公告)号：US08145961B2
公开(公告)日：2012-03-27
申请号：US12122753
申请日：2008-05-19
申请人： Andreas Arnez , Joerg-Stephan Vogt
发明人： Andreas Arnez , Joerg-Stephan Vogt
IPC分类号： G01R31/28
CPC分类号： H03M13/096 , G11C29/42
摘要： The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors when the ECC-bits cannot be accessed directly for a read or write process. The system and process employs the selection of data patterns that produce check bits that are all ones to ferret out errors in the ECC circuitry.
摘要翻译：本发明涉及计算机硬件存储器逻辑的架构和操作，特别涉及用于验证硬件存储器逻辑的方法和相应系统，其中纠错码（ECC）用于校正单位或多位错误当ECC位不能直接访问读或写进程时。系统和过程采用产生校验位的数据模式的选择，这些校验位都是ECC电路中的错误。

2. 发明申请

US20080229176A1 METHOD FOR FAST ECC MEMORY TESTING BY SOFTWARE INCLUDING ECC CHECK BYTE 有权
标题翻译：用于通过软件进行快速ECC记忆测试的方法，包括ECC检查字节
公开(公告)号：US20080229176A1
公开(公告)日：2008-09-18
申请号：US12122753
申请日：2008-05-19
申请人： Andreas Arnez , Joerg-Stephan Vogt
发明人： Andreas Arnez , Joerg-Stephan Vogt
IPC分类号： G06F11/07 , G11C29/00 , G06F17/10
CPC分类号： H03M13/096 , G11C29/42
摘要： The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors when the ECC-bits cannot be accessed directly for a read or write process. The system and process employs the selection of data patterns that produce check bits that are all ones to ferret out errors in the ECC circuitry.
摘要翻译：本发明涉及计算机硬件存储器逻辑的架构和操作，特别涉及用于验证硬件存储器逻辑的方法和相应系统，其中纠错码（ECC）用于校正单位或多位错误当ECC位不能直接访问读或写进程时。系统和过程采用产生校验位的数据模式的选择，这些校验位都是ECC电路中的错误。

3. 发明申请

US20130031419A1 Collecting Debug Data in a Secure Chip Implementation 审中-公开
公开(公告)号：US20130031419A1
公开(公告)日：2013-01-31
申请号：US13192769
申请日：2011-07-28
申请人： Frank Haverkamp , Heiko Michel , Joerg-Stephan Vogt
发明人： Frank Haverkamp , Heiko Michel , Joerg-Stephan Vogt
IPC分类号： G06F11/34
CPC分类号： G06F21/74 , G06F11/3656
摘要： Mechanisms, in a processor chip, are provided for obtaining debug data from on-chip logic of the processor chip while the processor chip is in a secure mode of operation. The processor chip is placed into a secure mode of operation in which access to internal logic of the processor chip to control the internal logic of the processor chip, by mechanisms external to the processor chip, is disabled on a debug interface of the processor chip. A triggering condition of the processor chip is detected that is a trigger for initiated debug data collection from the on-chip logic. Debug data collection is performed from the on-chip logic to generate debug data. Data is output, by the processor chip to an external mechanism, on the debug interface based on the debug data.

4. 发明授权

US08166338B2 Reliable exception handling in a computer system 有权
标题翻译：计算机系统中可靠的异常处理
公开(公告)号：US08166338B2
公开(公告)日：2012-04-24
申请号：US12786981
申请日：2010-05-25
申请人： Thomas Huth , Jan Kunigk , Joerg-Stephan Vogt
发明人： Thomas Huth , Jan Kunigk , Joerg-Stephan Vogt
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F9/3861 , G06F11/073
摘要： A method provides exception handling for a computer system. As an error in the computer system's hardware is detected, an exception vector pertaining to the hardware error is determined, and execution flow is transferred to a dispatcher that corresponds/pertains to the exception vector. A specific instance of a plurality of instances of a main exception handler is selected, and the specific instance of the main exception handler is executed. The actual exception handler thus contains two distinct parts, a dispatcher, which is unique and preferably resides in a safe memory region, and a main exception handler, multiple copies of which reside in an unsafe memory region.
摘要翻译：一种方法为计算机系统提供异常处理。由于检测到计算机系统硬件中的错误，因此确定了与硬件错误有关的异常向量，并将执行流传送到与异常向量相对应的调度器。选择主异常处理程序的多个实例的特定实例，并执行主异常处理程序的特定实例。因此，实际的异常处理程序包含两个不同的部分，一个调度程序，它是唯一的，最好位于一个安全的内存区域，一个主异常处理程序，它们的多个副本位于一个不安全的内存区域。

5. 发明申请

US20100313061A1 METHOD AND SYSTEM FOR RELIABLE EXCEPTION HANDLING IN A COMPUTER SYSTEM 有权
标题翻译：计算机系统中可靠的例外处理方法与系统
公开(公告)号：US20100313061A1
公开(公告)日：2010-12-09
申请号：US12786981
申请日：2010-05-25
申请人： Thomas Huth , Jan Kunigk , Joerg-Stephan Vogt
发明人： Thomas Huth , Jan Kunigk , Joerg-Stephan Vogt
IPC分类号： G06F11/07 , G06F12/06 , G06F12/02 , G06F12/08
CPC分类号： G06F11/0793 , G06F9/3861 , G06F11/073
摘要： A method provides exception handling for a computer system. As an error in the computer system's hardware is detected, an exception vector pertaining to the hardware error is determined, and execution flow is transferred to a dispatcher that corresponds/pertains to the exception vector. A specific instance of a plurality of instances of a main exception handler is selected, and the specific instance of the main exception handler is executed. The actual exception handler thus contains two distinct parts, a dispatcher, which is unique and preferably resides in a safe memory region, and a main exception handler, multiple copies of which reside in an unsafe memory region.
摘要翻译：一种方法为计算机系统提供异常处理。由于检测到计算机系统硬件中的错误，因此确定了与硬件错误有关的异常向量，并将执行流传送到与异常向量相对应的调度器。选择主异常处理程序的多个实例的特定实例，并执行主异常处理程序的特定实例。因此，实际的异常处理程序包含两个不同的部分，一个调度程序，它是唯一的，最好位于一个安全的内存区域，一个主异常处理程序，它们的多个副本位于一个不安全的内存区域。

6. 发明授权

US07376887B2 Method for fast ECC memory testing by software including ECC check byte 有权
标题翻译：通过软件快速ECC内存测试的方法，包括ECC校验字节
公开(公告)号：US07376887B2
公开(公告)日：2008-05-20
申请号：US11013678
申请日：2004-12-16
申请人： Andreas Arnez , Joerg-Stephan Vogt
发明人： Andreas Arnez , Joerg-Stephan Vogt
IPC分类号： G11C29/00
CPC分类号： H03M13/096 , G11C29/42
摘要： The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors when the ECC-bits cannot be accessed directly for a read or write process. The system and process employs the selection of data patterns that produce check bits that are all ones to ferret out errors in the ECC circuitry.
摘要翻译：本发明涉及计算机硬件存储器逻辑的架构和操作，特别涉及用于验证硬件存储器逻辑的方法和相应系统，其中纠错码（ECC）用于校正单位或多位错误当ECC位不能直接访问读或写进程时。系统和过程采用产生校验位的数据模式的选择，这些校验位都是ECC电路中的错误。

7. 发明申请

US20050149824A1 Method for fast ECC memory testing by software including ECC check byte 有权
标题翻译：通过软件快速ECC内存测试的方法，包括ECC校验字节
公开(公告)号：US20050149824A1
公开(公告)日：2005-07-07
申请号：US11013678
申请日：2004-12-16
申请人： Andreas Arnez , Joerg-Stephan Vogt
发明人： Andreas Arnez , Joerg-Stephan Vogt
IPC分类号： G11C29/00 , G11C29/42 , H03M13/00 , H03M13/09
CPC分类号： H03M13/096 , G11C29/42
摘要： The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors, and wherein the ECC-bits cannot be accessed directly for a read or write process. In order to improve ECC testing, an ECC verification is proposed.
摘要翻译：本发明涉及计算机硬件存储器逻辑的架构和操作，特别涉及用于验证硬件存储器逻辑的方法和相应系统，其中纠错码（ECC）用于校正单位或多位错误，并且其中ECC位不能被直接访问用于读或写处理。为了改进ECC测试，提出了ECC验证。

8. 发明授权

US08843785B2 Collecting debug data in a secure chip implementation 有权
标题翻译：在安全芯片实现中收集调试数据
公开(公告)号：US08843785B2
公开(公告)日：2014-09-23
申请号：US13494314
申请日：2012-06-12
申请人： Frank Haverkamp , Heiko Michel , Joerg-Stephan Vogt
发明人： Frank Haverkamp , Heiko Michel , Joerg-Stephan Vogt
IPC分类号： G06F11/00 , G06F11/36 , G06F21/74
CPC分类号： G06F21/74 , G06F11/3656
摘要： Mechanisms, in a processor chip, are provided for obtaining debug data from on-chip logic of the processor chip while the processor chip is in a secure mode of operation. The processor chip is placed into a secure mode of operation in which access to internal logic of the processor chip to control the internal logic of the processor chip, by mechanisms external to the processor chip, is disabled on a debug interface of the processor chip. A triggering condition of the processor chip is detected that is a trigger for initiated debug data collection from the on-chip logic. Debug data collection is performed from the on-chip logic to generate debug data. Data is output, by the processor chip to an external mechanism, on the debug interface based on the debug data.
摘要翻译：在处理器芯片中提供用于在处理器芯片处于安全操作模式时从处理器芯片的片上逻辑获得调试数据的机制。处理器芯片被放置在安全操作模式中，其中通过处理器芯片外部的机制来控制处理器芯片的内部逻辑的内部逻辑的访问在处理器芯片的调试接口上禁用。检测到处理器芯片的触发条件，该触发条件是从片上逻辑引发的调试数据收集的触发。从片上逻辑执行调试数据采集，以生成调试数据。数据由处理器芯片输出到外部机制，在调试接口上基于调试数据。

9. 发明申请

US20130031420A1 Collecting Debug Data in a Secure Chip Implementation 有权
标题翻译：在安全芯片实现中收集调试数据
公开(公告)号：US20130031420A1
公开(公告)日：2013-01-31
申请号：US13494314
申请日：2012-06-12
申请人： Frank Haverkamp , Heiko Michel , Joerg-Stephan Vogt
发明人： Frank Haverkamp , Heiko Michel , Joerg-Stephan Vogt
IPC分类号： G06F11/34
CPC分类号： G06F21/74 , G06F11/3656
摘要： Mechanisms, in a processor chip, are provided for obtaining debug data from on-chip logic of the processor chip while the processor chip is in a secure mode of operation. The processor chip is placed into a secure mode of operation in which access to internal logic of the processor chip to control the internal logic of the processor chip, by mechanisms external to the processor chip, is disabled on a debug interface of the processor chip. A triggering condition of the processor chip is detected that is a trigger for initiated debug data collection from the on-chip logic. Debug data collection is performed from the on-chip logic to generate debug data. Data is output, by the processor chip to an external mechanism, on the debug interface based on the debug data.
摘要翻译：在处理器芯片中提供用于在处理器芯片处于安全操作模式时从处理器芯片的片上逻辑获得调试数据的机制。处理器芯片被放置在安全操作模式中，其中通过处理器芯片外部的机制来控制处理器芯片的内部逻辑的内部逻辑的访问在处理器芯片的调试接口上禁用。检测到处理器芯片的触发条件，该触发条件是从片上逻辑引发的调试数据收集的触发。从片上逻辑执行调试数据采集，以生成调试数据。数据由处理器芯片输出到外部机制，在调试接口上基于调试数据。

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