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1. 发明申请

US20070121381A1 Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general-purpose CMOS technology with thick gate oxide 失效
标题翻译：多时间可编程（MTP）PMOS浮动栅极非易失性存储器件，用于具有厚栅极氧化物的通用CMOS技术
公开(公告)号：US20070121381A1
公开(公告)日：2007-05-31
申请号：US11508771
申请日：2006-08-23
申请人： Alexander Kalnitsky , Michael Church
发明人： Alexander Kalnitsky , Michael Church
IPC分类号： G11C16/04
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.
摘要翻译：根据实施例的多时间可编程（MTP）存储单元包括浮置栅极PMOS晶体管，高电压NMOS晶体管和n阱电容器。浮置栅极PMOS晶体管包括形成存储单元的第一端子，漏极和栅极的源极。高电压NMOS晶体管包括连接到地的源极，连接到PMOS晶体管的漏极的延伸漏极和形成存储器单元的第二端子的栅极。 n阱电容器包括连接到PMOS晶体管的栅极的第一端子和形成存储器单元的第三端子的第二端子。浮置栅极PMOS晶体管可以存储逻辑状态。可以将组合的电压施加到存储单元的第一，第二和第三端子，以编程，禁止程序，读取和擦除逻辑状态。

2. 发明申请

US20110176368A1 MULTIPLE TIME PROGRAMMABLE (MTP) PMOS FLOATING GATE-BASED NON-VOLATILE MEMORY DEVICE FOR A GENERAL PURPOSE CMOS TECHNOLOGY WITH THICK GATE OXIDE 有权
标题翻译：多通道时间可编程（MTP）PMOS浮动栅基非易失性存储器件用于一般用途CMOS技术与厚栅氧化物
公开(公告)号：US20110176368A1
公开(公告)日：2011-07-21
申请号：US13077065
申请日：2011-03-31
申请人： Alexander Kalnitsky , Michael Church
发明人： Alexander Kalnitsky , Michael Church
IPC分类号： G11C16/04 , H01L29/94
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.
摘要翻译：根据实施例的多时间可编程（MTP）存储单元包括浮置栅极PMOS晶体管，高电压NMOS晶体管和n阱电容器。浮置栅极PMOS晶体管包括形成存储单元的第一端子，漏极和栅极的源极。高电压NMOS晶体管包括连接到地的源极，连接到PMOS晶体管的漏极的扩展漏极和形成存储器单元的第二端子的栅极。 n阱电容器包括连接到PMOS晶体管的栅极的第一端子和形成存储器单元的第三端子的第二端子。浮置栅极PMOS晶体管可以存储逻辑状态。可以将组合的电压施加到存储单元的第一，第二和第三端子，以编程，禁止程序，读取和擦除逻辑状态。

3. 发明申请

US20070247915A1 Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general-purpose CMOS technology with thick gate oxide 审中-公开
公开(公告)号：US20070247915A1
公开(公告)日：2007-10-25
申请号：US11498672
申请日：2006-08-02
申请人： Alexander Kalnitsky , Michael Church
发明人： Alexander Kalnitsky , Michael Church
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.

4. 发明申请

US20090207655A1 MULTIPLE TIME PROGRAMMABLE (MTP) PMOS FLOATING GATE-BASED NON-VOLATILE MEMORY DEVICE FOR A GENERAL PURPOSE CMOS TECHNOLOGY WITH THICK GATE OXIDE 有权
标题翻译：多通道时间可编程（MTP）PMOS浮动栅基非易失性存储器件用于一般用途CMOS技术与厚栅氧化物
公开(公告)号：US20090207655A1
公开(公告)日：2009-08-20
申请号：US12430007
申请日：2009-04-24
申请人： Alexander Kalnitsky , Michael Church
发明人： Alexander Kalnitsky , Michael Church
IPC分类号： G11C16/04 , G11C16/06 , G11C11/34
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.
摘要翻译：根据实施例的多时间可编程（MTP）存储单元包括浮置栅极PMOS晶体管，高电压NMOS晶体管和n阱电容器。浮置栅极PMOS晶体管包括形成存储单元的第一端子，漏极和栅极的源极。高电压NMOS晶体管包括连接到地的源极，连接到PMOS晶体管的漏极的延伸漏极和形成存储器单元的第二端子的栅极。 n阱电容器包括连接到PMOS晶体管的栅极的第一端子和形成存储器单元的第三端子的第二端子。浮置栅极PMOS晶体管可以存储逻辑状态。可以将组合的电压施加到存储单元的第一，第二和第三端子，以编程，禁止程序，读取和擦除逻辑状态。

5. 发明授权

US07542342B2 Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general-purpose CMOS technology with thick gate oxide 失效
标题翻译：多时间可编程（MTP）PMOS浮动栅极非易失性存储器件，用于具有厚栅极氧化物的通用CMOS技术
公开(公告)号：US07542342B2
公开(公告)日：2009-06-02
申请号：US11508771
申请日：2006-08-23
申请人： Alexander Kalnitsky , Michael Church
发明人： Alexander Kalnitsky , Michael Church
IPC分类号： G11C16/04
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.
摘要翻译：根据实施例的多时间可编程（MTP）存储单元包括浮置栅极PMOS晶体管，高电压NMOS晶体管和n阱电容器。浮置栅极PMOS晶体管包括形成存储单元的第一端子，漏极和栅极的源极。高电压NMOS晶体管包括连接到地的源极，连接到PMOS晶体管的漏极的延伸漏极和形成存储器单元的第二端子的栅极。 n阱电容器包括连接到PMOS晶体管的栅极的第一端子和形成存储器单元的第三端子的第二端子。浮置栅极PMOS晶体管可以存储逻辑状态。可以将组合的电压施加到存储单元的第一，第二和第三端子，以编程，禁止程序，读取和擦除逻辑状态。

6. 发明授权

US08647971B2 Method of manufacturing junction barrier schottky diode with dual silicides 有权
标题翻译：制造具有双重硅化物的结型肖特基二极管的方法
公开(公告)号：US08647971B2
公开(公告)日：2014-02-11
申请号：US13356624
申请日：2012-01-23
申请人： Dev Alok Girdhar , Michael David Church , Alexander Kalnitsky
发明人： Dev Alok Girdhar , Michael David Church , Alexander Kalnitsky
IPC分类号： H01L21/28 , H01L21/44
CPC分类号： H01L29/872 , H01L27/0629 , H01L29/456 , H01L29/47 , H01L29/7833
摘要： An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.
摘要翻译：包括结势垒肖特基二极管的集成电路具有N型阱，阱表面中的P型阳极区域和阱表面中的N型肖特基区域，并且水平地邻接阳极区域。第一硅化物层在肖特基区域上并与其相邻的阳极区域形成肖特基接触。与第一硅化物不同的第二硅化物层位于阳极区上。对阳极区域和阱的第二硅化物进行欧姆接触。

7. 发明授权

US07960766B2 Light sensors with infrared suppression 有权
标题翻译：红外线抑制光传感器
公开(公告)号：US07960766B2
公开(公告)日：2011-06-14
申请号：US12817101
申请日：2010-06-16
申请人： Alexander Kalnitsky , Dong Zheng , Joy Jones , Xijian Lin , Gregory Cestra
发明人： Alexander Kalnitsky , Dong Zheng , Joy Jones , Xijian Lin , Gregory Cestra
IPC分类号： H01L31/062
CPC分类号： H01L31/103 , H01L27/1443 , H01L31/02162
摘要： Embodiments of the present invention are directed to light sensors, that primarily respond to visible light while suppressing infrared light. Such sensors are especially useful as ambient light sensors because such sensors can be used to provide a spectral response similar to that of a human eye. Embodiments of the present invention are also directed to methods of providing such light sensors, and methods for using such light sensors.
摘要翻译：本发明的实施例涉及在抑制红外光的同时主要响应于可见光的光传感器。这种传感器作为环境光传感器是特别有用的，因为这样的传感器可用于提供类似于人眼的光谱响应。本发明的实施例还涉及提供这种光传感器的方法，以及使用这种光传感器的方法。

8. 发明申请

US20110116319A1 MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS 有权
公开(公告)号：US20110116319A1
公开(公告)日：2011-05-19
申请号：US13012381
申请日：2011-01-24
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
IPC分类号： G11C16/26
CPC分类号： G11C16/0433
摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.

9. 发明申请

US20100149879A1 FLASH MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS 有权
标题翻译：基于盖板的非易失性记忆体的闪存存储阵列
公开(公告)号：US20100149879A1
公开(公告)日：2010-06-17
申请号：US12711520
申请日：2010-02-24
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Prabhjot Singh , Michael D. Church
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Prabhjot Singh , Michael D. Church
IPC分类号： G11C16/04
CPC分类号： G11C16/0416
摘要： A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译：闪存阵列包括以行和列的矩阵组织的多个存储单元。每个存储单元包括具有源极区和漏极区的浮动栅极存储晶体管，以及电连接到存储晶体管的耦合电容。多个字线各自电连接到相应行中的每个存储器单元中的电容器。第一组位线分别电连接到相应列中的每个存储单元中的存储晶体管的漏极区。多个高压存取晶体管分别电连接到第一组位线中的位线。第二组位线分别电连接到相应列中的每个存储器单元中的存储晶体管的源极区域。在操作中可以对字线和第一和第二组位线施加电压的各种组合，以擦除，编程，禁止或读取存储器晶体管存储在一个或多个存储器单元中的逻辑状态。

10. 发明授权

US07688627B2 Flash memory array of floating gate-based non-volatile memory cells 有权
标题翻译：基于浮动栅极的非易失性存储单元的闪存阵列
公开(公告)号：US07688627B2
公开(公告)日：2010-03-30
申请号：US11861102
申请日：2007-09-25
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Prabhjot Singh , Michael D. Church
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Prabhjot Singh , Michael D. Church
IPC分类号： G11C14/00 , G11C16/04
CPC分类号： G11C16/0416
摘要： A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译：闪存阵列包括以行和列的矩阵组织的多个存储单元。每个存储单元包括具有源极区和漏极区的浮动栅极存储晶体管，以及电连接到存储晶体管的耦合电容。多个字线各自电连接到相应行中的每个存储器单元中的电容器。第一组位线分别电连接到相应列中的每个存储单元中的存储晶体管的漏极区。多个高压存取晶体管分别电连接到第一组位线中的位线。第二组位线分别电连接到相应列中的每个存储器单元中的存储晶体管的源极区域。在操作中可以对字线和第一和第二组位线施加电压的各种组合，以擦除，编程，禁止或读取存储器晶体管存储在一个或多个存储器单元中的逻辑状态。

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