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81. 发明申请

US20120119310A1 STRUCTURE AND METHOD TO FABRICATE A BODY CONTACT 有权
标题翻译：结构和方法来组织身体接触
公开(公告)号：US20120119310A1
公开(公告)日：2012-05-17
申请号：US12944174
申请日：2010-11-11
申请人： Chengwen Pei , Roger Allen Booth, JR. , Kangguo Cheng , Joseph Ervin , Ravi M. Todi , Geng Wang
发明人： Chengwen Pei , Roger Allen Booth, JR. , Kangguo Cheng , Joseph Ervin , Ravi M. Todi , Geng Wang
IPC分类号： H01L29/49 , H01L21/285
CPC分类号： H01L29/49 , H01L21/743 , H01L21/823475 , H01L21/823871 , H01L21/84 , H01L27/1203 , H01L29/78612
摘要： A structure and method to fabricate a body contact on a transistor is disclosed. The method comprises forming a semiconductor structure with a transistor on a handle wafer. The structure is then inverted, and the handle wafer is removed. A silicided body contact is then formed on the transistor in the inverted position. The body contact may be connected to neighboring vias to connect the body contact to other structures or levels to form an integrated circuit.
摘要翻译：公开了一种在晶体管上制造体接触的结构和方法。该方法包括在处理晶片上形成具有晶体管的半导体结构。然后将结构反转，并移除手柄晶片。然后在倒置位置的晶体管上形成硅化物体接触。身体接触可以连接到相邻的通孔，以将身体接触连接到其他结构或水平以形成集成电路。

82. 发明授权

US08742503B2 Recessed single crystalline source and drain for semiconductor-on-insulator devices 有权
标题翻译：用于绝缘体上半导体器件的嵌入式单晶源极和漏极
公开(公告)号：US08742503B2
公开(公告)日：2014-06-03
申请号：US13285162
申请日：2011-10-31
申请人： Geng Wang , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi
发明人： Geng Wang , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi
IPC分类号： H01L27/12
CPC分类号： H01L29/66477 , H01L21/84 , H01L27/1203
摘要： After formation of a gate stack, regions in which a source and a drain are to be formed are recessed through the top semiconductor layer and into an upper portion of a buried single crystalline rare earth oxide layer of a semiconductor-on-insulator (SOI) substrate so that a source trench and drain trench are formed. An embedded single crystalline semiconductor portion epitaxially aligned to the buried single crystalline rare earth oxide layer is formed in each of the source trench and the drain trench to form a recessed source and a recessed drain, respectively. Protrusion of the recessed source and recessed drain above the bottom surface of a gate dielectric can be minimized to reduce parasitic capacitive coupling with a gate electrode, while providing low source resistance and drain resistance through the increased thickness of the recessed source and recessed drain relative to the thickness of the top semiconductor layer.
摘要翻译：在形成栅极叠层之后，要形成源极和漏极的区域通过顶部半导体层凹陷，并进入绝缘体上半导体（SOI）的掩埋的单晶稀土氧化物层的上部，衬底，从而形成源极沟槽和漏极沟槽。在源极沟槽和漏极沟槽的每一个中分别形成外延对齐于埋入的单晶稀土氧化物层的嵌入式单晶半导体部分，以分别形成凹陷源和凹陷漏极。可以将栅极电介质的底表面之上的凹陷源和凹陷漏极的突起最小化，以减少与栅极电极的寄生电容耦合，同时通过凹陷源和凹陷漏极的增加的厚度提供低的源极电阻和漏极电阻，相对于顶部半导体层的厚度。

83. 发明申请

US20130181326A1 MULTILAYER MIM CAPACITOR 有权
公开(公告)号：US20130181326A1
公开(公告)日：2013-07-18
申请号：US13352655
申请日：2012-01-18
申请人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L29/92 , H01L21/02 , B82Y99/00
CPC分类号： H01L28/40 , H01L21/32134 , H01L28/86 , H01L28/90 , H01L28/91
摘要： An improved semiconductor capacitor and method of fabrication is disclosed. A MIM stack, comprising alternating first-type and second-type metal layers (each separated by dielectric) is formed in a deep cavity. The entire stack can be planarized, and then patterned to expose a first area, and selectively etched to recess all first metal layers within the first area. A second selective etch is performed to recess all second metal layers within a second area. The etched recesses can be backfilled with dielectric. Separate electrodes can be formed; a first electrode formed in said first area and contacting all of said second-type metal layers and none of said first-type metal layers, and a second electrode formed in said second area and contacting all of said first-type metal layers and none of said second-type metal layers.

84. 发明申请

US20120171827A1 STRUCTURE AND METHOD TO FORM EDRAM ON SOI SUBSTRATE 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US20120171827A1
公开(公告)日：2012-07-05
申请号：US13417900
申请日：2012-03-12
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

85. 发明授权

US09080239B2 Method and apparatus for angular high density plasma chemical vapor deposition 有权
标题翻译：用于角高密度等离子体化学气相沉积的方法和装置
公开(公告)号：US09080239B2
公开(公告)日：2015-07-14
申请号：US13434934
申请日：2012-03-30
申请人： Daewon Yang , Kangguo Cheng , Pavel Smetana , Richard S. Wise , Keith Kwong Hon Wong
发明人： Daewon Yang , Kangguo Cheng , Pavel Smetana , Richard S. Wise , Keith Kwong Hon Wong
IPC分类号： C23C16/507 , C23C16/34 , C23C16/40 , C23C16/455 , C23C16/458 , C23C16/56 , H01J37/20 , H01J37/32 , H01L27/108 , H01L21/316 , H01L21/318
CPC分类号： C23C16/507 , C23C16/345 , C23C16/402 , C23C16/45578 , C23C16/4586 , C23C16/56 , H01J37/20 , H01J37/321 , H01J2237/20207 , H01J2237/3323 , H01L21/31608 , H01L21/3185 , H01L27/10867
摘要： Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.
摘要翻译：通过形成多个STI沟槽与FET结合形成浅沟槽电容器; 对于FET，在第一和第二STI沟槽之间注入具有第一极性的第一单元阱; 对于电容器，在第三个STI沟槽的区域中注入具有第二极性的第二单元阱; 从第三STI沟槽去除电介质材料; 形成具有位于所述STI沟槽的所述第一和第二STI沟槽之间的第一部分和位于所述第三沟槽中并延伸到所述第三沟槽中的第二部分的栅极堆叠; 并且执行与第二单元阱相同极性的源极/漏极注入，从而在第一单元阱中形成FET，以及在第二单元阱中形成电容器。第二极性可以与第一极性相反。额外的植入物可以减少第二细胞中的ESR。

86. 发明授权

US09059321B2 Buried channel field-effect transistors 有权
标题翻译：埋地通道场效应晶体管
公开(公告)号：US09059321B2
公开(公告)日：2015-06-16
申请号：US13470620
申请日：2012-05-14
申请人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Tak H. Ning
发明人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Tak H. Ning
IPC分类号： H01L21/338 , H01L21/84 , H01L27/12 , H01L29/66 , H01L29/10 , H01L29/786 , H01L29/78 , H01L21/8238 , H01L29/51
CPC分类号： H01L29/0642 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/0692 , H01L29/1054 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/66651 , H01L29/66772 , H01L29/78 , H01L29/78687 , H01L29/78696
摘要： Methods for forming a buried-channel field-effect transistor include doping source and drain regions on a substrate with a dopant having a first type; forming a doped shielding layer on the substrate in a channel region having a second doping type opposite the first type to displace a conducting channel away from a gate-interface region; forming a gate dielectric over the doped shielding layer; and forming a gate on the gate dielectric.
摘要翻译：用于形成掩埋沟道场效应晶体管的方法包括在具有第一类型的掺杂剂的衬底上掺杂源区和漏区; 在具有与第一类型相反的第二掺杂类型的沟道区域中的衬底上形成掺杂的屏蔽层，以使导电沟道偏离栅极 - 界面区域; 在所述掺杂屏蔽层上形成栅极电介质; 并在栅极电介质上形成栅极。

87. 发明授权

US09059207B2 Strained channel for depleted channel semiconductor devices 有权
标题翻译：用于耗尽通道半导体器件的应变通道
公开(公告)号：US09059207B2
公开(公告)日：2015-06-16
申请号：US13613747
申请日：2012-09-13
申请人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Davood Shahrjerdi
发明人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Davood Shahrjerdi
IPC分类号： H01L29/66 , H01L29/78 , H01L29/786
CPC分类号： H01L29/1054 , H01L21/02529 , H01L21/02532 , H01L21/306 , H01L21/31144 , H01L21/324 , H01L29/66545 , H01L29/66553 , H01L29/66772 , H01L29/66795 , H01L29/66803 , H01L29/6681 , H01L29/785 , H01L29/78687
摘要： A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel. The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device.
摘要翻译：一种平面半导体器件，包括绝缘体上半导体（SOI）衬底，源极和漏极部分具有由多层应变通道分离的小于10nm的厚度。 SOI层的多层应变通道包括存在于SOI衬底的掩埋介电层上的第一晶格尺寸的第一层和与第一层直接接触的第二晶格尺寸的第二层的多层应变通道部分。功能栅极结构存在于SOI衬底的多层应变通道部分上。具有多层通道的半导体器件也可以是finFET半导体器件。

88. 发明授权

US09048108B2 Integrated circuit with on chip planar diode and CMOS devices 有权
标题翻译：集成电路与片上平面二极管和CMOS器件
公开(公告)号：US09048108B2
公开(公告)日：2015-06-02
申请号：US13478080
申请日：2012-05-22
申请人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/8238 , H01L27/06
CPC分类号： H01L27/0629 , H01L29/0847 , H01L29/8611 , H01L29/868
摘要： An electrical circuit, planar diode, and method of forming a diode and one or more CMOS devices on the same chip. The method includes electrically isolating a portion of a substrate in a diode region from other substrate regions. The method also includes recessing the substrate in the diode region. The method further includes epitaxially forming in the diode region a first doped layer above the substrate and epitaxially forming in the diode region a second doped layer above the first doped layer.
摘要翻译：在同一芯片上形成二极管和一个或多个CMOS器件的电路，平面二极管和方法。该方法包括将二极管区域中的衬底的一部分与其它衬底区域电隔离。该方法还包括使二极管区域中的衬底凹陷。该方法还包括在二极管区域中外延形成在衬底上方的第一掺杂层，并在二极管区域中外延地形成第一掺杂层上方的第二掺杂层。

89. 发明授权

US09041116B2 Structure and method to modulate threshold voltage for high-K metal gate field effect transistors (FETs) 有权
公开(公告)号：US09041116B2
公开(公告)日：2015-05-26
申请号：US13478154
申请日：2012-05-23
申请人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
发明人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
IPC分类号： H01L27/092 , H01L27/12 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823842
摘要： A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.

90. 发明授权

US08933515B2 Device structure, layout and fabrication method for uniaxially strained transistors 有权
标题翻译：单轴应变晶体管的器件结构，布局和制造方法
公开(公告)号：US08933515B2
公开(公告)日：2015-01-13
申请号：US13531175
申请日：2012-06-22
申请人： Stephen W. Bedell , Huiming Bu , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz , Devendra K. Sadana , Chun-Chen Yeh
发明人： Stephen W. Bedell , Huiming Bu , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz , Devendra K. Sadana , Chun-Chen Yeh
IPC分类号： H01L27/088 , H01L21/8238 , H01L27/02 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/823814 , H01L27/0207 , H01L29/6656 , H01L29/66628 , H01L29/78 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.
摘要翻译：一种用于制造半导体器件的半导体器件和方法包括提供具有第一应变轴的应变半导体层，在应变半导体层的表面内形成有源区，其中有源区具有沿应变轴的纵向轴线并形成栅极结构在活跃地区。在应变半导体层的表面上方和与栅极结构相邻的有源区上形成升高的源/漏区，以形成晶体管器件。

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