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1. 发明授权

US08691697B2 Self-aligned devices and methods of manufacture 失效
标题翻译：自对准装置和制造方法
公开(公告)号：US08691697B2
公开(公告)日：2014-04-08
申请号：US12943956
申请日：2010-11-11
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/302 , B44C1/22
CPC分类号： H01L21/31056 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： A method includes forming patterned lines on a substrate having a predetermined pitch. The method further includes forming spacer sidewalls on sidewalls of the patterned lines. The method further includes forming material in a space between the spacer sidewalls of adjacent patterned lines. The method further includes forming another patterned line from the material by protecting the material in the space between the spacer sidewalls of adjacent patterned lines while removing the spacer sidewalls. The method further includes transferring a pattern of the patterned lines and the another patterned line to the substrate.
摘要翻译：一种方法包括在具有预定间距的基底上形成图案线。该方法还包括在图案化线的侧壁上形成间隔壁。该方法还包括在相邻图案线的间隔壁侧壁之间的空间中形成材料。该方法还包括通过在相邻图案化线的间隔壁侧壁之间的空间中保护材料同时去除间隔壁侧壁而从该材料形成另一图案化线。该方法还包括将图案化线和另一图案化线的图案转移到衬底。

2. 发明授权

US08575670B2 Embedded dynamic random access memory device formed in an extremely thin semiconductor on insulator (ETSOI) substrate 有权
标题翻译：在非常薄的半导体绝缘体（ETSOI）衬底上形成的嵌入式动态随机存取存储器件
公开(公告)号：US08575670B2
公开(公告)日：2013-11-05
申请号：US13316056
申请日：2011-12-09
申请人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L27/10861 , H01L28/91 , H01L29/945
摘要： A memory device including an SOI substrate with a buried dielectric layer having a thickness of less than 30 nm, and a trench extending through an SOI layer and the buried dielectric layer into the base semiconductor layer of the SOI substrate. A capacitor is present in a lower portion of the trench. A dielectric spacer is present on the sidewalls of an upper portion of the trench. The dielectric spacer is present on the portions of the trench where the sidewalls are provided by the SOI layer and the buried dielectric layer. A conductive material fill is present in the upper portion of the trench. A semiconductor device is present on the SOI layer that is adjacent to the trench. The semiconductor device is in electrical communication with the capacitor through the conductive material fill.
摘要翻译：一种存储器件，包括具有厚度小于30nm的掩埋介电层的SOI衬底，以及穿过SOI层的延伸沟槽和埋入电介质层到SOI衬底的基底半导体层中的沟槽。电容器存在于沟槽的下部。电介质垫片存在于沟槽上部的侧壁上。介质间隔物存在于沟槽的部分，其中侧壁由SOI层和埋入的介电层提供。导电材料填充物存在于沟槽的上部。半导体器件存在于与沟槽相邻的SOI层上。半导体器件通过导电材料填充与电容器电连通。

3. 发明授权

US09048339B2 Deep trench capacitor 有权
标题翻译：深沟槽电容器
公开(公告)号：US09048339B2
公开(公告)日：2015-06-02
申请号：US13606448
申请日：2012-09-07
申请人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/84 , H01L29/66 , H01L27/108 , H01L27/12
CPC分类号： H01L28/60 , H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/1203 , H01L29/66181
摘要： A method of forming a deep trench capacitor in a semiconductor-on-insulator substrate is provided. The method may include providing a pad layer positioned above a bulk substrate, etching a deep trench into the pad layer and the bulk substrate extending from a top surface of the pad layer down to a location within the bulk substrate, and doping a portion of the bulk substrate to form a buried plate. The method further including depositing a node dielectric, an inner electrode, and a dielectric cap substantially filling the deep trench, the node dielectric being located between the buried plate and the inner electrode, the dielectric cap being located at a top of the deep trench, removing the pad layer, growing an insulator layer on top of the bulk substrate, and growing a semiconductor-on-insulator layer on top of the insulator layer.
摘要翻译：提供了在绝缘体上半导体衬底中形成深沟槽电容器的方法。该方法可以包括提供定位在大块衬底之上的衬垫层，将深沟槽蚀刻到衬垫层中，以及从衬垫层的顶表面延伸到体衬底内的位置的本体衬底，以及掺杂散装衬底形成掩埋板。该方法还包括沉积基本上填充深沟槽的节点电介质，内部电极和电介质帽，节点电介质位于掩埋板和内部电极之间，电介质帽位于深沟槽的顶部，去除衬垫层，在本体衬底的顶部上生长绝缘体层，以及在绝缘体层的顶部上生长绝缘体上半导体层。

4. 发明申请

US20140061793A1 SUBLITHOGRAPHIC WIDTH FINFET EMPLOYING SOLID PHASE EPITAXY 有权
标题翻译：使用固体相外延片的子图形宽度FINFET
公开(公告)号：US20140061793A1
公开(公告)日：2014-03-06
申请号：US13597752
申请日：2012-08-29
申请人： Chengwen Pei , Kangguo Cheng , Joseph Ervin , Juntao Li , Ravi M. Todi , Geng Wang
发明人： Chengwen Pei , Kangguo Cheng , Joseph Ervin , Juntao Li , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/12 , H01L29/06 , H01L21/336
CPC分类号： H01L27/0886 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/0653 , H01L29/0657 , H01L29/0692 , H01L29/66795
摘要： A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device.
摘要翻译：介电心轴结构形成在单晶半导体层上。非晶半导体材料层沉积在单晶半导体层的物理暴露表面和心轴结构的表面上。可选地，非晶半导体材料层可以注入至少一种不同的半导体材料。在采用单晶半导体层作为种子层的非晶半导体材料层上进行固相外延，从而形成厚度均匀的外延半导体材料层。外延半导体材料层的剩余部分是单晶半导体鳍片，并且这些鳍片的厚度是亚光刻的。在去除介电心轴结构之后，可以采用单晶半导体鳍形成半导体器件。

5. 发明授权

US08637365B2 Spacer isolation in deep trench 有权
公开(公告)号：US08637365B2
公开(公告)日：2014-01-28
申请号：US13489572
申请日：2012-06-06
申请人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/8242
CPC分类号： H01L29/0649 , H01L27/10829 , H01L27/10861 , H01L27/10867 , H01L27/1203 , H01L29/66181 , H01L29/945
摘要： A method of forming improved spacer isolation in deep trench including recessing a node dielectric, a first conductive layer, and a second conductive layer each deposited within a deep trench formed in a silicon-on-insulator (SOI) substrate, to a level below a buried oxide layer of the SOI substrate, and creating an opening having a bottom surface in the deep trench. Further including depositing a spacer along a sidewall of the deep trench and the bottom surface of the opening, and removing the spacer from the bottom surface of the opening. Performing at least one of an ion implantation and an ion bombardment in one direction at an angle into an upper portion of the spacer. Removing the upper portion of the spacer from the sidewall of the deep trench. Depositing a third conductive layer within the opening.

6. 发明授权

US08564069B1 Field effect transistors with low body resistance and self-balanced body potential 有权
标题翻译：具有低体电阻和自平衡体电位的场效应晶体管
公开(公告)号：US08564069B1
公开(公告)日：2013-10-22
申请号：US13590212
申请日：2012-08-21
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L21/823412 , H01L21/823437 , H01L27/027 , H01L29/0615 , H01L29/78
摘要： Embodiments of the invention relate generally to semiconductor devices and, more particularly, to semiconductor devices having field effect transistors (FETs) with a low body resistance and, in some embodiments, a self-balanced body potential where multiple transistors share same body potential. In one embodiment, the invention includes a field effect transistor (FET) comprising a source within a substrate, a drain within the substrate, and an active gate atop the substrate and between the source and the drain, an inactive gate structure atop the substrate and adjacent the source or the drain, a body adjacent the inactive gate, and a discharge path within the substrate for releasing a charge from the FET, the discharge path lying between the active gate of the FET and the body, wherein the discharge path is substantially perpendicular to a width of the active gate.
摘要翻译：本发明的实施例大体上涉及半导体器件，更具体地，涉及具有低体电阻的场效应晶体管（FET）的半导体器件，在一些实施例中，具有多个晶体管共享相同体电位的自平衡体电位。在一个实施例中，本发明包括场效应晶体管（FET），其包括在衬底内的源极，衬底内的漏极，以及位于衬底顶部和源极与漏极之间的有源栅极，在衬底顶部的非活性栅极结构，邻近源极或漏极，与非活性栅极相邻的主体以及衬底内的用于从FET释放电荷的放电路径，放电路径位于FET的有源栅极和主体之间，其中放电路径基本上垂直于有源栅极的宽度。

7. 发明申请

US20130105898A1 Recessed Single Crystalline Source and Drain For Semiconductor-On-Insulator Devices 有权
标题翻译：嵌入式半导体绝缘体器件的单晶硅和漏极
公开(公告)号：US20130105898A1
公开(公告)日：2013-05-02
申请号：US13285162
申请日：2011-10-31
申请人： Geng Wang , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi
发明人： Geng Wang , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66477 , H01L21/84 , H01L27/1203
摘要： After formation of a gate stack, regions in which a source and a drain are to be formed are recessed through the top semiconductor layer and into an upper portion of a buried single crystalline rare earth oxide layer of a semiconductor-on-insulator (SOI) substrate so that a source trench and drain trench are formed. An embedded single crystalline semiconductor portion epitaxially aligned to the buried single crystalline rare earth oxide layer is formed in each of the source trench and the drain trench to form a recessed source and a recessed drain, respectively. Protrusion of the recessed source and recessed drain above the bottom surface of a gate dielectric can be minimized to reduce parasitic capacitive coupling with a gate electrode, while providing low source resistance and drain resistance through the increased thickness of the recessed source and recessed drain relative to the thickness of the top semiconductor layer.
摘要翻译：在形成栅极叠层之后，要形成源极和漏极的区域通过顶部半导体层凹陷，并进入绝缘体上半导体（SOI）的掩埋的单晶稀土氧化物层的上部，衬底，从而形成源极沟槽和漏极沟槽。在源极沟槽和漏极沟槽的每一个中分别形成外延对齐于埋入的单晶稀土氧化物层的嵌入式单晶半导体部分，以分别形成凹陷源和凹陷漏极。可以将栅极电介质的底表面之上的凹陷源和凹陷漏极的突起最小化，以减少与栅极电极的寄生电容耦合，同时通过凹陷源和凹陷漏极的增加的厚度提供低的源极电阻和漏极电阻，相对于顶部半导体层的厚度。

8. 发明授权

US08299530B2 Structure and method to fabricate pFETS with superior GIDL by localizing workfunction 失效
标题翻译：通过定位功能来制造具有优异GIDL的pFETS的结构和方法
公开(公告)号：US08299530B2
公开(公告)日：2012-10-30
申请号：US12717375
申请日：2010-03-04
申请人： Chengwen Pei , Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Ravi M. Todi , Geng Wang
发明人： Chengwen Pei , Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/12 , H01L21/8238
CPC分类号： H01L21/22 , H01L21/8238 , H01L27/092
摘要： A semiconductor structure and a method of forming the same are provided in which the gate induced drain leakage is controlled by introducing a workfunction tuning species within selected portions of a pFET such that the gate/SD (source/drain) overlap area of the pFET is tailored towards flatband, yet not affecting the workfunction at the device channel region. The structure includes a semiconductor substrate having at least one patterned gate stack located within a pFET device region of the semiconductor substrate. The structure further includes extension regions located within the semiconductor substrate at a footprint of the at least one patterned gate stack. A channel region is also present and is located within the semiconductor substrate beneath the at least one patterned gate stack. The structure further includes a localized workfunction tuning area located within a portion of at least one of the extension regions that is positioned adjacent the channel region as well as within at least a sidewall portion of the at least one gate stack. The localized workfunction tuning area can be formed by ion implantation or annealing.
摘要翻译：提供了一种半导体结构及其形成方法，其中通过在pFET的选定部分内引入功函数调谐物质来控制栅极感应漏极泄漏，使得pFET的栅极/ SD（源极/漏极）重叠区域为适应平带，但不影响设备通道区域的功能。该结构包括具有位于半导体衬底的pFET器件区域内的至少一个图案化栅叠层的半导体衬底。所述结构还包括位于所述半导体衬底内的所述至少一个图案化栅叠层的覆盖区的扩展区。沟道区域也存在并且位于至少一个图案化栅叠层下方的半导体衬底内。该结构进一步包括位于至少一个延伸区域的一部分内的局部功能调谐区域，其位于邻近通道区域以及至少一个栅极叠层的至少一个侧壁部分内。通过离子注入或退火可形成局部功能调谐区域。

9. 发明授权

US08809994B2 Deep isolation trench structure and deep trench capacitor on a semiconductor-on-insulator substrate 有权
标题翻译：绝缘体上半导体衬底上的深度隔离沟槽结构和深沟槽电容器
公开(公告)号：US08809994B2
公开(公告)日：2014-08-19
申请号：US13316104
申请日：2011-12-09
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/70
CPC分类号： H01L27/1087 , H01L27/10829 , H01L27/1203 , H01L29/945
摘要： Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions.
摘要翻译：在绝缘体上半导体（SOI）衬底中形成具有不同宽度的两个沟槽。在沟槽中形成不透氧层和填充材料层。从第一沟槽内去除填充材料层和不透氧层。执行热氧化以将第一沟槽的侧壁下方的半导体材料转换成上部热氧化物部分和下部热氧化物部分，而在第二沟槽的侧壁上的剩余的不透氧层防止半导体材料的氧化。在第二沟槽的侧壁上形成节点电介质之后，沉积导电材料以填充沟槽，从而分别形成导电沟槽填充部分和内部电极。上部和下部热氧化物部分用作电绝缘两个器件区域的介电材料部分的部件。

10. 发明申请

US20140070292A1 DEEP TRENCH CAPACITOR 有权
标题翻译：深层电容电容
公开(公告)号：US20140070292A1
公开(公告)日：2014-03-13
申请号：US13606448
申请日：2012-09-07
申请人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/108 , H01L21/311
CPC分类号： H01L28/60 , H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/1203 , H01L29/66181
摘要： A method of forming a deep trench capacitor in a semiconductor-on-insulator substrate is provided. The method may include providing a pad layer positioned above a bulk substrate, etching a deep trench into the pad layer and the bulk substrate extending from a top surface of the pad layer down to a location within the bulk substrate, and doping a portion of the bulk substrate to form a buried plate. The method further including depositing a node dielectric, an inner electrode, and a dielectric cap substantially filling the deep trench, the node dielectric being located between the buried plate and the inner electrode, the dielectric cap being located at a top of the deep trench, removing the pad layer, growing an insulator layer on top of the bulk substrate, and growing a semiconductor-on-insulator layer on top of the insulator layer.
摘要翻译：提供了在绝缘体上半导体衬底中形成深沟槽电容器的方法。该方法可以包括提供定位在大块衬底之上的衬垫层，将深沟槽蚀刻到衬垫层中，以及从衬垫层的顶表面延伸到体衬底内的位置的本体衬底，以及掺杂散装衬底形成掩埋板。该方法还包括沉积基本上填充深沟槽的节点电介质，内部电极和电介质帽，节点电介质位于掩埋板和内部电极之间，电介质帽位于深沟槽的顶部，去除衬垫层，在本体衬底的顶部上生长绝缘体层，以及在绝缘体层的顶部上生长绝缘体上半导体层。

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