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1. 发明申请

US20140216839A1 FRONT-END STRUCTURE OF A MOTOR VEHICLE 有权
标题翻译：电动汽车的前端结构
公开(公告)号：US20140216839A1
公开(公告)日：2014-08-07
申请号：US14169947
申请日：2014-01-31
申请人： Franz Ulrich Brockhoff , Stefan Grottke , Stefan Schmitz
发明人： Franz Ulrich Brockhoff , Stefan Grottke , Stefan Schmitz
IPC分类号： B62D21/15
CPC分类号： B62D21/155 , B62D21/152
摘要： A front-end structure of a motor vehicle includes a transverse member and two crash boxes. In addition a transverse reinforcement member is arranged according to the invention, wherein the transverse reinforcement member is supported via coupling beams on a subframe.
摘要翻译：机动车辆的前端结构包括横向构件和两个碰撞箱。此外，根据本发明布置横向加强构件，其中横向加强构件通过在子框架上的耦合梁被支撑。

2. 发明申请

US20140024181A1 SEMICONDUCTOR STRUCTURE HAVING NFET EXTENSION LAST IMPLANTS 有权
标题翻译：具有NFET延伸最后植入物的半导体结构
公开(公告)号：US20140024181A1
公开(公告)日：2014-01-23
申请号：US13551054
申请日：2012-07-17
申请人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Bala S. Haran , Pranita Kulkarni , Amlan Majumdar , Stefan Schmitz
发明人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Bala S. Haran , Pranita Kulkarni , Amlan Majumdar , Stefan Schmitz
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L27/1203
摘要： A method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. An amorphous silicon layer is formed on the RSD in the PFET portion. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The amorphous layer in the PFET portion prevents epitaxial growth in the PFET portion during formation of the RSD in the NFET portion. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.
摘要翻译：一种形成半导体结构的方法，其包括具有PFET部分和NFET部分的极薄的绝缘体上硅（ETSOI）半导体结构，PFET部分中的栅极结构和NFET部分，高质量氮化物间隔物 PFET部分中的栅极结构和NFET部分以及PFET部分中的掺杂多面外延硅锗升高源极/漏极（RSD）。在PFET部分的RSD上形成非晶硅层。在与NFET部分中的高质量氮化物相邻的ETSOI上形成刻面外延硅RSD。 PFET部分中的非晶层防止在NFET部分中形成RSD期间在PFET部分中的外延生长。扩展件被离子注入到NFET部分中的栅极结构下面的ETSOI中。

3. 发明申请

US20130334603A1 ISOLATION STRUCTURE FOR SEMICONDUCTOR DEVICES 审中-公开
标题翻译：半导体器件隔离结构
公开(公告)号：US20130334603A1
公开(公告)日：2013-12-19
申请号：US13525650
申请日：2012-06-18
申请人： Kangguo CHENG , Bruce B. DORIS , Shom PONOTH , Stefan SCHMITZ , Raghavasimhan SREENIVASAN
发明人： Kangguo CHENG , Bruce B. DORIS , Shom PONOTH , Stefan SCHMITZ , Raghavasimhan SREENIVASAN
IPC分类号： H01L29/78 , H01L21/302
CPC分类号： H01L21/76283 , H01L21/76232 , H01L29/66772 , H01L29/78654
摘要： A method including etching a shallow trench laterally surrounding a portion of a semiconductor substrate, the semiconductor substrate comprising a semiconductor-on-insulator SOI layer, a pad oxide layer, and a pad nitride layer, depositing a first nitride liner, a dielectric liner, and a second nitride liner in the shallow trench, wherein the dielectric liner is located between the first and the second nitride liner, and filling the shallow trench with a shallow trench fill portion.
摘要翻译：一种方法，包括蚀刻横向围绕半导体衬底的一部分的浅沟槽，所述半导体衬底包括绝缘体上半导体SOI层，衬垫氧化物层和衬垫氮化物层，沉积第一氮化物衬垫，介电衬垫，以及浅沟槽中的第二氮化物衬垫，其中所述电介质衬垫位于所述第一和第二氮化物衬垫之间，并且用浅沟槽填充部分填充所述浅沟槽。

4. 发明申请

US20130319613A1 CUT-VERY-LAST DUAL-EPI FLOW 有权
标题翻译：切割 - 最近的双EPI流程
公开(公告)号：US20130319613A1
公开(公告)日：2013-12-05
申请号：US13545456
申请日：2012-07-10
申请人： Veeraraghavan S. Basker , Huiming Bu , Kangguo Cheng , Balasubramanian S. Haran , Nicolas Loubet , Shom Ponoth , Stefan Schmitz , Theodorus E. Standaert , Tenko Yamashita
发明人： Veeraraghavan S. Basker , Huiming Bu , Kangguo Cheng , Balasubramanian S. Haran , Nicolas Loubet , Shom Ponoth , Stefan Schmitz , Theodorus E. Standaert , Tenko Yamashita
IPC分类号： H01L21/308
CPC分类号： H01L29/66795 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/6681
摘要： A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method. The method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material. Apparatus and computer program products are also described.
摘要翻译：描述了制造双外延FinFET的方法。该方法包括将第一外延材料添加到翅片阵列。该方法还包括使用第一掩蔽材料覆盖翅片阵列的至少第一部分并且从翅片阵列的未覆盖部分移除第一外延材料。在散热片阵列的未覆盖部分中的翅片上添加第二外延材料包括在该方法中。该方法还包括使用第二掩模材料覆盖翅片阵列的第二部分，并使用第一掩模材料和第二掩模材料执行定向蚀刻。还描述了装置和计算机程序产品。

5. 发明申请

US20130313643A1 Structure and Method to Modulate Threshold Voltage For High-K Metal Gate Field Effect Transistors (FETs) 有权
标题翻译：用于调制高K金属栅场效应晶体管（FET）的阈值电压的结构和方法
公开(公告)号：US20130313643A1
公开(公告)日：2013-11-28
申请号：US13478154
申请日：2012-05-23
申请人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
发明人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
IPC分类号： H01L27/12 , H01L27/092 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823842
摘要： A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.
摘要翻译：一种用于形成电气装置的方法，包括在半导体衬底上形成高k栅介质层，该半导体衬底被图案化以将存在于第一导电器件区域上的高k栅介质层的第一部分与第二部分分离存在于第二导电装置区域上的高k栅介质层。连接栅极导体形成在高k栅介质层的第一部分和第二部分上。连接栅极导体从隔离区域上的第一导电器件区域延伸到第二导电器件区域。然后可以将第一导电器件区域和第二导电器件区域中的一个暴露于含氧气氛中。用含氧气氛曝光改变暴露的半导体器件的阈值电压。

6. 发明申请

US20130001750A1 FILM STACK INCLUDING METAL HARDMASK LAYER FOR SIDEWALL IMAGE TRANSFER FIN FIELD EFFECT TRANSISTOR FORMATION 有权
标题翻译：包括金属硬质合金层的薄膜堆叠，用于边缘图像传输金场效应晶体管形成
公开(公告)号：US20130001750A1
公开(公告)日：2013-01-03
申请号：US13171868
申请日：2011-06-29
申请人： JOHN C. ARNOLD , Sivananda K. Kanakasabapathy , Stefan Schmitz , Yunpeng Yin
发明人： JOHN C. ARNOLD , Sivananda K. Kanakasabapathy , Stefan Schmitz , Yunpeng Yin
IPC分类号： H01L29/06 , H01L21/311
CPC分类号： H01L21/3088 , H01L21/3086 , H01L21/845 , H01L29/66795
摘要： A method for formation of a fin field effect transistor (FinFET) device includes forming a mandrel mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer; forming a large feature (FX) mask on the metal hardmask layer; etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer; etching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask.
摘要翻译：用于形成鳍状场效应晶体管（FinFET）器件的方法包括在膜堆叠的金属硬掩模层上形成心轴掩模，所述膜堆叠包括位于金属硬掩模层下面的绝缘体上硅层（SOI）层; 在金属硬掩模层上形成大特征（FX）掩模; 将芯棒掩模和FX掩模同时蚀刻到金属硬掩模层中; 使用蚀刻的金属硬掩模层作为掩模将芯棒掩模和FX掩模刻蚀成SOI层。

7. 发明授权

US08084329B2 Transistor devices and methods of making 失效
标题翻译：晶体管器件及其制造方法
公开(公告)号：US08084329B2
公开(公告)日：2011-12-27
申请号：US12693629
申请日：2010-01-26
申请人： John C. Arnold , Xuefeng Hua , Rangarajan Jagannathan , Stefan Schmitz
发明人： John C. Arnold , Xuefeng Hua , Rangarajan Jagannathan , Stefan Schmitz
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.
摘要翻译：在一个实施例中，制造晶体管器件的方法包括：提供半导体形貌，其包括设置在一对电介质间隔物之间的半导体衬底之上的栅极导体; 各向异性地蚀刻介电间隔物的相对侧上的半导体衬底的暴露区域，以在衬底中形成凹陷区域; 在所述凹陷区域中氧化所述衬底的暴露表面以在其上形成氧化物; 从凹陷区域的底部除去氧化物，同时将氧化物保持在凹陷区域的侧壁上; 并且各向同性蚀刻所述基板，使得所述凹陷区域切割所述一对电介质间隔物。

8. 发明申请

US20110001957A1 DISTANCE-MEASURING OPTOELECTRONIC SENSOR 有权
标题翻译：距离测量光电传感器
公开(公告)号：US20110001957A1
公开(公告)日：2011-01-06
申请号：US12825433
申请日：2010-06-29
申请人： Ingolf BRAUNE , Markus HAMMES , Stefan SCHMITZ , Shane MACNAMARA
发明人： Ingolf BRAUNE , Markus HAMMES , Stefan SCHMITZ , Shane MACNAMARA
IPC分类号： G01C3/08
CPC分类号： F16P3/144 , F16P3/142 , G01B11/00 , G01B11/026 , G01C3/14 , G01S17/026 , G01S17/42 , G01S17/89 , G06K9/00771 , G06K9/2027
摘要： A distance-measuring optoelectronic sensor for the monitoring of a working zone is provided which is located within a detection zone of the sensor and at a first distance from the sensor, wherein the sensor has a lighting unit having a light source to illuminate the working zone at least partly as well as an object detection unit by means of which unauthorized objects in the working zone can be detected. In this respect, an illumination control is designed, in a switching-on phase, first to activate the lighting unit with a lower power so that a provisional working zone at a second distance from the sensor less than the first distance is illuminated with at most a preset maximum power; to check by means of the object detection unit whether an unauthorized object intrusion is taking place into the provisional working zone; and if no unauthorized object intrusion is recognized, to activate the lighting unit at a higher power so that the working zone is illuminated with at most the preset maximum power.
摘要翻译：提供了用于监测工作区域的测距光电传感器，其位于传感器的检测区域内并距离传感器第一距离处，其中传感器具有照明单元，该照明单元具有照亮工作区域的光源至少部分地以及物体检测单元，通过该物体检测单元可以检测到工作区域中的未经授权的物体。在这方面，照明控制在接通阶段首先被设计成以较低的功率激活照明单元，使得距传感器小于第一距离的第二距离处的临时工作区最多被照亮预设最大功率; 通过对象检测单元检查临时工作区内是否有未经授权的对象入侵; 并且如果未识别到未经授权的对象入侵，则以较高功率激活照明单元，使得工作区域以最多预设的最大功率被照亮。

9. 发明申请

US20070200194A1 Apparatus And Method For Temperature-Interrupting Protection Of An Electric Device 审中-公开
标题翻译：电气设备温度中断保护装置及方法
公开(公告)号：US20070200194A1
公开(公告)日：2007-08-30
申请号：US11680342
申请日：2007-02-28
申请人： Alfons Graf , Josef Hoeglauer , Martin Schneider-Ramelow , Stefan Schmitz , Klaus-Dieter Lang
发明人： Alfons Graf , Josef Hoeglauer , Martin Schneider-Ramelow , Stefan Schmitz , Klaus-Dieter Lang
IPC分类号： H01L31/058
CPC分类号： H01L23/34 , H01L23/4952 , H01L23/62 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05618 , H01L2224/05644 , H01L2224/45124 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48699 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/0102 , H01L2924/01023 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01055 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/13091 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/00014 , H01L2924/00 , H01L2224/48744 , H01L2224/48718 , H01L2924/00012
摘要： A current load of an electric device having a current inlet or current outlet can be protected cost-effectively and efficiently via a contact pad in the current inlet or current outlet when a first conductive material and the second conductive material are connected conductively in the contact pad such that the first conductive material and the second conductive material can form an eutectic mixture which has a fusion temperature below the fusion temperature of the individual materials and when the contact pad is additionally implemented such that the conductive connection between the first and second materials is interrupted when a fused eutectic mixture occurs.
摘要翻译：当第一导电材料和第二导电材料在接触垫中导电地连接时，具有当前入口或电流出口的电气设备的电流负载可以通过当前入口或电流出口中的接触焊盘成本有效且有效地被保护使得第一导电材料和第二导电材料可以形成熔融温度低于单个材料的熔化温度的熔融混合物，并且当另外实施接触焊盘时，使得第一和第二材料之间的导电连接被中断当发生熔融共晶混合物时。

10. 发明授权

US5699679A Cryogenic aerosol separator 失效
标题翻译：低温气溶胶分离器
公开(公告)号：US5699679A
公开(公告)日：1997-12-23
申请号：US691702
申请日：1996-07-31
申请人： Jin Jwang Wu , William Albert Cavaliere , James Patrick Norum , Stefan Schmitz
发明人： Jin Jwang Wu , William Albert Cavaliere , James Patrick Norum , Stefan Schmitz
IPC分类号： B07B7/00 , F25J1/00
CPC分类号： B07B7/00
摘要： A cryogenic aerosol separator/classifier for separating and selectively removing particles from a stream of aerosol. The aerosol stream is produced by a cryogenic aerosol generator comprising a reservoir containing a cryogenic gas-liquid mixture at a first pressure, a delivery line coupled to the reservoir, and a nozzle. The nozzle has at least one exit opening which allows the cryogenic gas-liquid mixture to expand from the first pressure to a lower pressure and, thus, to produce cryogenic aerosol. A separator is coupled to the nozzle, such that the light particles having high mobility are removed from the stream, thereby producing a stream of cryogenic flow with particles having a controlled size to clean a contaminated surface. The apparatus is enhanced by utilizing a magnetic field and/or specially designed flow fields to fully take advantage of the enhanced mobilities of light particles.
摘要翻译：用于从气溶胶流中分离和选择性除去颗粒的低温气溶胶分离器/分级器。气溶胶流由低温气溶胶发生器产生，所述低温气溶胶发生器包括在第一压力下包含低温气体 - 液体混合物的储存器，连接到储存器的输送管线和喷嘴。喷嘴具有至少一个出口，其允许低温气液混合物从第一压力膨胀到较低的压力，从而产生低温气溶胶。分离器联接到喷嘴，使得具有高迁移率的轻粒子从流中除去，从而产生具有受控尺寸的颗粒的低温流，以清洁被污染的表面。该设备通过利用磁场和/或特别设计的流场来增强，以充分利用光粒子的增强的迁移率。

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