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81. 发明授权

US08176444B2 Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance 有权
标题翻译：分析多个诱导的系统和统计布局对电路性能的影响
公开(公告)号：US08176444B2
公开(公告)日：2012-05-08
申请号：US12426475
申请日：2009-04-20
申请人： Shayak Banerjee , Dureseti Chidambarrao , James A. Culp , Praveen Elakkumanan , Saibal Mukhopadhyay
发明人： Shayak Banerjee , Dureseti Chidambarrao , James A. Culp , Praveen Elakkumanan , Saibal Mukhopadhyay
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F2217/10
摘要： A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.
摘要翻译：一种用于实现系统的变异感知集成电路提取的方法包括：将一组处理条件输入到多个变化模型，每个模型对应于与集成电路布局的半导体制造相关联的单独的系统参数变化; 针对每个变化模型生成归因于相关变化的网表更新，其中网表更新是相对于从集成电路布局提取的原始网表的更新; 以及存储针对每个处理条件生成的网表更新。

82. 发明授权

US08168489B2 High performance stress-enhanced MOSFETS using Si:C and SiGe epitaxial source/drain and method of manufacture 有权
标题翻译：使用Si：C和SiGe外延源/漏极的高性能应力增强MOSFETs及其制造方法
公开(公告)号：US08168489B2
公开(公告)日：2012-05-01
申请号：US11782429
申请日：2007-07-24
申请人： Huajie Chen , Dureseti Chidambarrao , Omer H. Dokumaci
发明人： Huajie Chen , Dureseti Chidambarrao , Omer H. Dokumaci
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/3081 , H01L21/823807 , H01L21/823814 , H01L27/092 , H01L29/1054 , H01L29/66628 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.
摘要翻译：半导体器件及半导体器件的制造方法。半导体器件包括用于pFET和nFET的沟道。在pFET沟道的源极和漏极区域选择性地生长SiGe层，并且在nFET沟道的源极和漏极区域选择性地生长Si：C层。 SiGe和Si：C层与下层Si层的晶格网络匹配以产生应力分量。在一个实现中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。

83. 发明授权

US08119472B2 Silicon device on Si:C SOI and SiGe and method of manufacture 有权
标题翻译： Si：C SOI和SiGe上的硅器件及其制造方法
公开(公告)号：US08119472B2
公开(公告)日：2012-02-21
申请号：US11757883
申请日：2007-06-04
申请人： Dureseti Chidambarrao , Omer H. Dokumaci , Oleg G. Gluschenkov
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Oleg G. Gluschenkov
IPC分类号： H01L21/8238
CPC分类号： H01L29/1608 , H01L21/8213 , H01L21/823412 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/1054 , H01L29/1095 , H01L29/66651 , H01L29/7378 , H01L29/7843 , H01L29/7846 , H01L29/7849 , H01L29/8086
摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.
摘要翻译：提供半导体结构和制造方法。制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。第一材料和第二材料通过热退火工艺混合到衬底中，以分别在nFET区和pFET区形成第一岛和第二岛。在第一岛和第二岛上形成不同材料的层。科学技术组织放松并促进第一个岛屿和第二个岛屿的放松。可以将第一材料沉积或生长Ge材料，并且第二材料可以沉积或生长Si：C或C.在第一岛和第二岛中的至少一个上形成应变Si层。

84. 发明授权

US08013397B2 Embedded stressed nitride liners for CMOS performance improvement 有权
标题翻译：嵌入式应力氮化物衬垫可提高CMOS性能
公开(公告)号：US08013397B2
公开(公告)日：2011-09-06
申请号：US12049450
申请日：2008-03-17
申请人： Dureseti Chidambarrao , Omer H. Dokumaci
发明人： Dureseti Chidambarrao , Omer H. Dokumaci
IPC分类号： H01L27/00
CPC分类号： H01L21/823807 , H01L21/28247 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces of the substrate adjacent to the gate region, the nitride liner providing a stress to a device channel underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 275 MPa to about 450 MPa.
摘要翻译：本发明提供了一种半导体器件，其包括位于衬底的台面部分上的栅极区域; 以及位于所述栅极区域上的氮化物衬垫和与所述栅极区域相邻的所述衬底的凹陷表面，所述氮化物衬垫向所述栅极区域下方的器件沟道施加压力。在器件通道上产生的应力是大约275MPa至大约450MPa的纵向应力。

85. 发明授权

US08004059B2 eFuse containing SiGe stack 有权
标题翻译： eFuse包含SiGe堆栈
公开(公告)号：US08004059B2
公开(公告)日：2011-08-23
申请号：US11622616
申请日：2007-01-12
申请人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
发明人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.
摘要翻译： eFuse包括：衬底和设置在衬底上的绝缘层; 包括设置在所述绝缘层上的单晶或多晶硅的第一层; 包括设置在第一层上的单晶或多晶硅锗的第二层，以及包括设置在第二层上的硅化物的第三层。 Ge的终浓度范围约为百分之五至百分之二十五。

86. 发明授权

US07989233B2 Semiconductor nanowire with built-in stress 失效
公开(公告)号：US07989233B2
公开(公告)日：2011-08-02
申请号：US13004340
申请日：2011-01-11
申请人： Lidija Sekaric , Dureseti Chidambarrao , Xiao H. Liu
发明人： Lidija Sekaric , Dureseti Chidambarrao , Xiao H. Liu
IPC分类号： H01L29/06
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/517 , H01L29/66439 , H01L29/7843 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.

87. 发明申请

US20110147885A1 FORMATION OF IMPROVED SOI SUBSTRATES USING BULK SEMICONDUCTOR WAFERS 有权
标题翻译：使用块状半导体波形形成改进的SOI衬底
公开(公告)号：US20110147885A1
公开(公告)日：2011-06-23
申请号：US13037608
申请日：2011-03-01
申请人： William K. Henson , Dureseti Chidambarrao , Kern Rim , Hsingjen Wann , Hung Y. Ng
发明人： William K. Henson , Dureseti Chidambarrao , Kern Rim , Hsingjen Wann , Hung Y. Ng
IPC分类号： H01L23/58
CPC分类号： H01L21/764 , H01L21/76283
摘要： The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.
摘要翻译：本发明涉及具有一个或多个器件区域的绝缘体上半导体（SOI）衬底。每个器件区域至少包括基底半导体衬底层和其间设置有掩埋绝缘体层的半导体器件层，而半导体器件层由一个或多个垂直绝缘柱支撑。垂直绝缘柱各自优选地具有在基底半导体衬底层和半导体器件层之间延伸的凸缘。本发明的SOI衬底可以容易地由具有“浮动”半导体器件层的前体衬底结构形成，半导体器件层通过气隙与基底半导体衬底层间隔开并由一个或多个垂直绝缘柱支撑。气隙优选通过选择性地去除位于基底半导体衬底层和半导体器件层之间的牺牲层来形成。

88. 发明授权

US07960809B2 eFuse with partial SiGe layer and design structure therefor 有权
标题翻译： eFuse部分SiGe层及其设计结构
公开(公告)号：US07960809B2
公开(公告)日：2011-06-14
申请号：US12354996
申请日：2009-01-16
申请人： Chandrasekharan Kothandaraman , Deok-kee Kim , Dureseti Chidambarrao , William K. Henson
发明人： Chandrasekharan Kothandaraman , Deok-kee Kim , Dureseti Chidambarrao , William K. Henson
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse includes a fuse link region, a first region and a second region. The fuse link region electrically connects the first region to the second region. A SiGe layer is disposed only in the fuse link region and the first region.
摘要翻译：熔丝包括熔丝链接区域，第一区域和第二区域。熔丝链路区域将第一区域电连接到第二区域。 SiGe层仅设置在熔丝连接区域和第一区域中。

89. 发明授权

US07776695B2 Semiconductor device structure having low and high performance devices of same conductive type on same substrate 失效
标题翻译：具有相同基板上相同导电类型的低和高性能器件的半导体器件结构
公开(公告)号：US07776695B2
公开(公告)日：2010-08-17
申请号：US11306716
申请日：2006-01-09
申请人： John C. Arnold , Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Siddhartha Panda , Brian L. Tessier , Richard Wise
发明人： John C. Arnold , Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Siddhartha Panda , Brian L. Tessier , Richard Wise
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823864 , H01L27/0922 , H01L29/6656 , H01L29/7842 , H01L29/7843
摘要： A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region disposed intermediate of the first gate and the second gate, silicides on the first gate, the second gate and respective source and drain regions; forming additional spacers on the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure.
摘要翻译：一种制造半导体器件结构的方法，包括：提供衬底; 在衬底上形成具有第一间隔物的第一栅极，具有第二间隔物的第二栅极，与第一栅极和第二栅极相邻的相同导电类型的相应源极和漏极区域，设置在第一栅极和第二栅极之间的隔离区域栅极，第一栅极上的硅化物，第二栅极和相应的源极和漏极区域; 在第一间隔物上形成附加间隔物以产生中间结构，然后在整个中间结构上设置应力层。

90. 发明授权

US07675118B2 Semiconductor structure with enhanced performance using a simplified dual stress liner configuration 失效
标题翻译：使用简化的双重应力衬垫配置提高性能的半导体结构
公开(公告)号：US07675118B2
公开(公告)日：2010-03-09
申请号：US11468958
申请日：2006-08-31
申请人： Dureseti Chidambarrao , Yaocheng Liu , William K. Henson
发明人： Dureseti Chidambarrao , Yaocheng Liu , William K. Henson
IPC分类号： H01L27/12
CPC分类号： H01L21/28097 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/4908 , H01L29/4975 , H01L29/665 , H01L29/66545 , H01L29/7843
摘要： A semiconductor structure including an nFET having a fully silicided gate electrode wherein a new dual stress liner configuration is used to enhance the stress in the channel region that lies beneath the gate electrode is provided. The new dual stress liner configuration includes a first stress liner that has an upper surface that is substantially planar with an upper surface of a fully silicided gate electrode of the nFET. In accordance with the present invention, the first stress liner is not present atop the nFET including the fully silicided gate electrode. Instead, the first stress liner of the present invention partially wraps around, i.e., surrounds the sides of, the nFET with the fully silicided gate electrode. A second stress liner having an opposite polarity as that of the first stress liner (i.e., of an opposite stress type) is located on the upper surface of the first stress liner as well as atop the nFET that contains the fully silicided FET. In accordance with the present invention, the first stress liner is a tensile stress liner and the second stress liner is a compressive stress liner.
摘要翻译：提供了包括具有完全硅化栅电极的nFET的半导体结构，其中使用新的双应力衬垫配置来增强位于栅电极下方的沟道区中的应力。新的双应力衬垫构造包括第一应力衬垫，其具有与nFET的完全硅化栅电极的上表面基本上平面的上表面。根据本发明，第一应力衬垫不存在于包括全硅化物栅电极的nFET顶部。相反，本发明的第一应力衬垫部分地包裹着nFET的侧面，即用完全硅化的栅电极包围nFET。具有与第一应力衬垫相反极性（即相反应力类型）的第二应力衬垫位于第一应力衬垫的上表面上以及位于包含完全硅化FET的nFET顶上。根据本发明，第一应力衬垫是拉伸应力衬垫，第二应力衬垫是压应力衬垫。

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