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1. 发明申请

US20110272779A1 EFUSE CONTAINING SIGE STACK 有权
标题翻译： EFUSE包含信号堆栈
公开(公告)号：US20110272779A1
公开(公告)日：2011-11-10
申请号：US13189016
申请日：2011-07-22
申请人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
发明人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.
摘要翻译： eFuse包括：衬底和设置在衬底上的绝缘层; 包括设置在所述绝缘层上的单晶或多晶硅的第一层; 包括设置在第一层上的单晶或多晶硅锗的第二层，以及包括设置在第二层上的硅化物的第三层。 Ge的终浓度范围约为百分之五至百分之二十五。

2. 发明授权

US07943493B2 Electrical fuse having a fully silicided fuselink and enhanced flux divergence 有权
标题翻译：电熔丝具有完全硅化的富熔体和增强的焊剂分散
公开(公告)号：US07943493B2
公开(公告)日：2011-05-17
申请号：US12873882
申请日：2010-09-01
申请人： Dureseti Chidambarrao , William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman
发明人： Dureseti Chidambarrao , William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01L21/20
CPC分类号： H01L23/5256 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.
摘要翻译：在绝缘体区域上形成两个不均匀半导体层的堆叠的连续块，例如浅沟槽隔离。连续块的一部分暴露于蚀刻，而另一部分在蚀刻期间被掩蔽。蚀刻去除在暴露部分中对下半导体层有选择性的上半导体层。去除蚀刻掩模，并且暴露区域内的下半导体层的整体被金属化。形成垂直邻接绝缘体区域的第一金属半导体合金，同时将包含上半导体层的材料的两个非均匀半导体层的堆叠的暴露表面同时金属化以形成第二金属半导体合金。在两个金属半导体合金的边界处形成电流的拐点，从而形成磁通发散区域。

3. 发明申请

US20100330783A1 ELECTRICAL FUSE HAVING A FULLY SILICIDED FUSELINK AND ENHANCED FLUX DIVERGENCE 有权
标题翻译：全自动充电式电熔炉和增强型流量分流器
公开(公告)号：US20100330783A1
公开(公告)日：2010-12-30
申请号：US12873882
申请日：2010-09-01
申请人： Dureseti Chidambarrao , William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman
发明人： Dureseti Chidambarrao , William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01L21/20
CPC分类号： H01L23/5256 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.
摘要翻译：在绝缘体区域上形成两个不均匀半导体层的堆叠的连续块，例如浅沟槽隔离。连续块的一部分暴露于蚀刻，而另一部分在蚀刻期间被掩蔽。蚀刻去除在暴露部分中对下半导体层有选择性的上半导体层。去除蚀刻掩模，并且暴露区域内的下半导体层的整体被金属化。形成垂直邻接绝缘体区域的第一金属半导体合金，同时将包含上半导体层的材料的两个非均匀半导体层的堆叠的暴露表面同时金属化以形成第二金属半导体合金。在两个金属半导体合金的边界处形成电流的拐点，从而形成磁通发散区域。

4. 发明申请

US20080169529A1 EFUSE CONTAINING SIGE STACK 有权
标题翻译： EFUSE包含信号堆栈
公开(公告)号：US20080169529A1
公开(公告)日：2008-07-17
申请号：US11622616
申请日：2007-01-12
申请人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
发明人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.
摘要翻译： eFuse包括：衬底和设置在衬底上的绝缘层; 包括设置在所述绝缘层上的单晶或多晶硅的第一层; 包括设置在第一层上的单晶或多晶硅锗的第二层，以及包括设置在第二层上的硅化物的第三层。 Ge的终浓度范围约为百分之五至百分之二十五。

5. 发明授权

US08004059B2 eFuse containing SiGe stack 有权
标题翻译： eFuse包含SiGe堆栈
公开(公告)号：US08004059B2
公开(公告)日：2011-08-23
申请号：US11622616
申请日：2007-01-12
申请人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
发明人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.
摘要翻译： eFuse包括：衬底和设置在衬底上的绝缘层; 包括设置在所述绝缘层上的单晶或多晶硅的第一层; 包括设置在第一层上的单晶或多晶硅锗的第二层，以及包括设置在第二层上的硅化物的第三层。 Ge的终浓度范围约为百分之五至百分之二十五。

6. 发明授权

US08299570B2 Efuse containing sige stack 有权
标题翻译： Efuse包含sige堆栈
公开(公告)号：US08299570B2
公开(公告)日：2012-10-30
申请号：US13189016
申请日：2011-07-22
申请人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
发明人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.
摘要翻译： eFuse包括：衬底和设置在衬底上的绝缘层; 包括设置在所述绝缘层上的单晶或多晶硅的第一层; 包括设置在第一层上的单晶或多晶硅锗的第二层，以及包括设置在第二层上的硅化物的第三层。 Ge的终浓度范围约为百分之五至百分之二十五。

7. 发明授权

US07838963B2 Electrical fuse having a fully silicided fuselink and enhanced flux divergence 有权
标题翻译：电熔丝具有完全硅化的富熔体和增强的焊剂分散
公开(公告)号：US07838963B2
公开(公告)日：2010-11-23
申请号：US11925164
申请日：2007-10-26
申请人： Dureseti Chidambarrao , William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman
发明人： Dureseti Chidambarrao , William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01L29/86
CPC分类号： H01L23/5256 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.
摘要翻译：在绝缘体区域上形成两个不均匀半导体层的堆叠的连续块，例如浅沟槽隔离。连续块的一部分暴露于蚀刻，而另一部分在蚀刻期间被掩蔽。蚀刻去除在暴露部分中对下半导体层有选择性的上半导体层。去除蚀刻掩模，并且暴露区域内的下半导体层的整体被金属化。形成垂直邻接绝缘体区域的第一金属半导体合金，同时将包含上半导体层的材料的两个非均匀半导体层的堆叠的暴露表面同时金属化以形成第二金属半导体合金。在两个金属半导体合金的边界处形成电流的拐点，从而形成磁通发散区域。

8. 发明申请

US20090108396A1 ELECTRICAL FUSE HAVING A FULLY SILICIDED FUSELINK AND ENHANCED FLUX DIVERGENCE 有权
标题翻译：全自动充电式电熔炉和增强型流量分流器
公开(公告)号：US20090108396A1
公开(公告)日：2009-04-30
申请号：US11925164
申请日：2007-10-26
申请人： Dureseti Chidambarrao , William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman
发明人： Dureseti Chidambarrao , William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01L29/86 , H01L21/71
CPC分类号： H01L23/5256 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.
摘要翻译：在绝缘体区域上形成两个不均匀半导体层的堆叠的连续块，例如浅沟槽隔离。连续块的一部分暴露于蚀刻，而另一部分在蚀刻期间被掩蔽。蚀刻去除在暴露部分中对下半导体层有选择性的上半导体层。去除蚀刻掩模，并且暴露区域内的下半导体层的整体被金属化。形成垂直邻接绝缘体区域的第一金属半导体合金，同时将包含上半导体层的材料的两个非均匀半导体层的堆叠的暴露表面同时金属化以形成第二金属半导体合金。在两个金属半导体合金的边界处形成电流的拐点，从而形成磁通发散区域。

9. 发明申请

US20090090993A1 SINGLE CRYSTAL FUSE ON AIR IN BULK SILICON 有权
标题翻译：单晶硅中的单晶保险丝
公开(公告)号：US20090090993A1
公开(公告)日：2009-04-09
申请号：US11867268
申请日：2007-10-04
申请人： William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman , Byeongju Park
发明人： William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman , Byeongju Park
IPC分类号： H01L29/00 , H01L21/02
CPC分类号： H01L23/5256 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： An integrated eFUSE device is formed by forming a silicon “floating beam” on air, whereupon the fusible portion of the eFUSE device resides. This beam extends between two larger, supporting terminal structures. “Undercutting” techniques are employed whereby a structure is formed atop a buried layer, and that buried layer is removed by selective etching. Whereby a “floating” silicide eFUSE conductor is formed on a silicon beam structure. In its initial state, the eFUSE silicide is highly conductive, exhibiting low electrical resistance (the “unblown state of the eFUSE). When a sufficiently large current is passed through the eFUSE conductor, localized heating occurs. This heating causes electromigration of the silicide into the silicon beam (and into surrounding silicon, thereby diffusing the silicide and greatly increasing its electrical resistance. When the current source is removed, the silicide remains permanently in this diffused state, the “blown” state of the eFUSE.
摘要翻译：通过在空气中形成硅“浮动光束”形成集成eFUSE装置，于是eFUSE装置的可熔部分驻留。该梁在两个更大的支撑端子结构之间延伸。采用“底切”技术，由此在掩埋层顶部形成结构，并且通过选择性蚀刻去除掩埋层。由此在硅梁结构上形成“浮动”硅化物eFUSE导体。在初始状态下，eFUSE硅化物具有高导电性，表现出较低的电阻（eFUSE的未吹出状态），当足够大的电流通过eFUSE导体时，发生局部加热，该加热导致硅化物的电迁移（并且进入周围的硅，从而扩散硅化物并大大增加其电阻。当电流源被去除时，硅化物永久地保持在这种扩散状态，eFUSE的“吹”状态。

10. 发明授权

US07745855B2 Single crystal fuse on air in bulk silicon 有权
标题翻译：单晶保险丝在散装硅中的空气中
公开(公告)号：US07745855B2
公开(公告)日：2010-06-29
申请号：US11867268
申请日：2007-10-04
申请人： William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman , Byeongju Park
发明人： William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman , Byeongju Park
IPC分类号： H01L27/10
CPC分类号： H01L23/5256 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： An integrated eFUSE device is formed by forming a silicon “floating beam” on air, whereupon the fusible portion of the eFUSE device resides. This beam extends between two larger, supporting terminal structures. “Undercutting” techniques are employed whereby a structure is formed atop a buried layer, and that buried layer is removed by selective etching. Whereby a “floating” silicide eFUSE conductor is formed on a silicon beam structure. In its initial state, the eFUSE silicide is highly conductive, exhibiting low electrical resistance (the “unblown state of the eFUSE). When a sufficiently large current is passed through the eFUSE conductor, localized heating occurs. This heating causes electromigration of the silicide into the silicon beam (and into surrounding silicon, thereby diffusing the silicide and greatly increasing its electrical resistance. When the current source is removed, the silicide remains permanently in this diffused state, the “blown” state of the eFUSE.
摘要翻译：通过在空气中形成硅“浮动光束”形成集成eFUSE装置，于是eFUSE装置的可熔部分驻留。该梁在两个较大的支撑端子结构之间延伸。采用“底切”技术，由此在掩埋层顶部形成结构，并且通过选择性蚀刻去除掩埋层。由此在硅梁结构上形成“浮动”硅化物eFUSE导体。在其初始状态下，eFUSE硅化物具有高导电性，表现出低电阻（eFUSE的未吹出状态）。当足够大的电流通过eFUSE导体时，发生局部加热。这种加热导致硅化物的电迁移到硅束（并进入周围的硅，从而扩散硅化物，并大大增加其电阻。当电流源被去除时，硅化物永久地保持在这种扩散状态，“吹”状态 eFUSE。

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