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81. 发明申请

US20050277257A1 Gap filling with a composite layer 失效
标题翻译：间隙填充复合层
公开(公告)号：US20050277257A1
公开(公告)日：2005-12-15
申请号：US10857829
申请日：2004-06-01
申请人： Jeong Byun , Zheng Yuan , Shankar Venkataraman , M. Karim , Thanh Pham , Ellie Yieh
发明人： Jeong Byun , Zheng Yuan , Shankar Venkataraman , M. Karim , Thanh Pham , Ellie Yieh
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76224
摘要： A method of filling a gap formed between adjacent raised surfaces on a substrate. In one embodiment the method comprises depositing a boron-doped silica glass (BSG) layer over the substrate to partially fill the gap using a thermal CVD process; exposing the BSG layer to a steam ambient at a temperature above the BSG layer's Eutectic temperature; removing an upper portion of the BSG layer by exposing the layer to a fluorine-containing etchant; and depositing an undoped silica glass (USG) layer over the BSG layer to fill the remainder of the gap.
摘要翻译：填充在基板上相邻的凸起表面之间形成的间隙的方法。在一个实施例中，该方法包括在衬底上沉积硼掺杂石英玻璃（BSG）层，以使用热CVD工艺部分填充间隙; 在高于BSG层的共晶温度的温度下将BSG层暴露于蒸汽环境; 通过将层暴露于含氟蚀刻剂来除去BSG层的上部; 以及在BSG层上沉积未掺杂的二氧化硅玻璃（USG）层以填补间隙的剩余部分。

82. 发明申请

US20050103266A1 Accelerated plasma clean 有权
标题翻译：加速等离子清洁
公开(公告)号：US20050103266A1
公开(公告)日：2005-05-19
申请号：US10968420
申请日：2004-10-18
申请人： Shankar Chandran , Scott Hendrickson , Gwendolyn Jones , Shankar Venkataraman , Ellie Yieh
发明人： Shankar Chandran , Scott Hendrickson , Gwendolyn Jones , Shankar Venkataraman , Ellie Yieh
IPC分类号： B08B9/08 , C23C16/44 , H01L21/304 , C25F1/00 , C23C16/00
CPC分类号： C23C16/4405 , Y10S134/902 , Y10S438/905
摘要： A method and apparatus that reduces the time required to clean a processing chamber employing a reactive plasma cleaning process. A plasma is formed in an Astron fluorine source generator from a flow of substantially pure inert-source gas. After formation of the plasma, a flow of a fluorine source gas is introduced therein such that the fluorine source flow accelerates at a rate no greater than 1.67 standard cubic centimeters per second2 (scc/s2). In this fashion, the plasma contains a plurality of radicals and dissociated inert-source gas atoms, defining a cleaning mixture. The ratio of inert-source gas to fluorine source is greater than 1:1.
摘要翻译：一种减少使用反应性等离子体清洗工艺清洁处理室所需时间的方法和装置。在基本上纯的惰性气体气体的流中，在Astron氟源发生器中形成等离子体。在形成等离子体之后，引入氟源气体的流动，使得氟源流以不大于1.67标准立方厘米/秒的速度加速（scc / s < 2 ）。以这种方式，等离子体包含多个自由基和解离的惰性气体原子，限定清洁混合物。惰性气体与氟源的比例大于1:1。

83. 发明授权

US06709721B2 Purge heater design and process development for the improvement of low k film properties 失效
标题翻译：吹扫加热器设计和工艺开发，用于改善低k膜性能
公开(公告)号：US06709721B2
公开(公告)日：2004-03-23
申请号：US09820586
申请日：2001-03-28
申请人： Juan Carlos Rocha-Alvarez , Chen-An Chen , Ellie Yieh , Shankar Venkataraman
发明人： Juan Carlos Rocha-Alvarez , Chen-An Chen , Ellie Yieh , Shankar Venkataraman
IPC分类号： C23C1640
CPC分类号： C23C16/45521 , C23C16/401 , C23C16/455 , C23C16/4585 , H01L21/02126 , H01L21/02211 , H01L21/02274 , H01L21/31633 , Y10T428/31
摘要： The present invention provides a method of depositing a carbon doped silicon oxide film having a low dielectric constant (k). A process gas mixture containing at least a carrier gas, an oxidizer, a carbon gas source, or combinations thereof, is supplied adjacent an edge of a substrate though a purge gas inlet in a substrate support to facilitate deposition of low k carbon doped silicon oxide film having a greater concentration of silicon oxide around the edge of the substrate than an inner portion of the substrate.
摘要翻译：本发明提供一种沉积具有低介电常数（k）的碳掺杂氧化硅膜的方法。含有至少载体气体，氧化剂，碳气体源或其组合的工艺气体混合物通过衬底支撑件中的吹扫气体入口邻近衬底的边缘提供，以便于沉积低k碳掺杂氧化硅膜比衬底的内部具有比衬底边缘更高浓度的氧化硅。

84. 发明授权

US09530674B2 Method and system for three-dimensional (3D) structure fill 有权
标题翻译：三维（3D）结构填充的方法和系统
公开(公告)号：US09530674B2
公开(公告)日：2016-12-27
申请号：US14044138
申请日：2013-10-02
申请人： Ellie Yieh , Ludovic Godet , Srinivas Nemani , Er-Xuan Ping , Gary Dickerson
发明人： Ellie Yieh , Ludovic Godet , Srinivas Nemani , Er-Xuan Ping , Gary Dickerson
IPC分类号： H01L21/00 , H01L21/67 , C23C14/02 , C23C14/04 , C23C16/02 , C23C16/04 , H01L21/02
CPC分类号： H01L21/02271 , C23C14/021 , C23C14/046 , C23C16/0227 , C23C16/045 , C23C16/45544 , C23C16/50 , H01J37/32009 , H01J2237/334 , H01L21/02266 , H01L21/02274 , H01L21/0228 , H01L21/02315 , H01L21/2855 , H01L21/28556 , H01L21/31116 , H01L21/32136 , H01L21/67017 , H01L21/67213 , H01L21/76224
摘要： Embodiments include methods and systems of 3D structure fill. In one embodiment, a method of filling a trench in a wafer includes performing directional plasma treatment with an ion beam at an angle with respect to a sidewall of the trench to form a treated portion of the sidewall and an untreated bottom of the trench. A material is deposited in the trench. The deposition rate of the material on the treated portion of the sidewall is different than a second deposition rate on the untreated bottom of the trench. In one embodiment, a method includes depositing a material on the wafer, filling a bottom of the trench and forming a layer on a sidewall of the trench and a top surface adjacent to the trench. The method includes etching the layer with an ion beam at an angle with respect to the sidewall.
摘要翻译：实施例包括3D结构填充的方法和系统。在一个实施例中，在晶片中填充沟槽的方法包括使用离子束相对于沟槽的侧壁以一定角度执行定向等离子体处理，以形成侧壁的处理部分和沟槽的未处理底部。材料沉积在沟槽中。材料在侧壁的处理部分上的沉积速率不同于沟槽的未处理底部上的第二沉积速率。在一个实施例中，一种方法包括在晶片上沉积材料，填充沟槽的底部并在沟槽的侧壁上形成层，以及邻近沟槽的顶表面。该方法包括用相对于侧壁成一定角度的离子束蚀刻该层。

85. 发明授权

US08940642B2 Method of multiple patterning of a low-K dielectric film 有权
标题翻译：低K电介质膜的多次图案化方法
公开(公告)号：US08940642B2
公开(公告)日：2015-01-27
申请号：US13187304
申请日：2011-07-20
申请人： Srinivas D. Nemani , Yifeng Zhou , Dmitry Lubomirsky , Ellie Yieh
发明人： Srinivas D. Nemani , Yifeng Zhou , Dmitry Lubomirsky , Ellie Yieh
IPC分类号： H01L21/311 , H01L21/3105 , H01L21/768 , H01L21/02
CPC分类号： H01L21/31116 , H01L21/02126 , H01L21/02203 , H01L21/3105 , H01L21/31138 , H01L21/31144 , H01L21/76802 , H01L21/76811 , H01L21/76813 , H01L21/76826
摘要： Methods of multiple patterning of low-k dielectric films are described. For example, a method includes forming and patterning a first mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. A second mask layer is formed and patterned above the first mask layer. A pattern of the second mask layer is transferred at least partially into the low-k dielectric layer by modifying first exposed portions of the low-k dielectric layer with a first plasma process and removing the modified portions of the low-k dielectric layer. Subsequently, a pattern of the first mask layer is transferred at least partially into the low-k dielectric layer by modifying second exposed portions of the low-k dielectric layer with a second plasma process and removing the modified portions of the low-k dielectric layer.
摘要翻译：描述了低k电介质膜的多次图案化方法。例如，一种方法包括在低k电介质层上形成和图案化第一掩模层，低k电介质层设置在衬底之上。第二掩模层在第一掩模层之上形成并图案化。通过用第一等离子体处理修改低k电介质层的第一暴露部分并去除低k电介质层的修改部分，将第二掩模层的图案至少部分地转移到低k电介质层中。随后，通过用第二等离子体处理修改低k电介质层的第二暴露部分，将第一掩模层的图案至少部分地转移到低k电介质层中，并且去除低k电介质层的修饰部分。

86. 发明申请

US20120073501A1 PROCESS CHAMBER FOR DIELECTRIC GAPFILL 审中-公开
标题翻译：电介质加工室
公开(公告)号：US20120073501A1
公开(公告)日：2012-03-29
申请号：US13248567
申请日：2011-09-29
申请人： Dmitry Lubomirsky , Qiwei Liang , Soonam Park , Kien N. Chuc , Ellie Yieh
发明人： Dmitry Lubomirsky , Qiwei Liang , Soonam Park , Kien N. Chuc , Ellie Yieh
IPC分类号： C23C16/50 , C23C16/455
CPC分类号： C23C16/45502 , C23C16/401 , C23C16/402 , C23C16/452 , C23C16/45514 , C23C16/45565 , C23C16/45574 , C23C16/45576 , C23C16/45578 , C23C16/4584 , C23C16/4586 , C23C16/505 , C23C16/509 , C23C16/52 , H01J37/32082 , H01J37/32357 , H01J37/3244 , H01J37/32724 , H01J37/32752 , H01J2237/2001 , H01J2237/3321 , H01L21/02164 , H01L21/02274 , H01L21/76224
摘要： A system to form a dielectric layer on a substrate from a plasma of dielectric precursors is described. The system may include a deposition chamber, a substrate stage in the deposition chamber to hold the substrate, and a remote plasma generating system coupled to the deposition chamber, where the plasma generating system is used to generate a dielectric precursor having one or more reactive radicals. The system may include a precursor distribution system that includes at least one top inlet and a plurality of side inlets. The top inlet may be positioned above the substrate stage and the side inlets may be radially distributed around the substrate stage. The reactive radical precursor may be supplied to the deposition chamber through the top inlet. An in-situ plasma generating system may also be included to generate the plasma in the deposition chamber from the dielectric precursors supplied to the deposition chamber.
摘要翻译：描述了从电介质前体的等离子体在衬底上形成电介质层的系统。该系统可以包括沉积室，用于保持衬底的沉积室中的衬底台和耦合到沉积室的远程等离子体生成系统，其中等离子体产生系统用于产生具有一个或多个反应性基团的电介质前体。该系统可以包括前体分配系统，其包括至少一个顶部入口和多个侧入口。顶部入口可以位于衬底台的上方，并且侧入口可以在衬底台周围径向分布。反应性自由基前体可以通过顶部入口提供给沉积室。还可以包括原位等离子体产生系统，以从沉积室中提供的电介质前体在沉积室中产生等离子体。

87. 发明授权

US07678662B2 Memory cell having stressed layers 失效
标题翻译：具有应力层的记忆单元
公开(公告)号：US07678662B2
公开(公告)日：2010-03-16
申请号：US11609851
申请日：2006-12-12
申请人： Reza Arghavani , Ellie Yieh , Hichem M'Saad
发明人： Reza Arghavani , Ellie Yieh , Hichem M'Saad
IPC分类号： H01L21/76
CPC分类号： H01L29/7846 , H01L27/105 , H01L27/1052 , H01L29/66825 , H01L29/7883
摘要： A memory cell comprises a p-doped substrate with a pair of spaced apart n-doped regions on the substrate that form a source and drain about the channel. A stack of layers on the channel comprises, in sequence, (i) a tunnel oxide layer, (ii) a floating gate, (iii) an inter-gate dielectric, and (iv) a control gate. A polysilicon layer is on the source and drain. A cover layer covering the stack of layers comprises a spacer layer and a pre-metal-deposition layer. Optionally, contacts are used to contact each of the source, drain, and silicide layers, and each have exposed portions. A shallow isolation trench is provided about n-doped regions, the trench comprising a stressed silicon oxide layer having a tensile stress of at least about 200 MPa. The stressed layer reduces leakage of charge held in the floating gate during operation of the memory cell.
摘要翻译：存储单元包括在基板上具有一对间隔开的n掺杂区域的p掺杂衬底，其在沟道周围形成源极和漏极。通道上的层叠层包括（i）隧道氧化物层，（ii）浮动栅极，（iii）栅极间电介质和（iv）控制栅极。源极和漏极上的多晶硅层。覆盖层叠层的覆盖层包括间隔层和预金属沉积层。可选地，使用触点来接触源极，漏极和硅化物层中的每一个，并且每个都具有暴露部分。围绕n掺杂区域提供浅的隔离沟槽，沟槽包括具有至少约200MPa的拉伸应力的应力氧化硅层。应力层在存储器单元的操作期间减少了保持在浮动栅极中的电荷的泄漏。

88. 发明申请

US20070034153A1 Thermal management of inductively coupled plasma reactors 有权
标题翻译：电感耦合等离子体反应器的热管理
公开(公告)号：US20070034153A1
公开(公告)日：2007-02-15
申请号：US11200431
申请日：2005-08-09
申请人： Siqing Lu , Qiwei Liang , Irene Chou , Steven Kim , Young Lee , Ellie Yieh , Muhammad Rasheed
发明人： Siqing Lu , Qiwei Liang , Irene Chou , Steven Kim , Young Lee , Ellie Yieh , Muhammad Rasheed
IPC分类号： H01L21/306 , C23C16/00
CPC分类号： H01J37/32522 , H01J37/321
摘要： An RF coil assembly provides a source to generate a plasma inductively in a process chamber. The RF coil assembly includes an RF coil disposed about a perimeter of the processing chamber and a frame disposed about a perimeter of the processing chamber. The frame is adapted to support the RF coil in position. An interface material is disposed between and in thermal contact with the frame and a sidewall of the processing chamber. The interface material has a thermal conductivity of 4.0 W/mK or greater.
摘要翻译： RF线圈组件提供源以在处理室中感应地产生等离子体。 RF线圈组件包括围绕处理室的周边布置的RF线圈和围绕处理室的周边设置的框架。框架适于将RF线圈支撑在适当位置。界面材料设置在框架和处理室的侧壁之间并与之热接触。界面材料的导热率为4.0W / mK以上。

89. 发明授权

US07008484B2 Method and apparatus for deposition of low dielectric constant materials 有权
公开(公告)号：US07008484B2
公开(公告)日：2006-03-07
申请号：US10140324
申请日：2002-05-06
申请人： Kang Sub Yim , Soovo Sen , Dian Sugiarto , Peter Lee , Ellie Yieh
发明人： Kang Sub Yim , Soovo Sen , Dian Sugiarto , Peter Lee , Ellie Yieh
IPC分类号： C23C16/00 , C23F1/00 , H01L21/306
CPC分类号： C23C16/45565 , C23C16/5096 , H01J37/32082 , H01J37/3244
摘要： A showerhead adapted for distributing gases into a process chamber and a method for forming dielectric layers on a substrate are generally provided. In one embodiment, a showerhead for distributing gases in a processing chamber includes an annular body coupled between a disk and a mounting flange. The disk has a plurality of holes formed therethrough. A lip extends from a side of the disk opposite the annular body and away from the mounting flange. The showerhead may be used for the deposition of dielectric materials on a substrate. In one embodiment, silicon nitride and silicon oxide layers are formed on the substrate without removing the substrate from a processing chamber utilizing the showerhead of the present invention.

90. 发明申请

US20050255667A1 Method of inducing stresses in the channel region of a transistor 失效
标题翻译：在晶体管的沟道区域中产生应力的方法
公开(公告)号：US20050255667A1
公开(公告)日：2005-11-17
申请号：US10846734
申请日：2004-05-14
申请人： Reza Arghavani , Zheng Yuan , Ellie Yieh , Shankar Venkataraman , Nitin Ingle
发明人： Reza Arghavani , Zheng Yuan , Ellie Yieh , Shankar Venkataraman , Nitin Ingle
IPC分类号： H01L21/336 , H01L21/76 , H01L21/8238 , H01L29/00 , H01L29/78
CPC分类号： H01L29/6656 , H01L21/823807 , H01L29/6659 , H01L29/7833 , H01L29/7846
摘要： A method of fabricating a semiconductor device, where the method includes forming on a transistor on a substrate, where the transistor includes a channel region configured to conduct charge between a source region and a drain region, forming a trench adjacent to the transistor, depositing a material on the substrate and within the trench, and annealing the material, where the material is tensile following the annealing and creates a tensile stress in the channel region. Also, a method of forming a trench isolation in a semiconductor device, where the method includes forming a trench in a substrate, forming a material within the trench at a lower deposition rate, forming the material on the substrate at a higher deposition rate after the depositing of the material within the trench, and annealing the material, where after the annealing the material in the trench is tensile.
摘要翻译：一种制造半导体器件的方法，其中所述方法包括在衬底上的晶体管上形成晶体管，其中所述晶体管包括被配置为在源极区域和漏极区域之间导电的沟道区域，形成与所述晶体管相邻的沟槽，材料在衬底上并在沟槽内，并退火材料，其中材料在退火之后是拉伸的，并且在沟道区域中产生拉伸应力。另外，在半导体器件中形成沟槽隔离的方法，其中所述方法包括在衬底中形成沟槽，以较低的沉积速率在沟槽内形成材料，在衬底上以更高的沉积速率在衬底上形成材料在沟槽内沉积材料并退火材料，其中在退火之后，沟槽中的材料是拉伸的。

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