专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US06261948B1 Method of forming contact openings 有权
公开(公告)号：US06261948B1
公开(公告)日：2001-07-17
申请号：US09285322
申请日：1999-04-02
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： H01L214763
CPC分类号： H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a contact opening is described and which includes providing a node location to which electrical connection is to be made; forming a conductive line adjacent the node location, the conductive line having a conductive top and sidewall surfaces; forming electrically insulative oxide in covering relation relative to the top surface of the conductive line; forming electrically insulative nitride sidewall spacers over the conductive sidewall surfaces, the nitride sidewall spacers projecting outwardly of the conductive line top conductive surface, the electrically insulative oxide positioned between the nitride sidewall spacers; forming an electrically insulative layer outwardly of the conductive line, and the node location; and etching a contact opening to the node location or the top surface through the electrically insulative layer substantially selective relative to the nitride sidewall spacers.

82. 发明授权

US06233190B1 Method of storing a temperature threshold in an integrated circuit, method of modifying operation of dynamic random access memory in response to temperature, programmable temperature sensing circuit and memory integrated circuit 有权
标题翻译：在集成电路中存储温度阈值的方法，响应于温度修改动态随机存取存储器的操作的方法，可编程温度感测电路和存储器集成电路
公开(公告)号：US06233190B1
公开(公告)日：2001-05-15
申请号：US09386075
申请日：1999-08-30
申请人： Christopher B. Cooper , Ming-Bo Liu , Chris G. Martin , Troy A. Manning , Stephen L. Casper , Charles H. Dennison , Brian M. Shirley , Brian L. Brown , Shubneesh Batra
发明人： Christopher B. Cooper , Ming-Bo Liu , Chris G. Martin , Troy A. Manning , Stephen L. Casper , Charles H. Dennison , Brian M. Shirley , Brian L. Brown , Shubneesh Batra
IPC分类号： G11C704
CPC分类号： G11C7/04 , G11C7/1045 , G11C7/20 , G11C11/4072 , G11C11/4078
摘要： A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses. As a result, the integrated circuit is able to provide signals to devices external to the integrated circuit to indicate that the integrated circuit may be too hot to operate properly.
摘要翻译：一种用于在集成电路中存储温度阈值的方法包括：测量集成电路的相对于温度的操作参数，计算集成电路性能超过预定规格的最大温度，并将集成电路性能中最高温度的参数存储在集成电路中的比较电路中通过在比较电路中选择性地吹入可熔设备。可熔断器件可以是反熔丝。因此，集成电路能够向集成电路外部的设备提供信号，以指示集成电路可能太热而无法正常工作。

83. 发明授权

US06200842B1 Method of forming complementary type conductive regions on a substrate 有权
标题翻译：在基板上形成互补型导电区域的方法
公开(公告)号：US06200842B1
公开(公告)日：2001-03-13
申请号：US09547194
申请日：2000-04-11
申请人： Trung Tri Doan , Charles H. Dennison
发明人： Trung Tri Doan , Charles H. Dennison
IPC分类号： H01L218238
CPC分类号： H01L21/82385 , H01L21/823842
摘要： A method of forming complementary type conductive regions on a substrate includes, a) providing a first etch stop layer over a substrate; b) etching a void through the first etch stop layer inwardly towards the substrate; c) providing a first conductive layer of a first conductive material over the first etch stop layer and into the void; d) removing the first conductive layer over the first etch stop layer to eliminate all first conductive material from atop the first etch stop layer, and leaving first conductive material in the void; e) removing the remaining first etch stop layer from the substrate thereby defining a remaining region of first conductive layer; f) providing a second conductive layer of a second conductive material over the substrate and remaining first conductive layer region; and g) removing the second conductive layer over the first conductive layer to eliminate all second conductive material from atop the first conductive layer, and leaving second conductive material atop the substrate which is adjacent the projecting first conductive material region.
摘要翻译：在衬底上形成互补型导电区域的方法包括：a）在衬底上提供第一蚀刻停止层; b）通过第一蚀刻停止层向衬底内部蚀刻空隙; c）在所述第一蚀刻停止层上并在所述空隙中提供第一导电材料的第一导电层; d）去除第一蚀刻停止层上的第一导电层，以从第一蚀刻停止层顶部消除所有第一导电材料，并将第一导电材料留在空隙中; e）从衬底去除剩余的第一蚀刻停止层，从而限定第一导电层的剩余区域; f）在所述衬底上提供第二导电材料的第二导电层和剩余的第一导电层区域; 以及g）在所述第一导电层之上移除所述第二导电层以从所述第一导电层顶部消除所有第二导电材料，并且在所述基板的顶部与所述突出的第一导电材料区域相邻处留下第二导电材料。

84. 发明授权

US06184096B2 Semiconductor processing method of providing dopant impurity into a semiconductor substrate 有权
标题翻译：向半导体衬底提供掺杂杂质的半导体处理方法
公开(公告)号：US06184096B2
公开(公告)日：2001-02-06
申请号：US09276976
申请日：1999-03-26
申请人： Roger R. Lee , Charles H. Dennison
发明人： Roger R. Lee , Charles H. Dennison
IPC分类号： H01L21336
CPC分类号： H01L21/76216 , H01L21/823418 , H01L21/823878
摘要： A semiconductor processing method of providing dopant impurity into a semiconductor substrate includes: a) providing a semiconductor substrate, the substrate comprising a first bulk region having a blanket doping of a first conductivity type dopant, the substrate comprising a second bulk region having a blanket doping of a second conductivity type dopant; b) defining field oxide regions and active area regions in each of the first and second bulk substrate regions; c) in the same masking step, masking active area regions of the first bulk substrate region while leaving field oxide regions of the first bulk substrate region unmasked and masking field oxide regions of the second bulk substrate region while leaving select active area regions of the second bulk substrate region unmasked; and d) in the same ion implanting step, ion implanting first conductivity type impurity through the unmasked portions of the first and second bulk substrate regions to simultaneously form channel stop isolation implants beneath the unmasked field oxide regions in the first bulk substrate region and electrically conductive active area implants in the unmasked active area regions of the second bulk substrate region.
摘要翻译：向半导体衬底提供掺杂杂质的半导体处理方法包括：a）提供半导体衬底，该衬底包括具有第一导电类型掺杂剂的覆盖掺杂的第一体区，该衬底包括具有覆盖掺杂的第二体区的第二导电型掺杂剂; b）限定所述第一和第二体基板区域中的每一个中的场氧化物区域和有源区域区域; c）在相同的掩蔽步骤中，掩蔽所述第一体基板区域的有源区域区域，同时保留所述第一体基板区域的场氧化物区域未掩蔽并掩蔽所述第二体基板区域的场氧化物区域，同时留下所述第二体基板区域的选择有源区域区域散装衬底区域未屏蔽; 以及d）在相同的离子注入步骤中，通过第一和第二体衬底区域的未屏蔽部分离子注入第一导电类型杂质，以同时在第一体衬底区域中未掩模的场氧化物区域下面形成沟道截止隔离植入物，并且导电在第二体基板区域的未掩蔽的有源区域区域中的有源区植入。

85. 发明授权

US6140219A Method of forming contact openings 失效
标题翻译：形成接触孔的方法
公开(公告)号：US6140219A
公开(公告)日：2000-10-31
申请号：US127577
申请日：1998-07-31
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： H01L21/8242 , H01L23/485 , H01L29/417 , H01L21/4763 , H01L21/3205
CPC分类号： H01L27/10873 , H01L23/485 , H01L29/41725 , H01L2924/0002 , Y10S257/90 , Y10S257/906
摘要： A method for forming a contact opening is described and which includes providing a node location to which electrical connection is to be made; forming a conductive line adjacent the node location, the conductive line having a conductive top and sidewall surfaces; forming electrically insulative oxide in covering relation relative to the top surface of the conductive line; forming electrically insulative nitride sidewall spacers over the conductive sidewall surfaces, the nitride sidewall spacers projecting outwardly of the conductive line top conductive surface, the electrically insulative oxide positioned between the nitride sidewall spacers; forming an electrically insulative layer outwardly of the conductive line, and the node location; and etching a contact opening to the node location or the top surface through the electrically insulative layer substantially selective relative to the nitride sidewall spacers.
摘要翻译：描述了一种用于形成接触开口的方法，其包括提供将要进行电连接的节点位置; 在所述节点位置附近形成导线，所述导电线具有导电顶部和侧壁表面; 形成相对于导电线的顶表面的覆盖关系的电绝缘氧化物; 在所述导电侧壁表面上形成电绝缘氮化物侧壁隔离物，所述氮化物侧壁间隔物从所述导电线顶部导电表面向外突出，所述电绝缘氧化物位于所述氮化物侧壁间隔物之间; 在导电线外部形成电绝缘层，以及节点位置; 以及通过所述电绝缘层蚀刻到所述节点位置或所述顶表面的接触开口，所述电绝缘层相对于所述氮化物侧壁间隔件基本上是选择性的。

86. 发明授权

US6124616A Integrated circuitry comprising halo regions and LDD regions 失效
标题翻译：包含晕圈区和LDD区的集成电路
公开(公告)号：US6124616A
公开(公告)日：2000-09-26
申请号：US49282
申请日：1998-03-26
申请人： Charles H. Dennison , Mark Helm
发明人： Charles H. Dennison , Mark Helm
IPC分类号： H01L21/8238 , H01L27/092 , H01L27/105 , H01L29/76
CPC分类号： H01L21/823807 , H01L27/0922 , H01L27/105
摘要： A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor; b) masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and c) in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration at a second depth within both the PMOS substrate area and the NMOS substrate area, the first energy level and the first depth being greater than the second energy level and the second depth, respectively. Methods of forming memory and other CMOS integrated circuitry are also disclosed involving optimization of different NMOS transistors.
摘要翻译：一种形成CMOS集成电路的方法包括：a）在半导体衬底上提供一系列栅极线，第一栅极线相对于衬底的区域定位以形成NMOS晶体管，第二栅极线相对于用于形成PMOS晶体管的衬底的区域; b）在将p型卤素离子注入进入与第一栅极线相邻的NMOS衬底区域的同时掩蔽第二栅极线和PMOS衬底区域，p型卤素离子注入以第一能级进行，以提供p 在NMOS衬底区域内的第一深度处的第一杂质浓度; 和c）在共同的步骤中，将磷离子注入到与第一和第二栅极线相邻的NMOS衬底区域和PMOS衬底区域中，分别形成NMOS LDD区和PMOS n型晕区，磷植入在第二能级进行，以在PMOS衬底区域和NMOS衬底区域内的第二深度处提供n型第二杂质浓度，第一能级和第一深度大于第二能级，第二级深度。还公开了形成存储器和其它CMOS集成电路的方法，其涉及不同NMOS晶体管的优化。

87. 发明授权

US6117721A Semiconductor processing method of forming a static random access memory cell and static random access memory cell 失效
标题翻译：形成静态随机存取存储单元和静态随机存取存储单元的半导体处理方法
公开(公告)号：US6117721A
公开(公告)日：2000-09-12
申请号：US979406
申请日：1997-11-26
申请人： Charles H. Dennison , Ken Marr
发明人： Charles H. Dennison , Ken Marr
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/10
CPC分类号： H01L27/11 , H01L29/1033 , H01L2924/0002 , Y10S438/945
摘要： A semiconductor processing method of forming a static random access memory cell having an n-channel access transistor includes, providing a bulk semiconductor substrate; patterning the substrate for definition of field oxide regions and active area regions for the n-channel access transistor; subjecting the patterned substrate to oxidizing conditions to form a pair of field oxide regions and an intervening n-channel access transistor active area therebetween, the field oxide regions having respective bird's beak regions extending into the n-channel access transistor active area, the n-channel access transistor active area defining a central region away from the bird's beak regions; and conducting a p-type V.sub.T ion implant into the n-channel active area using the field oxide bird's beak regions as an implant mask to concentrate the V.sub.T implant in the central region of the active area. A semiconductor device includes, a substrate; an n-type transistor on the substrate; and field oxide surrounding the transistor, the transistor having an active area including a central region and a peripheral region with respect to the field oxide, the transistor having a p-type V.sub.T ion implant which is more concentrated in the central region than in the peripheral region.
摘要翻译：一种形成具有n沟道存取晶体管的静态随机存取存储单元的半导体处理方法，包括提供体半导体衬底; 图案化衬底以定义用于n沟道存取晶体管的场氧化物区域和有源区域区域; 使图案化衬底经受氧化条件以形成一对场氧化物区域和其间的中间n沟道存取晶体管有源区域，所述场氧化物区域具有延伸到n沟道存取晶体管有源区域中的相应鸟嘴区域，通道存取晶体管有源区域限定远离鸟嘴区域的中心区域; 并且使用场氧化物鸟嘴区域作为植入物掩模将p型VT离子注入到n沟道有源区域中，以将VT植入物集中在有源区域的中心区域中。半导体器件包括：衬底; 衬底上的n型晶体管; 以及围绕晶体管的场氧化物，所述晶体管具有相对于场氧化物包括中心区域和外围区域的有源区域，所述晶体管具有p型VT离子注入，所述p型VT离子注入物在中心区域比在外围区域更集中地区。

88. 发明授权

US6083831A Semiconductor processing method of forming a contact pedestal, of forming a storage node of a capacitor 失效
标题翻译：形成接触基座的半导体处理方法，形成电容器的存储节点
公开(公告)号：US6083831A
公开(公告)日：2000-07-04
申请号：US622591
申请日：1996-03-26
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： H01L21/768 , H01L21/28 , H01L21/8242 , H01L27/108 , H01L21/44
CPC分类号： H01L27/10852
摘要： A semiconductor processing method of forming a contact pedestal includes, a) providing a node location to which electrical connection is to be made; b) providing insulating dielectric material over the node location; c) etching a contact opening into the insulating dielectric material over the node location to a degree insufficient to outwardly expose the node location, the contact opening having a base; d) providing a spacer layer over the insulating dielectric material to within the contact opening to a thickness which less than completely fills the contact opening; e) anisotropically etching the spacer layer to form a sidewall spacer within the contact opening; f) after forming the sidewall spacer, etching through the contact opening base to outwardly expose the node location; g) filling the contact opening to the node location with electrically conductive material; h) rendering the sidewall spacer electrically conductive; and i) etching the electrically conductive material to form an electrically conductive contact pedestal comprising the sidewall spacer, the pedestal having an outer surface which is substantially coplanar with opposing laterally adjacent electrically insulative surfaces. Also disclosed is integrated circuitry including contact pedestals. Also disclosed are methods of forming storage nodes of capacitors.
摘要翻译：形成接触基座的半导体处理方法包括：a）提供要进行电连接的节点位置; b）在节点位置上提供绝缘电介质材料; c）在所述节点位置上将接触开口蚀刻到所述绝缘介电材料中至不足以向外暴露所述节点位置的程度，所述接触开口具有基部; d）在绝缘电介质材料之上提供间隔层至接触开口内至少小于完全填充接触开口的厚度; e）各向异性地蚀刻间隔层以在接触开口内形成侧壁间隔物; f）在形成侧壁间隔物之后，通过接触开口基底蚀刻以向外暴露节点位置; g）用导电材料将接触开口填充到节点位置; h）使侧壁间隔物导电; 以及i）蚀刻所述导电材料以形成包括所述侧壁间隔物的导电接触基座，所述基座具有与相对的横向相邻的电绝缘表面基本上共面的外表面。还公开了包括接触基座的集成电路。还公开了形成电容器的存储节点的方法。

89. 再颁专利

USRE36644E Tapered via, structures made therewith, and methods of producing same 失效
标题翻译：锥形通孔，由其制成的结构及其制造方法
公开(公告)号：USRE36644E
公开(公告)日：2000-04-04
申请号：US745757
申请日：1996-11-08
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： H01L27/108 , H01L21/20
CPC分类号： H01L27/10817 , Y10S438/97
摘要： After formation of the storage poly in a stacked capacitor DRAM, the oxide 1 layer is partially etched to leave a thick oxide deposition in the area of the future bit line contact, upon which the cell poly is deposited, followed by oxide 2 and then a poly or nitride layer. A mask and etch process forms the bit line contact region through the cell poly, then a thin oxide is deposited and etched along with the oxide 1 to form cell poly spacers that don't close off the active area. The poly or nitride on top of the oxide 2 forms a hard mask that allows the spacers to travel down the side walls of the contact region creating a contact region that is wider at the top than bottom, facilitating metalization.
摘要翻译：在叠层电容器DRAM中形成储存多晶硅之后，氧化层1层被部分蚀刻，以便在将来的位线接触区域中留下厚的氧化物沉积，沉积电池多晶，然后是氧化物2，然后是聚或氮化物层。掩模和蚀刻工艺通过电池多孔形成位线接触区域，然后与氧化物1一起沉积和蚀刻薄氧化物，以形成不关闭有源区域的电池聚合间隔物。氧化物2顶部上的聚氮化物或氮化物形成硬掩模，其允许间隔物沿接触区域的侧壁向下移动，形成在顶部比底部更宽的接触区域，有利于金属化。

90. 再颁专利

USRE36518E Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device 失效
公开(公告)号：USRE36518E
公开(公告)日：2000-01-18
申请号：US504943
申请日：1995-07-20
申请人： Charles H. Dennison , Guy T. Blalock
发明人： Charles H. Dennison , Guy T. Blalock
IPC分类号： H01L21/28 , H01L21/60 , H01L21/768 , H01L23/485 , H01L23/522 , H01L21/44 , H01L21/48
CPC分类号： H01L21/76897 , H01L23/485 , H01L23/5226 , H01L2924/0002
摘要： A semiconducting processing method for making electrical contacts with an active area in sub-micron geometries includes: (a) providing a pair of conductive runners on a semiconductor wafer; (b) providing insulative spacers on the sides of the conductive runners wherein adjacent spacers are spaced a selected distance apart at a selected location on the wafer; (c) providing an active area between the conductive runners at the selected location; (d) providing an oxide layer over the active area and conductive runners; (e) providing a planarized nitride layer atop the oxide layer; (f) patterning and etching the nitride layer selectively relative to the oxide layer to define a first contact opening therethrough, wherein the first contact opening has an aperture width at the nitride layer upper surface which is greater than the selected distance between the insulative spacers; (g) etching the oxide layer within the first contact opening to expose the active area; (h) providing a polysilicon plug within the first contact opening over the exposed active areas; (i) providing an insulating layer over the nitride layer and the polysilicon plug; (j) patterning and etching the insulating layer to form a second contact opening to and exposing the polysilicon plug; and (k) providing a conductive layer over the insulating layer and into the second opening to electrically contact the polysilicon plug. A semiconductor device having buried landing plugs of approximately uniform height across the wafer is also described.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式