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1. 发明授权

US6117721A Semiconductor processing method of forming a static random access memory cell and static random access memory cell 失效
标题翻译：形成静态随机存取存储单元和静态随机存取存储单元的半导体处理方法
公开(公告)号：US6117721A
公开(公告)日：2000-09-12
申请号：US979406
申请日：1997-11-26
申请人： Charles H. Dennison , Ken Marr
发明人： Charles H. Dennison , Ken Marr
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/10
CPC分类号： H01L27/11 , H01L29/1033 , H01L2924/0002 , Y10S438/945
摘要： A semiconductor processing method of forming a static random access memory cell having an n-channel access transistor includes, providing a bulk semiconductor substrate; patterning the substrate for definition of field oxide regions and active area regions for the n-channel access transistor; subjecting the patterned substrate to oxidizing conditions to form a pair of field oxide regions and an intervening n-channel access transistor active area therebetween, the field oxide regions having respective bird's beak regions extending into the n-channel access transistor active area, the n-channel access transistor active area defining a central region away from the bird's beak regions; and conducting a p-type V.sub.T ion implant into the n-channel active area using the field oxide bird's beak regions as an implant mask to concentrate the V.sub.T implant in the central region of the active area. A semiconductor device includes, a substrate; an n-type transistor on the substrate; and field oxide surrounding the transistor, the transistor having an active area including a central region and a peripheral region with respect to the field oxide, the transistor having a p-type V.sub.T ion implant which is more concentrated in the central region than in the peripheral region.
摘要翻译：一种形成具有n沟道存取晶体管的静态随机存取存储单元的半导体处理方法，包括提供体半导体衬底; 图案化衬底以定义用于n沟道存取晶体管的场氧化物区域和有源区域区域; 使图案化衬底经受氧化条件以形成一对场氧化物区域和其间的中间n沟道存取晶体管有源区域，所述场氧化物区域具有延伸到n沟道存取晶体管有源区域中的相应鸟嘴区域，通道存取晶体管有源区域限定远离鸟嘴区域的中心区域; 并且使用场氧化物鸟嘴区域作为植入物掩模将p型VT离子注入到n沟道有源区域中，以将VT植入物集中在有源区域的中心区域中。半导体器件包括：衬底; 衬底上的n型晶体管; 以及围绕晶体管的场氧化物，所述晶体管具有相对于场氧化物包括中心区域和外围区域的有源区域，所述晶体管具有p型VT离子注入，所述p型VT离子注入物在中心区域比在外围区域更集中地区。

2. 发明授权

US5650350A Semiconductor processing method of forming a static random access memory cell and static random access memory cell 失效
标题翻译：形成静态随机存取存储单元和静态随机存取存储单元的半导体处理方法
公开(公告)号：US5650350A
公开(公告)日：1997-07-22
申请号：US514106
申请日：1995-08-11
申请人： Charles H. Dennison , Ken Marr
发明人： Charles H. Dennison , Ken Marr
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/10
CPC分类号： H01L27/11 , H01L29/1033 , H01L2924/0002 , Y10S438/945
摘要： A semiconductor processing method of forming a static random access memory cell having an n-channel access transistor includes, providing a bulk semiconductor substrate; patterning the substrate for definition of field oxide regions and active area regions for the n-channel access transistor; subjecting the patterned substrate to oxidizing conditions to form a pair of field oxide regions and an intervening n-channel access transistor active area therebetween, the field oxide regions having respective bird's beak regions extending into the n-channel access transistor active area, the n-channel access transistor active area defining a central region away from the bird's beak regions; and conducting a p-type V.sub.T ion implant into the n-channel active area using the field oxide bird's beak region as an implant mask to concentrate the V.sub.T implant in the central region of the active area. A semiconductor device includes, a substrate; an n-type transistor on the substrate; and field oxide surrounding the transistor, the transistor having an active area including a central region and a peripheral region with respect to the field oxide, the transistor having a p-type V.sub.T ion implant which is more concentrated in the central region than in the peripheral region.
摘要翻译：一种形成具有n沟道存取晶体管的静态随机存取存储单元的半导体处理方法，包括提供体半导体衬底; 图案化衬底以定义用于n沟道存取晶体管的场氧化物区域和有源区域区域; 使图案化衬底经受氧化条件以形成一对场氧化物区域和其间的中间n沟道存取晶体管有源区域，所述场氧化物区域具有延伸到n沟道存取晶体管有源区域中的相应鸟嘴区域，通道存取晶体管有源区域限定远离鸟嘴区域的中心区域; 并且使用场氧化物鸟嘴区域作为植入物掩模将p型VT离子注入到n沟道有源区域中，以将VT植入物集中在有源区域的中心区域中。半导体器件包括：衬底; 衬底上的n型晶体管; 以及围绕晶体管的场氧化物，所述晶体管具有相对于场氧化物包括中心区域和外围区域的有源区域，所述晶体管具有p型VT离子注入，所述p型VT离子注入物在中心区域比在外围区域更集中地区。

3. 发明授权

US5929495A Semiconductor processing method of forming a static random access memory cell and static random access memory cell 失效
公开(公告)号：US5929495A
公开(公告)日：1999-07-27
申请号：US28300
申请日：1998-02-24
申请人： Charles H. Dennison , Ken Marr
发明人： Charles H. Dennison , Ken Marr
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/10 , H01L23/58
CPC分类号： H01L27/11 , H01L29/1033 , H01L2924/0002 , Y10S438/945
摘要： A semiconductor processing method of forming a static random access memory cell having an n-channel access transistor includes, providing a bulk semiconductor substrate; patterning the substrate for definition of field oxide regions and active area regions for the n-channel access transistor; subjecting the patterned substrate to oxidizing conditions to form a pair of field oxide regions and an intervening n-channel access transistor active area therebetween, the field oxide regions having respective bird's beak regions extending into the n-channel access transistor active area, the n-channel access transistor active area defining a central region away from the bird's beak regions; and conducting a p-type V.sub.T ion implant into the n-channel active area using the field oxide bird's beak regions as an implant mask to concentrate the V.sub.T implant in the central region of the active area. A semiconductor device includes, a substrate; an n-type transistor on the substrate; and field oxide surrounding the transistor, the transistor having an active area including a central region and a peripheral region with respect to the field oxide, the transistor having a p-type V.sub.T ion implant which is more concentrated in the central region than in the peripheral region.

4. 发明授权

US5751046A Semiconductor device with V.sub.T implant 失效
标题翻译：具有VT植入物的半导体器件
公开(公告)号：US5751046A
公开(公告)日：1998-05-12
申请号：US850950
申请日：1997-05-05
申请人： Charles H. Dennison , Ken Marr
发明人： Charles H. Dennison , Ken Marr
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/10 , H01L23/58
CPC分类号： H01L27/11 , H01L29/1033 , H01L2924/0002 , Y10S438/945
摘要： A semiconductor processing method of forming a static random access memory cell having an n-channel access transistor includes providing a bulk semiconductor substrate; patterning the substrate for definition of field oxide regions and active area regions for the n-channel access transistor; subjecting the patterned substrate to oxidizing conditions to form a pair of field oxide regions and an intervening n-channel access transistor active area therebetween, the field oxide regions having respective bird's beak regions extending into the n-channel access transistor active area, the n-channel access transistor active area defining a central region away from the bird's beak regions; and conducting a p-type V.sub.T ion implant into the n-channel active area using the field oxide bird's beak regions as an implant mask to concentrate the V.sub.T implant in the central region of the active area. A semiconductor device includes, a substrate; an n-type transistor on the substrate; and field oxide surrounding the transistor, the transistor having an active area including a central region and a peripheral region with respect to the field oxide, the transistor having a p-type V.sub.T ion implant which is more concentrated in the central region than in the peripheral region.
摘要翻译：一种形成具有n沟道存取晶体管的静态随机存取存储单元的半导体处理方法，包括提供体半导体衬底; 图案化衬底以定义用于n沟道存取晶体管的场氧化物区域和有源区域区域; 使图案化衬底经受氧化条件以形成一对场氧化物区域和其间的中间n沟道存取晶体管有源区域，所述场氧化物区域具有延伸到n沟道存取晶体管有源区域中的相应鸟嘴区域，通道存取晶体管有源区域限定远离鸟嘴区域的中心区域; 并且使用场氧化物鸟嘴区域作为植入物掩模将p型VT离子注入到n沟道有源区域中，以将VT植入物集中在有源区域的中心区域中。半导体器件包括：衬底; 衬底上的n型晶体管; 以及围绕晶体管的场氧化物，所述晶体管具有相对于场氧化物包括中心区域和外围区域的有源区域，所述晶体管具有p型VT离子注入，所述p型VT离子注入物在中心区域比在外围区域更集中地区。

5. 发明授权

US5739056A Semiconductor processing method of forming a static random access memory cell and static random access memory cell 失效
公开(公告)号：US5739056A
公开(公告)日：1998-04-14
申请号：US800553
申请日：1997-02-18
申请人： Charles H. Dennison , Ken Marr
发明人： Charles H. Dennison , Ken Marr
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/10
CPC分类号： H01L27/11 , H01L29/1033 , H01L2924/0002 , Y10S438/945
摘要： A semiconductor processing method of forming a static random access memory cell having an n-channel access transistor includes, providing a bulk semiconductor substrate; patterning the substrate for definition of field oxide regions and active area regions for the n-channel access transistor; subjecting the patterned substrate to oxidizing conditions to form a pair of field oxide regions and an intervening n-channel access transistor active area therebetween, the field oxide regions having respective bird's beak regions extending into the n-channel access transistor active area, the n-channel access transistor active area defining a central region away from the bird's beak regions; and conducting a p-type V.sub.T ion implant into the n-channel active area using the field oxide bird's beak regions as an implant mask to concentrate the V.sub.T implant in the central region of the active area. A semiconductor device includes, a substrate; an n-type transistor on the substrate; and field oxide surrounding the transistor, the transistor having an active area including a central region and a peripheral region with respect to the field oxide, the transistor having a p-type V.sub.T ion implant which is more concentrated in the central region than in the peripheral region.

6. 发明授权

US08462545B2 Semiconductor phase change memory using multiple phase change layers 有权
公开(公告)号：US08462545B2
公开(公告)日：2013-06-11
申请号：US13526686
申请日：2012-06-19
申请人： Charles H. Dennison , Stephen J. Hudgens
发明人： Charles H. Dennison , Stephen J. Hudgens
IPC分类号： G11C11/00
CPC分类号： H01L45/065 , G11C13/0004 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , Y10S977/754
摘要： In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.

7. 发明申请

US20120081956A1 SEMICONDUCTOR PHAST CHANGE MEMORY USING MULTIPLE PHASE CHANGE LAYERS 有权
标题翻译：使用多个相位变化层的半导体相位变化记忆
公开(公告)号：US20120081956A1
公开(公告)日：2012-04-05
申请号：US13315374
申请日：2011-12-09
申请人： Charles H. Dennison , Stephen J. Hudgens
发明人： Charles H. Dennison , Stephen J. Hudgens
IPC分类号： G11C11/00
CPC分类号： H01L45/065 , G11C13/0004 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , Y10S977/754
摘要： In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.
摘要翻译：根据一些实施例，可以形成相变存储器，其中减少了编程体积相变材料之外的区域中的热导率。这可能会降低所得相变存储器的功耗。功耗的降低可以通过在编程体积之外形成很少或不混合的相变材料的不同层来实现。例如，在一个实施例中，可以在两个不同的相变层之间保持扩散阻挡层。在另一个实施方案中，可以使用面心立方硫属元素化合物结构。

8. 发明申请

US20100200829A1 Semiconductor Phase Change Memory Using Multiple Phase Change Layers 有权
标题翻译：使用多相变层的半导体相变存储器
公开(公告)号：US20100200829A1
公开(公告)日：2010-08-12
申请号：US12764157
申请日：2010-04-21
申请人： Charles H. Dennison , Stephen J. Hudgens
发明人： Charles H. Dennison , Stephen J. Hudgens
IPC分类号： H01L45/00
CPC分类号： H01L45/065 , G11C13/0004 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , Y10S977/754
摘要： In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.
摘要翻译：根据一些实施例，可以形成相变存储器，其中减少了编程体积相变材料之外的区域中的热导率。这可能会降低所得相变存储器的功耗。功耗的降低可以通过在编程体积之外形成很少或不混合的不同的相变材料层来实现。例如，在一个实施例中，可以在两个不同的相变层之间保持扩散阻挡层。在另一个实施方案中，可以使用面心立方硫属元素化合物结构。

9. 发明申请

US20080177943A1 Method and system for using dynamic random access memory as cache memory 有权
标题翻译：使用动态随机存取存储器作为高速缓冲存储器的方法和系统
公开(公告)号：US20080177943A1
公开(公告)日：2008-07-24
申请号：US12069812
申请日：2008-02-12
申请人： Brent Keeth , Brian M. Shirley , Charles H. Dennison , Kevin J. Ryan
发明人： Brent Keeth , Brian M. Shirley , Charles H. Dennison , Kevin J. Ryan
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/0846 , G06F12/0897 , G11C7/1006 , G11C7/1042 , G11C11/406 , G11C11/409 , G11C15/043
摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.
摘要翻译：高速缓冲存储器系统和方法包括具有多个存储体的DRAM，并且它们还包括两个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。在操作中，从DRAM的存储体读出的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。在从SRAM到DRAM的数据传输期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体或其它SRAM中。

10. 发明授权

US07390691B2 Increasing phase change memory column landing margin 有权
标题翻译：增加相变记忆柱着陆边界
公开(公告)号：US07390691B2
公开(公告)日：2008-06-24
申请号：US11262250
申请日：2005-10-28
申请人： Charles H. Dennison , Ilya V. Karpov
发明人： Charles H. Dennison , Ilya V. Karpov
IPC分类号： H01L21/00 , H01L21/336
CPC分类号： H01L45/06 , H01L27/2463 , H01L45/1233 , H01L45/1253 , H01L45/126 , H01L45/1675
摘要： A phase change memory with higher column landing margin may be formed. In one approach, the column landing margin may be increased by increasing the height of an electrode. For example, the electrode being made of two disparate materials, one of which includes nitride and the other of which does not. In another approach, a hard mask is used which is of substantially the same material as an overlying and surrounding insulator. The hard mask and an underlying phase change material are protected by a sidewall spacer of a different material than the hard mask. If the hard mask and the insulator have substantially the same etch characteristics, the hard mask may be removed while maintaining the protective character of the sidewall spacer.
摘要翻译：可以形成具有较高列着陆边缘的相变存储器。在一种方法中，可以通过增加电极的高度来增加列着色边缘。例如，电极由两种不同的材料制成，其中之一包括氮化物，另一个不包括氮化物。在另一种方法中，使用与覆盖和围绕的绝缘体基本上相同的材料的硬掩模。硬掩模和下面的相变材料由与硬掩模不同的材料的侧壁间隔物保护。如果硬掩模和绝缘体具有基本相同的蚀刻特性，则可以去除硬掩模，同时保持侧壁间隔物的保护特性。

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