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1. 发明授权

US6004854A Method of forming CMOS integrated circuitry 失效
公开(公告)号：US6004854A
公开(公告)日：1999-12-21
申请号：US97880
申请日：1998-06-15
申请人： Charles H. Dennison , Mark Helm
发明人： Charles H. Dennison , Mark Helm
IPC分类号： H01L21/8238 , H01L27/092 , H01L27/105 , H01L21/336
CPC分类号： H01L27/105 , H01L21/823807 , H01L27/0922
摘要： A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor; b) masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and c) in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration at a second depth within both the PMOS substrate area and the NMOS substrate area, the first energy level and the first depth being greater than the second energy level and the second depth, respectively. Methods of forming memory and other CMOS integrated circuitry are also disclosed involving optimization of different NMOS transistors.

2. 发明授权

US6124616A Integrated circuitry comprising halo regions and LDD regions 失效
标题翻译：包含晕圈区和LDD区的集成电路
公开(公告)号：US6124616A
公开(公告)日：2000-09-26
申请号：US49282
申请日：1998-03-26
申请人： Charles H. Dennison , Mark Helm
发明人： Charles H. Dennison , Mark Helm
IPC分类号： H01L21/8238 , H01L27/092 , H01L27/105 , H01L29/76
CPC分类号： H01L21/823807 , H01L27/0922 , H01L27/105
摘要： A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor; b) masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and c) in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration at a second depth within both the PMOS substrate area and the NMOS substrate area, the first energy level and the first depth being greater than the second energy level and the second depth, respectively. Methods of forming memory and other CMOS integrated circuitry are also disclosed involving optimization of different NMOS transistors.
摘要翻译：一种形成CMOS集成电路的方法包括：a）在半导体衬底上提供一系列栅极线，第一栅极线相对于衬底的区域定位以形成NMOS晶体管，第二栅极线相对于用于形成PMOS晶体管的衬底的区域; b）在将p型卤素离子注入进入与第一栅极线相邻的NMOS衬底区域的同时掩蔽第二栅极线和PMOS衬底区域，p型卤素离子注入以第一能级进行，以提供p 在NMOS衬底区域内的第一深度处的第一杂质浓度; 和c）在共同的步骤中，将磷离子注入到与第一和第二栅极线相邻的NMOS衬底区域和PMOS衬底区域中，分别形成NMOS LDD区和PMOS n型晕区，磷植入在第二能级进行，以在PMOS衬底区域和NMOS衬底区域内的第二深度处提供n型第二杂质浓度，第一能级和第一深度大于第二能级，第二级深度。还公开了形成存储器和其它CMOS集成电路的方法，其涉及不同NMOS晶体管的优化。

3. 发明授权

US06358787B2 Method of forming CMOS integrated circuitry 有权
标题翻译：形成CMOS集成电路的方法
公开(公告)号：US06358787B2
公开(公告)日：2002-03-19
申请号：US09832447
申请日：2001-04-10
申请人： Charles H. Dennison , Mark Helm
发明人： Charles H. Dennison , Mark Helm
IPC分类号： H01L218238
CPC分类号： H01L27/105 , H01L21/823807 , H01L27/0922
摘要： A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor; b) masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and c) in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration at a second depth within both the PMOS substrate area and the NMOS substrate area, the first energy level and the first depth being greater than the second energy level and the second depth, respectively. Methods of forming memory and other CMOS integrated circuitry are also disclosed involving optimization of different NMOS transistors.
摘要翻译：一种形成CMOS集成电路的方法包括：a）在半导体衬底上提供一系列栅极线，第一栅极线相对于衬底的区域定位以形成NMOS晶体管，第二栅极线相对于用于形成PMOS晶体管的衬底的区域; b）在将p型卤素离子注入进入与第一栅极线相邻的NMOS衬底区域的同时掩蔽第二栅极线和PMOS衬底区域，p型卤素离子注入以第一能级进行，以提供p 在NMOS衬底区域内的第一深度处的第一杂质浓度; 和c）在共同的步骤中，将磷离子注入到与第一和第二栅极线相邻的NMOS衬底区域和PMOS衬底区域中，分别形成NMOS LDD区和PMOS n型晕区，磷植入在第二能级进行，以在PMOS衬底区域和NMOS衬底区域内的第二深度处提供n型第二杂质浓度，第一能级和第一深度大于第二能级，第二级深度。还公开了形成存储器和其它CMOS集成电路的方法，其涉及不同NMOS晶体管的优化。

4. 发明授权

US5683927A Method of forming CMOS integrated circuitry 失效
标题翻译：形成CMOS集成电路的方法
公开(公告)号：US5683927A
公开(公告)日：1997-11-04
申请号：US631249
申请日：1996-04-12
申请人： Charles H. Dennison , Mark Helm
发明人： Charles H. Dennison , Mark Helm
IPC分类号： H01L21/8238 , H01L27/092 , H01L27/105 , H01L21/70
CPC分类号： H01L21/823807 , H01L27/0922 , H01L27/105
摘要： A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor; b) masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and c) in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration at a second depth within both the PMOS substrate area and the NMOS substrate area, the first energy level and the first depth being greater than the second energy level and the second depth, respectively. Methods of forming memory and other CMOS integrated circuitry are also disclosed involving optimization of different NMOS transistors.
摘要翻译：一种形成CMOS集成电路的方法包括：a）在半导体衬底上提供一系列栅极线，第一栅极线相对于衬底的区域定位以形成NMOS晶体管，第二栅极线相对于用于形成PMOS晶体管的衬底的区域; b）在将p型卤素离子注入进入与第一栅极线相邻的NMOS衬底区域的同时掩蔽第二栅极线和PMOS衬底区域，p型卤素离子注入以第一能级进行，以提供p 在NMOS衬底区域内的第一深度处的第一杂质浓度; 和c）在共同的步骤中，将磷离子注入到与第一和第二栅极线相邻的NMOS衬底区域和PMOS衬底区域中，分别形成NMOS LDD区和PMOS n型晕区，磷植入在第二能级进行，以在PMOS衬底区域和NMOS衬底区域内的第二深度处提供n型第二杂质浓度，第一能级和第一深度大于第二能级，第二级深度。还公开了形成存储器和其它CMOS集成电路的方法，其涉及不同NMOS晶体管的优化。

5. 发明授权

US5534449A Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry 失效
标题翻译：形成互补金属氧化物半导体（CMOS）集成电路的方法
公开(公告)号：US5534449A
公开(公告)日：1996-07-09
申请号：US503419
申请日：1995-07-17
申请人： Charles H. Dennison , Mark Helm
发明人： Charles H. Dennison , Mark Helm
IPC分类号： H01L21/8238 , H01L27/092 , H01L27/105 , H01L21/265
CPC分类号： H01L21/823807 , H01L27/0922 , H01L27/105
摘要： A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor; b) masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and c) in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration at a second depth within both the PMOS substrate area and the NMOS substrate area, the first energy level and the first depth being greater than the second energy level and the second depth, respectively. Methods of forming memory and other CMOS integrated circuitry are also disclosed involving optimization of different NMOS transistors.
摘要翻译：一种形成CMOS集成电路的方法包括：a）在半导体衬底上提供一系列栅极线，第一栅极线相对于衬底的区域定位以形成NMOS晶体管，第二栅极线相对于用于形成PMOS晶体管的衬底的区域; b）在将p型卤素离子注入进入与第一栅极线相邻的NMOS衬底区域的同时掩蔽第二栅极线和PMOS衬底区域，p型卤素离子注入以第一能级进行，以提供p 在NMOS衬底区域内的第一深度处的第一杂质浓度; 和c）在共同的步骤中，将磷离子注入到与第一和第二栅极线相邻的NMOS衬底区域和PMOS衬底区域中，分别形成NMOS LDD区和PMOS n型晕区，磷植入在第二能级进行，以在PMOS衬底区域和NMOS衬底区域内的第二深度处提供n型第二杂质浓度，第一能级和第一深度大于第二能级，第二级深度。还公开了形成存储器和其它CMOS集成电路的方法，其涉及不同NMOS晶体管的优化。

6. 发明授权

US6074924A Method of forming CMOS integrated circuitry 有权
标题翻译：形成CMOS集成电路的方法
公开(公告)号：US6074924A
公开(公告)日：2000-06-13
申请号：US404173
申请日：1999-09-24
申请人： Charles H. Dennison , Mark Helm
发明人： Charles H. Dennison , Mark Helm
IPC分类号： H01L21/8238 , H01L27/092 , H01L27/105 , H01L21/336
CPC分类号： H01L27/105 , H01L21/823807 , H01L27/0922
摘要： A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor; b) masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and c) in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the fist and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration at a second depth within both the PMOS substrate area and the NMOS substrate area, the first energy level and the first depth being greater than the second energy level and the second depth, respectively. Methods of forming memory and other CMOS integrated circuitry are also disclosed involving optimization of different NMOS transistors.
摘要翻译：一种形成CMOS集成电路的方法包括：a）在半导体衬底上提供一系列栅极线，第一栅极线相对于衬底的区域定位以形成NMOS晶体管，第二栅极线相对于用于形成PMOS晶体管的衬底的区域; b）在将p型卤素离子注入进入与第一栅极线相邻的NMOS衬底区域的同时掩蔽第二栅极线和PMOS衬底区域，p型卤素离子注入以第一能级进行，以提供p 在NMOS衬底区域内的第一深度处的第一杂质浓度; 和c）在一个共同的步骤中，将磷离子全面地注入到与第一和第二栅极线相邻的NMOS衬底区域和PMOS衬底区域中，分别形成NMOS LDD区和PMOS n型晕区，磷植入在第二能级进行，以在PMOS衬底区域和NMOS衬底区域内的第二深度处提供n型第二杂质浓度，第一能级和第一深度大于第二能级，第二级深度。还公开了形成存储器和其它CMOS集成电路的方法，其涉及不同NMOS晶体管的优化。

7. 发明授权

US06261888B1 Method of forming CMOS integrated circuitry 有权
标题翻译：形成CMOS集成电路的方法
公开(公告)号：US06261888B1
公开(公告)日：2001-07-17
申请号：US09468281
申请日：1999-12-20
申请人： Charles H. Dennison , Mark Helm
发明人： Charles H. Dennison , Mark Helm
IPC分类号： H01L218238
CPC分类号： H01L27/105 , H01L21/823807 , H01L27/0922
摘要： A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor; b) masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and c) in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration at a second depth within both the PMOS substrate area and the NMOS substrate area, the first energy level and the first depth being greater than the second energy level and the second depth, respectively. Methods of forming memory and other CMOS integrated circuitry are also disclosed involving optimization of different NMOS transistors.
摘要翻译：一种形成CMOS集成电路的方法包括：a）在半导体衬底上提供一系列栅极线，第一栅极线相对于衬底的区域定位以形成NMOS晶体管，第二栅极线相对于用于形成PMOS晶体管的衬底的区域; b）在将p型卤素离子注入进入与第一栅极线相邻的NMOS衬底区域的同时掩蔽第二栅极线和PMOS衬底区域，p型卤素离子注入以第一能级进行，以提供p 在NMOS衬底区域内的第一深度处的第一杂质浓度; 和c）在共同的步骤中，将磷离子注入到与第一和第二栅极线相邻的NMOS衬底区域和PMOS衬底区域中，分别形成NMOS LDD区和PMOS n型晕区，磷植入在第二能级进行，以在PMOS衬底区域和NMOS衬底区域内的第二深度处提供n型第二杂质浓度，第一能级和第一深度大于第二能级，第二级深度。还公开了形成存储器和其它CMOS集成电路的方法，其涉及不同NMOS晶体管的优化。

8. 发明授权

US5776806A Method of forming CMOS integrated circuitry having halo regions 失效
标题翻译：形成具有晕圈的CMOS集成电路的方法
公开(公告)号：US5776806A
公开(公告)日：1998-07-07
申请号：US866887
申请日：1997-05-30
申请人： Charles H. Dennison , Mark Helm
发明人： Charles H. Dennison , Mark Helm
IPC分类号： H01L21/8238 , H01L27/092 , H01L27/105
CPC分类号： H01L21/823807 , H01L27/0922 , H01L27/105
摘要： A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor; b) masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and c) in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration at a second depth within both the PMOS substrate area and the NMOS substrate area, the first energy level and the first depth being greater than the second energy level and the second depth, respectively. Methods of forming memory and other CMOS integrated circuitry are also disclosed involving optimization of different NMOS transistors.
摘要翻译：一种形成CMOS集成电路的方法包括：a）在半导体衬底上提供一系列栅极线，第一栅极线相对于衬底的区域定位以形成NMOS晶体管，第二栅极线相对于用于形成PMOS晶体管的衬底的区域; b）在将p型卤素离子注入进入与第一栅极线相邻的NMOS衬底区域的同时掩蔽第二栅极线和PMOS衬底区域，p型卤素离子注入以第一能级进行，以提供p 在NMOS衬底区域内的第一深度处的第一杂质浓度; 和c）在共同的步骤中，将磷离子注入到与第一和第二栅极线相邻的NMOS衬底区域和PMOS衬底区域中，分别形成NMOS LDD区和PMOS n型晕区，磷植入在第二能级进行，以在PMOS衬底区域和NMOS衬底区域内的第二深度处提供n型第二杂质浓度，第一能级和第一深度大于第二能级，第二级深度。还公开了形成存储器和其它CMOS集成电路的方法，其涉及不同NMOS晶体管的优化。

9. 发明授权

US5747855A CMOS integrated circuitry with Halo and LDD regions 失效
标题翻译：具有Halo和LDD区域的CMOS集成电路
公开(公告)号：US5747855A
公开(公告)日：1998-05-05
申请号：US782248
申请日：1997-01-14
申请人： Charles H. Dennison , Mark Helm
发明人： Charles H. Dennison , Mark Helm
IPC分类号： H01L21/8238 , H01L27/092 , H01L27/105 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L21/823807 , H01L27/0922 , H01L27/105
摘要： A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor; b) masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and c) in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration at a second depth within both the PMOS substrate area and the NMOS substrate area, the first energy level and the first depth being greater than the second energy level and the second depth, respectively. Methods of forming memory and other CMOS integrated circuitry are also disclosed involving optimization of different NMOS transistors.
摘要翻译：一种形成CMOS集成电路的方法包括：a）在半导体衬底上提供一系列栅极线，第一栅极线相对于衬底的区域定位以形成NMOS晶体管，第二栅极线相对于用于形成PMOS晶体管的衬底的区域; b）在将p型卤素离子注入进入与第一栅极线相邻的NMOS衬底区域的同时掩蔽第二栅极线和PMOS衬底区域，p型卤素离子注入以第一能级进行，以提供p 在NMOS衬底区域内的第一深度处的第一杂质浓度; 和c）在共同的步骤中，将磷离子注入到与第一和第二栅极线相邻的NMOS衬底区域和PMOS衬底区域中，分别形成NMOS LDD区和PMOS n型晕区，磷植入在第二能级进行，以在PMOS衬底区域和NMOS衬底区域内的第二深度处提供n型第二杂质浓度，第一能级和第一深度大于第二能级，第二级深度。还公开了形成存储器和其它CMOS集成电路的方法，其涉及不同NMOS晶体管的优化。

10. 发明授权

US08462545B2 Semiconductor phase change memory using multiple phase change layers 有权
公开(公告)号：US08462545B2
公开(公告)日：2013-06-11
申请号：US13526686
申请日：2012-06-19
申请人： Charles H. Dennison , Stephen J. Hudgens
发明人： Charles H. Dennison , Stephen J. Hudgens
IPC分类号： G11C11/00
CPC分类号： H01L45/065 , G11C13/0004 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , Y10S977/754
摘要： In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.

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