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81. 发明授权

US07579284B2 Etching solution, method of forming a pattern using the same, method of manufacturing a multiple gate oxide layer using the same and method of manufacturing a flash memory device using the same 失效
标题翻译：蚀刻溶液，使用其形成图案的方法，使用该方法制造多栅极氧化物层的方法以及使用其制造闪存器件的方法
公开(公告)号：US07579284B2
公开(公告)日：2009-08-25
申请号：US11482773
申请日：2006-07-10
申请人： Byoung-Moon Yoon , Ji-Hong Kim , Yong-Sun Ko , Kyung-Hyun Kim
发明人： Byoung-Moon Yoon , Ji-Hong Kim , Yong-Sun Ko , Kyung-Hyun Kim
IPC分类号： H01L21/311
CPC分类号： C09K13/04 , H01L21/32134
摘要： Example embodiments of the present invention relate to an etching solution, a method of forming a pattern using the same, a method of manufacturing a multiple gate oxide layer using the same and a method of manufacturing a flash memory device using the same. Other example embodiments of the present invention relate to an etching solution having an etching selectivity between a polysilicon layer and an oxide layer, a method of forming a pattern using an etching solution using the same, a method of manufacturing a multiple gate oxide layer using the same, and a method of manufacturing a flash memory device using the same. An etching solution including hydrogen peroxide (H2O2) and ammonium hydroxide (NH4OH) by a volume ratio of about 1:2 to about 1:10 mixed in water. In a method of forming a pattern and methods of manufacturing a multiple gate oxide layer and a flash memory device, a polysilicon layer may be formed on a substrate. An insulation layer pattern including an opening exposing the polysilicon layer may be formed on the polysilicon layer. The polysilicon layer exposed by the insulation layer pattern may be etched using the etching solution. A polysilicon layer pattern may be formed on the substrate using the etching solution.
摘要翻译：本发明的示例性实施例涉及一种蚀刻溶液，使用该方法形成图案的方法，使用该蚀刻溶液的多栅极氧化物层的制造方法以及使用其制造闪存器件的方法。本发明的其它示例性实施例涉及在多晶硅层和氧化物层之间具有蚀刻选择性的蚀刻溶液，使用其使用蚀刻溶液形成图案的方法，使用该栅极氧化物层的方法以及使用其制造闪存器件的方法。包含在水中混合的体积比为约1:2至约1:10的过氧化氢（H 2 O 2）和氢氧化铵（NH 4 OH）的蚀刻溶液。在形成图案的方法和制造多栅极氧化物层和闪存器件的方法中，可以在衬底上形成多晶硅层。可以在多晶硅层上形成包括露出多晶硅层的开口的绝缘层图案。可以使用蚀刻溶液蚀刻由绝缘层图案暴露的多晶硅层。可以使用蚀刻溶液在衬底上形成多晶硅层图案。

82. 发明申请

US20090175328A1 DECISION FEEDBACK EQUALIZER (DFE) CIRCUITS FOR USE IN A SEMICONDUCTOR MEMORY DEVICE AND INITIALIZING METHOD THEREOF 有权
标题翻译：用于半导体存储器件的决策反馈均衡器（DFE）电路及其初始化方法
公开(公告)号：US20090175328A1
公开(公告)日：2009-07-09
申请号：US12261814
申请日：2008-10-30
申请人： Kyung-Hyun KIM , Yongsam MOON
发明人： Kyung-Hyun KIM , Yongsam MOON
IPC分类号： H03H7/30
CPC分类号： G11C7/20 , G11C7/02 , G11C7/1006 , G11C7/1078 , G11C7/1084 , G11C27/02
摘要： A DFE circuit for use in a semiconductor memory device and an initializing method thereof. In the method of initializing a DFE circuit used in a semiconductor memory device having a discontinuous data transmission, the DFE circuit may be used for changing a sampling reference level in response to a level of previous data and sampling transmission data. The method includes terminating a data channel having a transmission of the transmission data at a predefined termination level, and controlling a sampling start time point of the transmission data as a time point preceding a transmission time point of the transmission data by a predefined time. Further, an initialization may be performed of the previous data on the basis of initialization data obtained through a pre-sampling of the data channel at a sampling start time point of the transmission data, thereby obtaining an initialization of the DFE circuit and compensating for a feedback delay.
摘要翻译：一种用于半导体存储器件的DFE电路及其初始化方法。在具有不连续数据传输的半导体存储器件中使用的DFE电路的初始化方法中，DFE电路可以用于响应于先前数据的电平和采样发送数据来改变采样基准电平。该方法包括终止在预定的终止级别具有传输数据的传输的数据信道，并且将传输数据的采样开始时间点控制在传输数据的传输时间点之前的时间点预定的时间。此外，可以基于在发送数据的采样开始时间点通过数据信道的预采样获得的初始化数据来执行先前数据的初始化，从而获得DFE电路的初始化并补偿反馈延迟。

83. 发明申请

US20090001401A1 Semiconductor Light Emitting Diode 有权
标题翻译：半导体发光二极管
公开(公告)号：US20090001401A1
公开(公告)日：2009-01-01
申请号：US10572486
申请日：2005-08-05
申请人： Nae Man Park , Kyung Hyun Kim , Tae Youb Kim , Gun Yong Sung
发明人： Nae Man Park , Kyung Hyun Kim , Tae Youb Kim , Gun Yong Sung
IPC分类号： H01L33/00
CPC分类号： H01L33/38
摘要： Provided is a semiconductor light emitting diode, in which a plurality of upper electrodes is formed on a surface of an upper doping layer or an emission layer and at least one lower electrode is formed on a surface of a lower doping layer or a substrate in a silicon-based light emitting diode or a nitride-based light emitting diode to enhance a spreading characteristic of current applied to the electrodes, thereby maximizing an emitting area of the emission layer and inducing an emission having a uniform intensity on an entire surface of the emission layer to further enhance the luminous efficiency of the light emitting diode.
摘要翻译：提供一种半导体发光二极管，其中在上掺杂层或发光层的表面上形成多个上电极，并且在下掺杂层或基板的表面上形成至少一个下电极硅基发光二极管或氮化物基发光二极管，以增强施加到电极的电流的扩展特性，从而使发射层的发射面积最大化并且在发射的整个表面上诱发具有均匀强度的发射层以进一步提高发光二极管的发光效率。

84. 发明申请

US20080042240A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080042240A1
公开(公告)日：2008-02-21
申请号：US11976251
申请日：2007-10-23
申请人： Yeol Jon , Chung-Ki Min , Yong-Sun Ko , Kyung-Hyun Kim
发明人： Yeol Jon , Chung-Ki Min , Yong-Sun Ko , Kyung-Hyun Kim
IPC分类号： H01L29/00
CPC分类号： H01L27/10894 , H01L27/10852
摘要： Provided is a semiconductor device including a vertically oriented capacitor extending above the substrate surface and a method of manufacturing such devices in which cell, peripheral and boundary areas between the cell and peripheral areas are defined on a semiconductor substrate. Capacitors are formed in the cell area, a mold pattern is provided in the peripheral areas and an elongated dummy pattern is provided in the boundary areas. The dummy pattern includes a boundary opening in which a thin layer is formed on the elongated inner sidewalls and on the exposed portion of the substrate during formation of the lower electrode. A mold pattern and lower electrode structures having substantially the same height are then formed area so that subsequent insulation interlayer(s) exhibit a generally planar surface, i.e., have no significant step difference between the cell areas and the peripheral areas.
摘要翻译：提供一种包括在基板表面上方延伸的垂直取向的电容器的半导体器件以及制造这样的器件的方法，其中在半导体衬底上限定了单元和外围区域之间的单元，外围和边界区域。电容器形成在电池区域中，在外围区域设置模具图案，并且在边界区域中设置细长的虚拟图案。虚拟图案包括边界开口，其中在形成下电极期间在细长的内侧壁上和在基板的暴露部分上形成薄层。然后形成具有基本上相同高度的模具图案和下部电极结构，使得随后的绝缘中间层呈现大致平坦的表面，即在电池区域和外围区域之间没有显着的步进差异。

85. 发明申请

US20070171738A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20070171738A1
公开(公告)日：2007-07-26
申请号：US11499156
申请日：2006-08-04
申请人： Kyung-Hyun Kim , Jae-Woong Lee
发明人： Kyung-Hyun Kim , Jae-Woong Lee
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/46 , G11C29/14
摘要： A semiconductor memory device includes a control signal generator for combining command signals applied from an external portion to generate a test signal; a set/reset signal generator for receiving a mode setting signal applied from an external portion in response to the test signal and generating a first set/reset signal when the mode setting signal is a signal that designates an individual set/reset; a test logic portion for storing and then outputting the mode setting signal in response to the test signal; a set/reset master signal generator for receiving the first set/reset signal to output a set/reset master signal for commonly controlling a test mode of internal blocks of the semiconductor memory device; and a test control signal generator for combining an output signal of the test logic portion to generate a plurality of control signals and generating the set/reset master signal as a plurality of test control signals in response to the plurality of control signals.
摘要翻译：半导体存储器件包括：控制信号发生器，用于组合从外部施加的命令信号以产生测试信号; 设置/复位信号发生器，用于响应于测试信号接收从外部施加的模式设置信号，并且当模式设置信号是指定单独设置/复位的信号时产生第一设置/复位信号; 测试逻辑部分，用于响应于测试信号存储并随后输出模式设置信号; 一个设置/复位主信号发生器，用于接收第一设置/复位信号以输出一个设置/复位主信号，用于共同控制半导体存储器件的内部块的测试模式; 以及测试控制信号发生器，用于组合测试逻辑部分的输出信号以产生多个控制信号，并且响应于多个控制信号，将设置/复位主信号生成为多个测试控制信号。

86. 发明申请

US20070100104A1 METHOD OF PREPARING VINYLCHLORIDE-BASED RESIN CAPABLE OF PRODUCING PLASTISOL WITH LOW VISCOSITY, VINYLCHLORIDE-BASED RESIN PREPARED USING THE METHOD, METHOD OF PREPARING VINYLCHLORIDE-BASED PLASTISOL, AND VINYLCHLORIDE-BASED PLASTISOL PREPARED USING THE METHOD 有权
标题翻译：制备能够制造低粘度的氯乙烯的树脂的方法，使用该方法制备的基于氯乙烯的树脂，制备基于乙烯基氯的PLASTISOL的方法和使用该方法制备的基于氯乙烯的PLASTISOL
公开(公告)号：US20070100104A1
公开(公告)日：2007-05-03
申请号：US11554336
申请日：2006-10-30
申请人： Yoonjeong BAEK , Kyung Hyun KIM , Hyunkyou HA , Chan Hee Lee
发明人： Yoonjeong BAEK , Kyung Hyun KIM , Hyunkyou HA , Chan Hee Lee
IPC分类号： C08F14/06
CPC分类号： C08F14/06 , C08F6/18 , C08J3/122 , C08J3/16 , C08J3/18 , C08J2327/06 , C08K5/09 , C08L27/06 , C08F2/16
摘要： Provided is a method of preparing a vinylchloride-based resin. The method includes adding to a vinylchloride-based latex an acid, preferably, 1-7 parts by weight of the acid based on 100 parts by weight of a solid of the vinylchloride-based latex; optionally, incubating the resultant mixture at a temperature of 30˜60° C. for 30 minutes to 3 hours; and drying the mixture. Therefore, it is possible to reduce the viscosity of a vinylchloride-based plastisol, thereby improving the processability of the plastisol.
摘要翻译：提供一种制备氯乙烯类树脂的方法。该方法包括以氯乙烯基胶乳为基础的100重量份固体将基于氯乙烯的胶乳中的酸，优选1-7重量份的酸加入到氯乙烯基胶乳中; 任选地，将所得混合物在30〜60℃的温度下孵育30分钟〜3小时; 并干燥混合物。因此，可以降低氯乙烯类增塑溶胶的粘度，从而提高增塑溶胶的加工性。

87. 发明授权

US07196010B2 Slurry for chemical mechanical polishing process and method of manufacturing semiconductor device using the same 失效
公开(公告)号：US07196010B2
公开(公告)日：2007-03-27
申请号：US10639541
申请日：2003-08-12
申请人： Young-rae Park , Jung-yup Kim , Bo-un Yoon , Kwang-bok Kim , Jae-phil Boo , Jong-won Lee , Sang-rok Hah , Kyung-hyun Kim , Chang-ki Hong
发明人： Young-rae Park , Jung-yup Kim , Bo-un Yoon , Kwang-bok Kim , Jae-phil Boo , Jong-won Lee , Sang-rok Hah , Kyung-hyun Kim , Chang-ki Hong
IPC分类号： H01L21/302
CPC分类号： H01L21/76224 , B24B37/044 , C09G1/02 , H01L21/31053
摘要： A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.

88. 发明授权

US07151043B2 Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07151043B2
公开(公告)日：2006-12-19
申请号：US11082616
申请日：2005-03-17
申请人： Tae-hyun Kim , Byoung-moon Yoon , Won-jun Lee , Yong-sun Ko , Kyung-hyun Kim
发明人： Tae-hyun Kim , Byoung-moon Yoon , Won-jun Lee , Yong-sun Ko , Kyung-hyun Kim
IPC分类号： H01L21/76
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/115
摘要： Methods of manufacturing a semiconductor device are provided. A trench is formed in a semiconductor substrate. A first field oxide layer is formed that partially fills the trench. The first field oxide layer defines an active region of the substrate that is adjacent to the trench. An upper portion of sidewalls of the trench extends upward beyond a surface of the first field oxide layer. A first liner is formed on the first field oxide layer and on the portion of the sidewalls of the trench that extend upward beyond the first field oxide layer. A second field oxide layer is formed on the first liner and fills the trench. The second field oxide layer and the first liner are each partially removed to expose a top adjacent surface and upper sidewalls of the trench along the active region of the substrate. A dielectric layer is formed on the exposed top adjacent surface and upper sidewalls of the trench. A gate electrode is formed on the dielectric layer.
摘要翻译：提供制造半导体器件的方法。在半导体衬底中形成沟槽。形成部分填充沟槽的第一场氧化物层。第一场氧化物层限定与沟槽相邻的衬底的有源区。沟槽的侧壁的上部向上延伸超过第一场氧化物层的表面。第一衬垫形成在第一场氧化物层上并且在沟槽的侧壁的部分上方向上延伸超过第一场氧化物层。在第一衬垫上形成第二场氧化物层并填充沟槽。每个部分去除第二场氧化物层和第一衬里以沿着衬底的有源区域暴露沟槽的顶部相邻表面和上侧壁。介电层形成在沟槽的暴露的顶部相邻表面和上侧壁上。在电介质层上形成栅电极。

89. 发明申请

US20060115950A1 Methods of fabricating trench type capacitors including protective layers for electrodes and capacitors so formed 审中-公开
标题翻译：制造沟槽型电容器的方法包括如此形成的用于电极和电容器的保护层
公开(公告)号：US20060115950A1
公开(公告)日：2006-06-01
申请号：US11284678
申请日：2005-11-22
申请人： Kwang-Bok Kim , Yong-Sun Ko , Kyung-Hyun Kim
发明人： Kwang-Bok Kim , Yong-Sun Ko , Kyung-Hyun Kim
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L21/3212
摘要： A method of forming a capacitor can include forming a protective layer on a metal layer in a trench in an insulating layer and outside thereof. A surface of the protective layer and the metal layer beneath can be planarized using a chemical mechanical polishing (CMP) process to expose a surface of the insulating layer outside the trench. Related structures are also disclosed.
摘要翻译：形成电容器的方法可以包括在绝缘层和其外部的沟槽中的金属层上形成保护层。可以使用化学机械抛光（CMP）工艺将保护层的表面和下面的金属层平坦化，以使沟槽外部的绝缘层的表面露出。还公开了相关结构。

90. 发明申请

US20060105686A1 Platen structure of polishing apparatus for processing semiconductor wafer and method for exchanging polishing pad affixed to the same 有权
标题翻译：用于处理半导体晶片的抛光装置的压板结构和用于更换固定在其上的抛光垫的方法
公开(公告)号：US20060105686A1
公开(公告)日：2006-05-18
申请号：US11260902
申请日：2005-10-28
申请人： Chung-Ki Min , Yong-Sun Ko , Kyung-Hyun Kim
发明人： Chung-Ki Min , Yong-Sun Ko , Kyung-Hyun Kim
IPC分类号： B24B1/00 , B24D17/00
CPC分类号： B24B37/16
摘要： A platen structure of a polishing apparatus for semiconductor wafer and a method for exchanging a polishing pad affixed to the same are provided in which the polishing pad supported by the platen is exchanged with convenience within a short time. The platen structure of the polishing apparatus in which the polishing pad attached to the platen of the polishing apparatus comprises a pad plate to which the polishing pad for polishing a wafer is attached, and a platen body combined with the pad plate and having at least one vacuum hole formed thereto to provide a vacuum passage.
摘要翻译：提供了一种用于半导体晶片的抛光装置的压板结构和用于更换固定在其上的抛光垫的方法，其中在短时间内方便地更换由压板支撑的抛光垫。抛光装置的压板结构，其中安装在抛光装置的压板上的抛光垫包括一个垫板，用于抛光晶片的抛光垫被安装到该垫板上，以及压板体与该焊盘板组合并具有至少一个形成真空孔以提供真空通道。

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