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1. 发明授权

US06626968B2 Slurry for chemical mechanical polishing process and method of manufacturing semiconductor device using the same 失效
公开(公告)号：US06626968B2
公开(公告)日：2003-09-30
申请号：US09861697
申请日：2001-05-21
申请人： Young-rae Park , Jung-yup Kim , Bo-un Yoon , Kwang-bok Kim , Jae-phil Boo , Jong-won Lee , Sang-rok Hah , Kyung-hyun Kim , Chang-ki Hong
发明人： Young-rae Park , Jung-yup Kim , Bo-un Yoon , Kwang-bok Kim , Jae-phil Boo , Jong-won Lee , Sang-rok Hah , Kyung-hyun Kim , Chang-ki Hong
IPC分类号： C09G102
CPC分类号： H01L21/76224 , B24B37/044 , C09G1/02 , H01L21/31053
摘要： A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.

2. 发明授权

US07196010B2 Slurry for chemical mechanical polishing process and method of manufacturing semiconductor device using the same 失效
公开(公告)号：US07196010B2
公开(公告)日：2007-03-27
申请号：US10639541
申请日：2003-08-12
申请人： Young-rae Park , Jung-yup Kim , Bo-un Yoon , Kwang-bok Kim , Jae-phil Boo , Jong-won Lee , Sang-rok Hah , Kyung-hyun Kim , Chang-ki Hong
发明人： Young-rae Park , Jung-yup Kim , Bo-un Yoon , Kwang-bok Kim , Jae-phil Boo , Jong-won Lee , Sang-rok Hah , Kyung-hyun Kim , Chang-ki Hong
IPC分类号： H01L21/302
CPC分类号： H01L21/76224 , B24B37/044 , C09G1/02 , H01L21/31053
摘要： A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.

3. 发明申请

US20070155178A1 Slurry for chemical mechanical polishing process and method of manufacturing semiconductor device using the same 审中-公开
标题翻译：用于化学机械抛光工艺的浆料及使用其制造半导体器件的方法
公开(公告)号：US20070155178A1
公开(公告)日：2007-07-05
申请号：US11712931
申请日：2007-03-01
申请人： Young-rae Park , Jung-yup Kim , Bo-un Yoon , Kwang-bok Kim , Jae-phill Boo , Jong-won Lee , Sang-rok Hah , Kyung-hyun Kim , Chang-ki Hong
发明人： Young-rae Park , Jung-yup Kim , Bo-un Yoon , Kwang-bok Kim , Jae-phill Boo , Jong-won Lee , Sang-rok Hah , Kyung-hyun Kim , Chang-ki Hong
IPC分类号： H01L21/306 , H01L21/461 , B44C1/22 , C23F1/00 , H01L21/302
CPC分类号： H01L21/76224 , B24B37/044 , C09G1/02 , H01L21/31053
摘要： A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.
摘要翻译：公开了一种用于材料层表面例如氧化硅层的化学机械抛光的浆料组合物。暴露于浆料的第一材料表面显示出亲水性，而第二材料层，例如其表面也暴露于浆料的多晶硅层，表现出疏水性，因此用作抛光停止层。浆料组合物基本上由水，磨料颗粒和具有亲水和疏水官能团的聚合物添加剂组成。

4. 发明授权

US06518157B2 Methods of planarizing insulating layers on regions having different etching rates 失效
公开(公告)号：US06518157B2
公开(公告)日：2003-02-11
申请号：US09917601
申请日：2001-07-27
申请人： Gee-won Nam , Gi-jong Park , Hong-kyu Hwang , Jun-shik Bae , Young-rae Park , Jung-yup Kim , Bo-un Yoon , Sang-rok Hah
发明人： Gee-won Nam , Gi-jong Park , Hong-kyu Hwang , Jun-shik Bae , Young-rae Park , Jung-yup Kim , Bo-un Yoon , Sang-rok Hah
IPC分类号： H01L2144
CPC分类号： H01L21/31056 , H01L21/31053 , H01L21/76819
摘要： An insulating layer can be formed on first and second adjacent regions of an integrated circuit having a first step difference therebetween, the first and second regions having first and second respective etch rates associated therewith. A recess can be formed in the insulating layer on the second region having a second step difference with the first region that is less than the first step difference to provide a portion of the insulating layer between the first and second adjacent regions having a third step difference with the first region that is greater than the second step difference. A width of the portion is selected based on a difference between the first and second etch rates.

5. 发明授权

US06548388B2 Semiconductor device including gate electrode having damascene structure and method of fabricating the same 失效
公开(公告)号：US06548388B2
公开(公告)日：2003-04-15
申请号：US09805213
申请日：2001-03-14
申请人： Hong-kyu Hwang , Young-Rae Park , Jung-yup Kim , Jeong-sic Jeon , Bo-un Yoon , Sang-rok Hah
发明人： Hong-kyu Hwang , Young-Rae Park , Jung-yup Kim , Jeong-sic Jeon , Bo-un Yoon , Sang-rok Hah
IPC分类号： H01L213205
CPC分类号： H01L21/76897 , H01L21/28123 , H01L21/76832 , H01L21/76834 , H01L21/76837 , H01L21/823437 , H01L21/823481
摘要： A gate electrode conductive layer is formed on an active region that is recessed relative to field oxide layers so as to define a damascene structure. The gate electrode conductive layer is formed on the active region but is not formed on a field region so that the thickness of an interlayer insulation layer deposited in a succeeding process is reduced, thereby reducing or preventing voids within the interlayer insulation layer. A polysilicon is formed on the bottom of the active region by selective epitaxial growth, thereby minimizing the influence of micro scratches, pits or stringers occurring on the bottom of the active region.

6. 发明授权

US06716732B2 Method for fabricating a contact pad of semiconductor device 有权
标题翻译：制造半导体器件接触焊盘的方法
公开(公告)号：US06716732B2
公开(公告)日：2004-04-06
申请号：US09986445
申请日：2001-11-08
申请人： Young-rae Park , Jung-yup Kim , Bo-un Yoon , Sang-rok Hah
发明人： Young-rae Park , Jung-yup Kim , Bo-un Yoon , Sang-rok Hah
IPC分类号： H01L213205
CPC分类号： H01L21/76897 , H01L21/76895
摘要： A method of fabricating a contact pad of a semiconductor device is disclosed. The method includes forming a stopping layer over the semiconductor substrate. An interdielectric layer is formed over the stopping layer, and the interdielectric layer is planarized to expose at least a gate upper dielectric layer by using a material which exhibits a high-polishing selectivity with respect to the interdielectric layer. The interdielectric layer is etched in a region in which a contact pad will be formed on the semiconductor substrate. A conductive material is deposited on the semiconductor substrate. Finally, planarizing is carried out using a material which exhibits a high-polishing selectivity of the upper dielectric layer with respect to the conductive material.
摘要翻译：公开了制造半导体器件的接触焊盘的方法。该方法包括在半导体衬底上形成阻挡层。在停止层上形成介电层，并且通过使用相对于介电层表现出高抛光选择性的材料，使介电层平坦化以至少暴露出栅极上电介质层。在其中将在半导体衬底上形成接触焊盘的区域中蚀刻介电层。导电材料沉积在半导体衬底上。最后，使用表现出相对于导电材料的上电介质层的高抛光选择性的材料进行平面化。

7. 发明授权

US06610596B1 Method of forming metal interconnection using plating and semiconductor device manufactured by the method 有权
标题翻译：使用该方法制造的使用电镀和半导体器件形成金属互连的方法
公开(公告)号：US06610596B1
公开(公告)日：2003-08-26
申请号：US09662120
申请日：2000-09-14
申请人： Jong-won Lee , Bo-un Yoon , Kun-tack Lee , Sang-rok Hah
发明人： Jong-won Lee , Bo-un Yoon , Kun-tack Lee , Sang-rok Hah
IPC分类号： H01L2144
CPC分类号： H01L21/7684 , H01L21/76879
摘要： A method is provided for forming a metal interconnection using a plating process, which can improve the throughput and reliability of semiconductor devices by decreasing the required polishing in a chemical mechanical polishing process. A semiconductor device manufactured by this method is also provided. In the method of forming a metal interconnection, a recess region is formed in a portion of an insulation layer formed over a substrate, i.e., where a metal interconnection layer will be formed. A diffusion prevention layer is formed over the substrate, the insulation layer, and the recess region. Then, a metal seed layer is formed over the diffusion prevention layer only in the recess region using a chemical mechanical polishing process or an etch back process. A conductive plating layer is then formed on the metal seed layer only in the recess region. Thereafter, surface polarization is performed to form a metal interconnection layer in the recess region. The plating layer may be formed after forming the seed layer only in the bottom portion of the recess region.
摘要翻译：提供了一种使用电镀工艺形成金属互连的方法，其可以通过减少化学机械抛光工艺中所需的抛光来提高半导体器件的生产能力和可靠性。还提供了通过该方法制造的半导体器件。在形成金属互连的方法中，在形成在基板上的绝缘层的一部分中，即将形成金属互连层的区域中形成凹陷区域。在基板，绝缘层和凹部区域上形成扩散防止层。然后，使用化学机械抛光工艺或回蚀工艺，仅在凹陷区域中在扩散防止层上形成金属种子层。然后在金属种子层上仅在凹陷区域中形成导电镀层。此后，进行表面极化以在凹部区域中形成金属互连层。可以在仅在凹部的底部形成种子层之后形成镀层。

8. 发明授权

US06514862B2 Wafer polishing slurry and chemical mechanical polishing (CMP) method using the same 有权
标题翻译：晶圆抛光浆和化学机械抛光（CMP）方法使用相同
公开(公告)号：US06514862B2
公开(公告)日：2003-02-04
申请号：US09977239
申请日：2001-10-16
申请人： Jae-dong Lee , Jong-won Lee , Bo-un Yoon , Sang-rok Hah
发明人： Jae-dong Lee , Jong-won Lee , Bo-un Yoon , Sang-rok Hah
IPC分类号： H01L21302
CPC分类号： C09G1/02 , H01L21/31053
摘要： A chemical mechanical polishing slurry includes an additive of a quaternary ammonium compound having a form of {N—(R1R2R3R4)}+X−, in which R1, R2, R3, and R4 are radicals, and X− is an anion derivative including halogen elements. Preferably, the quaternary ammonium compound is one of [(CH3)3NCH2CH2OH]Cl, [(CH3)3NCH2CH2OH]l, [(CH3)3NCH2CH2OH]Br, [(CH3)3NCH2CH2OH]CO3, and mixtures thereof. The slurry may further include a pH control agent formed of a base such as KOH, NH4OH, and (CH3)4NOH, and an acid such as HCl, H2SO4, H3PO4, and HNO3. Also, the pH control agent can include [(CH3)3NCH2CH2OH]OH. The slurry may further include a surfactant such as cetyldimethyl ammonium bromide, cetyldimethyl ammonium bromide, polyethylene oxide, polyethylene alcohol or polyethylene glycol.
摘要翻译：化学机械抛光浆料包括具有{N-（R1R2R3R4）} + X-形式的季铵化合物的添加剂，其中R 1，R 2，R 3和R 4是自由基，X是包含卤素的阴离子衍生物元素。优选地，季铵化合物是[（CH 3）3 NHCH 2 CH 2 OH] Cl，[（CH 3）3 NHCH 2 CH 2 OH] 1，[（CH 3）3 NHCH 2 CH 2 OH] Br，[（CH 3）3 NHCH 2 CH 2 OH] CO 3及其混合物之一。该浆料还可以包括由碱如KOH，NH 4 OH和（CH 3）4 NOH形成的pH控制剂，以及酸如HCl，H 2 SO 4，H 3 PO 4和HNO 3。此外，pH控制剂可以包括[（CH 3）3 NHCH 2 OH] OH。浆料还可以包括表面活性剂如十六烷基二甲基溴化铵，鲸蜡基二甲基溴化铵，聚环氧乙烷，聚乙烯醇或聚乙二醇。

9. 发明授权

US06914001B2 Chemical/mechanical polishing slurry, and chemical mechanical polishing process and shallow trench isolation process employing the same 失效
标题翻译：化学/机械抛光浆料和化学机械抛光工艺以及采用其的浅沟槽隔离工艺
公开(公告)号：US06914001B2
公开(公告)日：2005-07-05
申请号：US10351539
申请日：2003-01-27
申请人： Jong-won Lee , Jae-dong Lee , Bo-un Yoon , Sang-rok Hah
发明人： Jong-won Lee , Jae-dong Lee , Bo-un Yoon , Sang-rok Hah
IPC分类号： B24B57/02 , B24B37/00 , C09G1/02 , C09K3/14 , H01L21/304 , H01L21/3105 , H01L21/302
CPC分类号： H01L21/31053 , C09G1/02 , C09K3/1463
摘要： A CMP oxide slurry includes an aqueous solution containing abrasive particles and two or more different passivation agents. Preferably, the aqueous solution is made up of deionized water, and the abrasive particles are a metal oxide selected from the group consisting of ceria, silica, alumina, titania, zirconia and germania. Also, a first passivation agent may be an anionic, cationic or nonionic surfactant, and a second passivation agent may be a phthalic acid and its salts. In one example, the first passivation agent is poly-vinyl sulfonic acid, and the second passivation agent is potassium hydrogen phthalate. The slurry exhibits a high oxide to silicon nitride removal selectivity.
摘要翻译： CMP氧化物浆料包括含有磨料颗粒和两种或更多种不同钝化剂的水溶液。优选地，水溶液由去离子水组成，磨料颗粒是选自二氧化铈，二氧化硅，氧化铝，二氧化钛，氧化锆和氧化锗的金属氧化物。此外，第一钝化剂可以是阴离子，阳离子或非离子表面活性剂，第二钝化剂可以是邻苯二甲酸及其盐。在一个实例中，第一钝化剂是聚乙烯基磺酸，第二钝化剂是邻苯二甲酸氢钾。该浆料表现出高的氧化物与氮化硅的去除选择性。

10. 发明授权

US07846801B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07846801B2
公开(公告)日：2010-12-07
申请号：US11833050
申请日：2007-08-02
申请人： Sung-jun Kim , Seong-kyu Yun , Chang-ki Hong , Bo-un Yoon , Jong-won Lee , Ho-young Kim
发明人： Sung-jun Kim , Seong-kyu Yun , Chang-ki Hong , Bo-un Yoon , Jong-won Lee , Ho-young Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/7851
摘要： Disclosed is a method of fabricating a semiconductor device including a multi-gate transistor. The method of fabricating a semiconductor device includes providing a semiconductor device having a number of active patterns which extend in a first direction, are separated by an isolation layer, and covered with a first insulating layer; forming a first groove by etching the isolation layer located between the active patterns adjacent to each other in the first direction; burying the first groove with a passivation layer; forming a second groove exposing at least a portion of both sides of the active patterns by etching the isolation layer located between the active patterns in a second direction intersecting the first direction; removing the passivation layer in the first groove; and forming a gate line filling at least a portion of the second groove and extending in the second direction.
摘要翻译：公开了一种制造包括多栅极晶体管的半导体器件的方法。制造半导体器件的方法包括提供具有多个沿第一方向延伸的活性图案的半导体器件，被隔离层隔开并被第一绝缘层覆盖; 通过在第一方向上蚀刻位于彼此相邻的有源图案之间的隔离层来形成第一凹槽; 用钝化层掩埋第一槽; 通过在与所述第一方向相交的第二方向上蚀刻位于所述有源图案之间的所述隔离层来形成暴露所述有源图案的两侧的至少一部分的第二凹槽; 去除第一凹槽中的钝化层; 以及形成填充所述第二凹槽的至少一部分并沿所述第二方向延伸的栅极线。

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