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81. 发明申请

US20050094431A1 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20050094431A1
公开(公告)日：2005-05-05
申请号：US10948295
申请日：2004-09-24
申请人： Atsuhiro Sato , Riichiro Shirota , Kikuko Sugimae , Koji Sakui
发明人： Atsuhiro Sato , Riichiro Shirota , Kikuko Sugimae , Koji Sakui
IPC分类号： G11C16/06 , G11C16/04 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/00
CPC分类号： G11C16/06 , G11C11/005 , G11C16/0433 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/26 , H01L27/11521 , H01L27/11546
摘要： A nonvolatile semiconductor memory includes: a memory sub array including a memory cell unit configured with a memory cell transistor and a select transistor connected in series; a control gate line driver including a control gate line driver transistor connected to a control gate line of the memory cell transistor; and a select transistor gate line driver including a select gate line driver transistor connected to a select gate line of the select transistor. A thickness of a gate insulator of the control gate line driver transistor is thicker than that of the select gate line driver transistor.
摘要翻译：非易失性半导体存储器包括：存储器子阵列，包括配置有存储单元晶体管的存储单元单元和串联连接的选择晶体管; 控制栅极线驱动器，包括连接到存储单元晶体管的控制栅极线的控制栅极线驱动晶体管; 以及选择晶体管栅极线驱动器，其包括连接到选择晶体管的选择栅极线的选择栅极线驱动晶体管。控制栅极线驱动晶体管的栅极绝缘体的厚度比选择栅线驱动晶体管的厚度厚。

82. 发明授权

US06801458B2 Nonvolatile semiconductor memory 失效
公开(公告)号：US06801458B2
公开(公告)日：2004-10-05
申请号：US10638406
申请日：2003-08-12
申请人： Koji Sakui , Junichi Miyamoto
发明人： Koji Sakui , Junichi Miyamoto
IPC分类号： G11C1602
CPC分类号： G11C16/10 , G11C16/0433
摘要： A memory cell array has a unit formed from one memory cell and two select transistors sandwiching the memory cell. One block has one control gate line. Memory cells connected to one control gate line form one page. A sense amplifier having a latch function is connected to a bit line. In a data change operation, data of memory cells of one page are read to the sense amplifiers. After data are superscribed on data in the sense amplifiers, and a page erase is performed, data in the sense amplifiers are programmed in the memory cells of one page. Superscription of data in the sense amplifiers allows a data change operation for byte data or page data.

83. 发明授权

US06594169B2 Semiconductor memory device and memory system 失效
公开(公告)号：US06594169B2
公开(公告)日：2003-07-15
申请号：US10078009
申请日：2002-02-20
申请人： Koji Sakui
发明人： Koji Sakui
IPC分类号： G11C700
CPC分类号： G11C5/025 , G06F13/4234 , Y02D10/14 , Y02D10/151
摘要： The present invention provides a semiconductor memory device and memory system comprising a first semiconductor memory having a first peripheral circuit for transmitting and receiving memory data to/from a first memory cell array, a second semiconductor memory having a second peripheral circuit for transmitting and receiving the memory data to/from a second memory cell array, and a part of the peripheral circuit of the first semiconductor memory formed adjacent to the second memory cell array by a design rule of the second peripheral circuit.

84. 发明授权

US06512703B2 Nonvolatile semiconductor memory 失效
公开(公告)号：US06512703B2
公开(公告)日：2003-01-28
申请号：US09921570
申请日：2001-08-06
申请人： Koji Sakui , Junichi Miyamoto
发明人： Koji Sakui , Junichi Miyamoto
IPC分类号： G11C700
CPC分类号： G11C16/10 , G11C16/0433
摘要： A memory cell array has a unit formed from one memory cell and two select transistors sandwiching the memory cell. One block has one control gate line. Memory cells connected to one control gate line form one page. A sense amplifier having a latch function is connected to a bit line. In a data change operation, data of memory cells of one page are read to the sense amplifiers. After data are superscribed on data in the sense amplifiers, and a page erase is performed, data in the sense amplifiers are programmed in the memory cells of one page. Superscription of data in the sense amplifiers allows a data change operation for byte data or page data.

85. 发明授权

US06512702B1 Non-volatile semiconductor memory device and data erase controlling method for use therein 失效
标题翻译：非挥发性半导体存储器件和数据擦除控制方法
公开(公告)号：US06512702B1
公开(公告)日：2003-01-28
申请号：US09539212
申请日：2000-03-30
申请人： Toshio Yamamura , Yoshihisa Sugiura , Kazuhisa Kanazawa , Koji Sakui , Hiroshi Nakamura
发明人： Toshio Yamamura , Yoshihisa Sugiura , Kazuhisa Kanazawa , Koji Sakui , Hiroshi Nakamura
IPC分类号： G11C1604
CPC分类号： G11C16/3445 , G11C16/0483 , G11C16/16 , G11C16/344
摘要： A memory cell array is divided into left and right cell arrays, each of which includes a plurality of blocks. Data erase is sequentially controlled by an erase control circuit on the basis of an erase command flag incorporated into a command register and an address incorporated into an address register. Batch erase is carried out with respect to selected blocks of the right and left cell arrays. After data erase, a verify operation is carried out with respect to the erased blocks by retrieving the erased blocks simultaneously with respect to the right and left cell arrays in parallel. Thus, the time required to retrieve the selected blocks for the verify operation after data erase is shortened, so that the time required to carry out the whole data erase is shortened.
摘要翻译：存储单元阵列被分成左和右单元阵列，每个阵列中的每一个包括多个块。基于结合到命令寄存器中的擦除命令标志和结合到地址寄存器中的地址，由擦除控制电路依次控制数据擦除。相对于右和左单元阵列的选定块执行批量擦除。在数据擦除之后，通过并行地相对于左和右单元阵列同时检索擦除块来执行关于擦除块的验证操作。因此，缩短在数据擦除之后检索用于验证操作的所选块所需的时间，从而缩短了执行整个数据擦除所需的时间。

86. 发明授权

US06418058B1 Nonvolatile semiconductor memory device 有权
公开(公告)号：US06418058B1
公开(公告)日：2002-07-09
申请号：US09994828
申请日：2001-11-28
申请人： Koji Sakui , Hiroshi Nakamura , Kenichi Imamiya
发明人： Koji Sakui , Hiroshi Nakamura , Kenichi Imamiya
IPC分类号： G11C1606
CPC分类号： G11C16/3454
摘要： In NAND type EEPROM capable of high-speed rewriting by ensuring that the memory cell current during write verify read-out operation is larger than that during normal data read-out operation, a NAND cell is composed of a plurality of serially connected memory cells (MC0 through MC31) and selection transistors (SST and GST). During data write operation, a voltage (Vpgm) is applied to a selected word line of a selected block, and a pass voltage (Vpass2) is applied to non-selected word lines to introduce electrons to the floating gate of the selected memory cell. In verify read-out operation after data write operation, a verify read-out voltage is applied to the selected word line and a pass voltage (Vpass3) to non-selected word lines. The pass voltage (Vpass3) applied to non-selected word lines during verify read-operation is higher than the pass voltage (Vpass1) applied to non-selected word lines during normal data read-out operation.

87. 发明授权

US06329250B1 Method of manufacturing semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US06329250B1
公开(公告)日：2001-12-11
申请号：US09521612
申请日：2000-03-09
申请人： Koji Sakui
发明人： Koji Sakui
IPC分类号： H01L218246
CPC分类号： H01L27/1126 , H01L27/112
摘要： A semiconductor memory device has a semiconductor substrate and a plurality of memory transistors, each having a gate electrode, a source diffused layer and a drain diffused layer and provided in array. Data is fixedly written as a difference between threshold voltages depending on an existence or non-existence of a doped channel layer. The doped channel layer extends to at least one of the source and the drain diffused layers. In order to manufacture such memory device, after forming a plurality of memory transistors, the steps of providing a mask having an opening formed so that a side surface of the gate electrode and substrate surface of one of the source diffused layer and the drain diffused layer are exposed and providing a doped channel layer under the gate electrode and in one of the source and drain diffused layers by implanting impurity ions through the opening with an inclined angle selected from a range from perpendicularity to parallelism to the substrate.
摘要翻译：半导体存储器件具有半导体衬底和多个存储晶体管，每个存储晶体管具有栅电极，源极扩散层和漏极扩散层并且阵列设置。根据存在或不存在掺杂沟道层，将数据固定地写为阈值电压之间的差。掺杂沟道层延伸到源极和漏极扩散层中的至少一个。为了制造这样的存储器件，在形成多个存储晶体管之后，提供具有开口形成为使源极扩散层和漏极扩散层之一的栅电极和衬底表面的侧表面的掩模的步骤并且通过从垂直于平行于衬底到平行度的范围内以倾斜角度注入杂质离子而在栅极电极之下和在源极和漏极扩散层中的一个中提供掺杂沟道层。

88. 发明授权

US06240022B1 Non-volatile semiconductor memory device with block erase function 失效
标题翻译：具有块擦除功能的非易失性半导体存储器件
公开(公告)号：US06240022B1
公开(公告)日：2001-05-29
申请号：US09055215
申请日：1998-04-06
申请人： Koji Sakui , Hiroshi Nakamura , Toshihiko Himeno , Junichi Miyamoto
发明人： Koji Sakui , Hiroshi Nakamura , Toshihiko Himeno , Junichi Miyamoto
IPC分类号： G11C1604
CPC分类号： G11C16/16
摘要： At the time of erasing data, common gate lines connected to selective gates are charged with Vcc or a voltage higher than. This enables reliable cut-off of transfer transistors at the time of erasing data. Accordingly, even if the potential of the selective gates increase in accordance with an increase in the substrate potential of a memory cell portion, current leakage through the transistors can be prevented. Further, at the time of erasing data, the common gate lines are set to VL slightly higher than Vss. This can enhance the cut-off characteristics of transfer transistors in a non-selected block, and prevent erroneous erasion of data stored in memory cells included in the non-selected block.
摘要翻译：在擦除数据时，连接到选择栅极的公共栅极线用Vcc或高于电压的电压充电。这样可以在擦除数据时切换传输晶体管。因此，即使选择栅极的电位根据存储单元部分的衬底电位的增加而增加，也可以防止通过晶体管的漏电流。此外，在擦除数据时，将公共栅极线设置为略高于Vss的VL。这可以增强非选择块中的转移晶体管的截止特性，并且防止存储在未选择块中的存储单元中的数据的错误擦除。

89. 发明授权

US06214665B1 Semiconductor memory device having memory cells each having a conductive body of booster plate and a method for manufacturing the same 失效
标题翻译：具有各自具有增压板的导电体的存储单元的半导体存储器件及其制造方法
公开(公告)号：US06214665B1
公开(公告)日：2001-04-10
申请号：US09186182
申请日：1998-11-05
申请人： Koji Sakui
发明人： Koji Sakui
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： A booster plate is insulatively formed on a silicon semiconductor substrate with a first gate insulating film disposed therebetween. A floating gate which forms a capacitor in cooperation with part of at least the upper surface of the booster plate is insulatively formed on the booster plate with a second insulating film disposed therebetween. Further, a control gate is insulatively formed on the floating gate with a third insulating film disposed therebetween.
摘要翻译：在硅半导体衬底上绝缘地形成升压板，其间设置有第一栅极绝缘膜。与增压板的至少上表面的一部分配合形成电容器的浮动栅极在增压板上间隔地形成有设置在其间的第二绝缘膜。此外，在浮置栅极上绝缘地形成控制栅极，其间设置有第三绝缘膜。

90. 发明授权

US6107658A Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US6107658A
公开(公告)日：2000-08-22
申请号：US468928
申请日：1999-12-22
申请人： Yasuo Itoh , Koji Sakui
发明人： Yasuo Itoh , Koji Sakui
IPC分类号： G11C16/04 , H01L27/115 , H01L29/72
CPC分类号： H01L27/115 , G11C16/0483
摘要： In a NAND EEPROM using the local self-boosting system, an intermediate voltage which allows a memory cell adjacent to a selected memory cell to be turned on is applied to the control gate of the adjacent memory cell. As a result, even if the adjacent memory cell is in a normally-off state, the potential of a bit line can be transmitted to the adjacent memory cell. Thus, the reliability of the write inhibition in a non-selected NAND memory cell column is improved, while data can be written at random into a plurality of memory cells in a selected NAND memory cell column. When data is to be erased, an absolute value of an erasing voltage applied to a control gate can be less. As a result, data can be erased by a lower erasure voltage than that required in the conventional art. Consequently, the element refinement, the reliability and the yield can be further improved.
摘要翻译：在使用本地自增强系统的NAND EEPROM中，将允许与所选存储单元相邻的存储单元导通的中间电压被施加到相邻存储单元的控制栅极。因此，即使相邻的存储单元处于常关状态，也可以将位线的电位发送到相邻的存储单元。因此，提高了在非选择的NAND存储单元列中写入禁止的可靠性，同时可以将数据随机写入到所选NAND存储单元列中的多个存储单元中。当要擦除数据时，施加到控制栅极的擦除电压的绝对值可以较小。结果，可以通过比传统技术中所需的更低的擦除电压来擦除数据。因此，可以进一步提高元素精化，可靠性和产率。

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