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1. 发明授权

US07139201B2 Non-volatile semiconductor memory device and memory system using the same 失效
标题翻译：非易失性半导体存储器件和使用其的存储器系统
公开(公告)号：US07139201B2
公开(公告)日：2006-11-21
申请号：US11243985
申请日：2005-10-06
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G11C11/34
CPC分类号： G11C29/785 , G06F11/1008 , G06F11/1068 , G06F2201/81 , G06F2212/2022 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C29/34 , G11C29/52
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.
摘要翻译：可以缩短程序验证和擦除验证操作所需的时间。即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。在数据重写操作中，通过改变数据寄存器中的数据，对具有一次适当写入的数据的存储单元不进行重写操作。

2. 发明授权

US06781895B1 Non-volatile semiconductor memory device and memory system using the same 失效
标题翻译：非易失性半导体存储器件和使用其的存储器系统
公开(公告)号：US06781895B1
公开(公告)日：2004-08-24
申请号：US09722474
申请日：2000-11-28
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G11C700
CPC分类号： G11C29/785 , G06F11/1008 , G06F11/1068 , G06F2201/81 , G06F2212/2022 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C29/34 , G11C29/52
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.
摘要翻译：可以缩短程序验证和擦除验证操作所需的时间。即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。在数据重写过程中，通过改变数据寄存器中的数据，对数据一次正确写入的存储单元不会影响重写操作。

3. 发明授权

US06172911B2 Non-volatile semiconductor memory device with an improved verify voltage generator 失效
标题翻译：具有改进的验证电压发生器的非易失性半导体存储器件
公开(公告)号：US06172911B2
公开(公告)日：2001-01-09
申请号：US09283583
申请日：1999-04-01
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G11C1606
CPC分类号： G11C29/785 , G06F11/1008 , G06F11/1068 , G06F2201/81 , G06F2212/2022 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3454 , G11C29/34 , G11C29/52
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.
摘要翻译：可以缩短程序验证和擦除验证操作所需的时间。即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。在数据重写操作中，通过改变数据寄存器中的数据，对具有一次适当写入的数据的存储单元不进行重写操作。

4. 发明授权

US5751634A Non-volatile semiconductor memory device for storing multivalue data and readout/write-in method therefor 失效
标题翻译：用于存储多值数据和其读出/写入方法的非易失性半导体存储器件
公开(公告)号：US5751634A
公开(公告)日：1998-05-12
申请号：US647629
申请日：1996-05-15
申请人： Yasuo Itoh
发明人： Yasuo Itoh
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/26 , G11C7/00
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/26 , G11C2211/5642 , G11C2211/5647
摘要： Memory cells each for storing 2-bit data are connected to a bit line. First and second flip-flop circuits are coupled to the bit line. The first flip-flop circuit holds the lower bit of 2-bit data read out from or written into the memory cell and the second flip-flop circuit holds the upper bit of 2-bit data read out from or written into the memory cell. At the data readout time, the upper bit is first read out from the memory cell and then the lower bit is read out from the memory cell. At the data writing time, the upper bit is first written into the memory cell and then the lower bit is written into the memory cell.
摘要翻译：每个用于存储2位数据的存储单元连接到位线。第一和第二触发器电路耦合到位线。第一触发器电路保持从存储单元读出或写入存储单元的2位数据的低位，并且第二触发器电路保持从存储单元读出或写入存储单元的2位数据的高位。在数据读出时，首先从存储单元读出高位，然后从存储单元读出低位。在数据写入时，首先将高位写入存储单元，然后将较低位写入存储单元。

5. 发明授权

US5557568A Non-volatile semiconductor memory device with verify mode for verifying data written to memory cells 失效
标题翻译：具有用于验证写入存储单元的数据的验证模式的非易失性半导体存储器件
公开(公告)号：US5557568A
公开(公告)日：1996-09-17
申请号：US427265
申请日：1995-04-24
申请人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
发明人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
IPC分类号： G11C17/00 , G11C7/02 , G11C7/10 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454 , G11C7/02 , G11C7/1006 , G11C7/1048
摘要： A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element, and a transistor charges the bit line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range. A data setting circuit for connects one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.
摘要翻译：非挥发性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路。位线通过开关元件连接到触发器电路，晶体管对位线进行充电。连接到位线并具有MOS晶体管结构的非易失性存储单元将其阈值设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，存储单元的阈值在触发器电路保持在第一状态的同时触发器电路保持在第二状态，并且当触发器电路保持在第二状态时阈值的偏移不被影响时，从第一阈值范围向第二阈值范围移位，在写模式之后，当阈值保持在第二阈值范围内时，位线被充电晶体管保持在电荷电位。一种数据设定电路，用于在触发电路的第一和第二信号节点之一连接到预定电位，当位线在验证模式下处于充电电位时，从而将触发器电路设置在第二状态，而与在验证模式之前的状态。

6. 发明授权

US5368088A Apparatus of continuously casting a metal sheet 失效
标题翻译：连续铸造金属板的装置
公开(公告)号：US5368088A
公开(公告)日：1994-11-29
申请号：US42860
申请日：1993-04-05
申请人： Takashi Furuya , Hidemaro Takeuchi , Akio Kasama , Yasuo Itoh , Motoya Fujii , Hideki Oka , Shogo Matsumura , Kunimasa Sasaki , Keiichi Yamamoto
发明人： Takashi Furuya , Hidemaro Takeuchi , Akio Kasama , Yasuo Itoh , Motoya Fujii , Hideki Oka , Shogo Matsumura , Kunimasa Sasaki , Keiichi Yamamoto
IPC分类号： B22D11/06
CPC分类号： B22D11/0651 , B22D11/064 , B22D11/0697
摘要： Molten metal is supplied to a pouring basin formed between cooling members, such as movable cooling drums. A closed space is formed at a meniscus area whereat any one of the cooling members starts to come into contact with the molten metal, and a soluble gas or a mixture of soluble and insoluble gases is supplied to and filled in the closed space, thereby covering the meniscus area with the gas or the mixture. This arrangement enables a continuous casting of a thin metal sheet without surface cracks and having excellent surface characteristics.
摘要翻译：将熔融金属供应到形成在诸如可移动冷却鼓之类的冷却构件之间的倾倒盆中。在弯液面区域处形成封闭空间，其中任何一个冷却构件开始与熔融金属接触，并且将可溶性气体或可溶性和不溶性气体的混合物供给并填充在封闭空间中，从而覆盖弯液面与气体或混合物。这种布置使得能够连续铸造薄金属片而没有表面裂纹并且具有优异的表面特性。

7. 外观设计

USD305721S Electric finishing sander 失效
公开(公告)号：USD305721S
公开(公告)日：1990-01-30
申请号：US51062
申请日：1987-05-15
申请人： Fusao Fushiya , Yasuo Itoh
设计人： Fusao Fushiya , Yasuo Itoh

8. 发明授权

US4800530A Semiconductor memory system with dynamic random access memory cells 失效
标题翻译：具有动态随机存取存储单元的半导体存储器系统
公开(公告)号：US4800530A
公开(公告)日：1989-01-24
申请号：US85086
申请日：1987-08-13
申请人： Yasuo Itoh , Fumio Horiguchi , Shigeyoshi Watanabe , Kazunori Ohuchi , Mitsugi Ogura
发明人： Yasuo Itoh , Fumio Horiguchi , Shigeyoshi Watanabe , Kazunori Ohuchi , Mitsugi Ogura
IPC分类号： G11C11/40 , G11C7/00 , G11C7/10 , G11C7/22
CPC分类号： G11C7/22 , G11C7/00 , G11C7/1033
摘要： A dynamic random access memory system comprises first and second memory banks. A plurality of memory cells connected to a word line are grouped into first and second groups. The first group is arranged in the first memory bank and the second group is arranged in the second memory bank. Read/write means is provided in which each n bits from and to the first group and each n bits from and to the second group are read and written alternatively. Each bit is read and written in synchronism with the toggles of a column address strobe signal.
摘要翻译：动态随机存取存储器系统包括第一和第二存储体。连接到字线的多个存储单元被分组为第一组和第二组。第一组布置在第一存储体中，第二组布置在第二存储体中。提供读/写装置，其中从第一组的每个n位和从第二组的每个n位和第二组的每个n位被交替地读取和写入。每个位与列地址选通信号的切换同步读写。

9. 发明授权

US4792547A Pyrazine-2-carboxamide derivatives useful in treating allergic disease 失效
标题翻译：吡嗪-2-甲酰胺衍生物，用于治疗过敏性疾病
公开(公告)号：US4792547A
公开(公告)日：1988-12-20
申请号：US941918
申请日：1986-12-15
申请人： Yasuo Itoh , Hideo Kato , Eiichi Koshinaka , Nobuo Ogawa , Kazuya Mitani
发明人： Yasuo Itoh , Hideo Kato , Eiichi Koshinaka , Nobuo Ogawa , Kazuya Mitani
IPC分类号： C07D401/14 , C07D403/12 , C07D403/14 , A61K31/55 , A61K31/495
CPC分类号： C07D401/14 , C07D403/12 , C07D403/14
摘要： Novel pyrazine derivatives useful for treatment of bronchial asthma, allergic gastorenteric trouble, hay fever urticaria, allertic rhinitis, and allergic conjunctivitis, and pharmaceutical compositions thereof, are disclosed. The compounds have the formula I as follows: ##STR1## wherein R represents hydrogen or ##STR2## wherein R.sub.1 and R.sub.2 may be the same or different and each independently represents hydrogen, straight or branched-chain lower-alkyl, or cycloalkyl having three to six carbon atoms inclusive, phenyl which may be substituted with halogen, lower-alkyl, or lower-alkoxy, or wherein R.sub.1 and R.sub.2 together represent alkylene of four to six carbon atoms, inclusive, optionally interrupted by one or two nitrogen atoms or one oxygen atom and said ring being optionally substituted by straight or branched-chain lower-alkyl having one to six carbon atoms inclusive, hydroxy, or phenyl,and pharmaceutically-acceptable salts thereof.
摘要翻译：用于治疗支气管哮喘，过敏性胃炎，花粉荨麻疹，过敏性鼻炎和过敏性结膜炎的新颖吡嗪衍生物及其药物组合物。化合物具有如下式I：其中R表示氢或者其中R 1和R 2可以相同或不同，并且各自独立地表示氢，直链或支链低级烷基或具有三个至 6个碳原子，可被卤素，低级烷基或低级烷氧基取代的苯基，或其中R 1和R 2一起代表四至六个碳原子的亚烷基，包括任选地被一个或两个氮原子或一个氧所述环任选被具有1-6个碳原子的直链或支链低级烷基，羟基或苯基取代，及其药学上可接受的盐。

10. 发明授权

US4528287A 6-Fluoro-1, 4-dihydro-4-oxo-7-substituted piperazinylquinoline-3-carboxylic acids and the method for preparing the same 失效
标题翻译： 6-氟-1,4-二氢-4-氧代-7-取代的哌嗪基喹啉-3-羧酸及其制备方法
公开(公告)号：US4528287A
公开(公告)日：1985-07-09
申请号：US651423
申请日：1984-09-17
申请人： Yasuo Itoh , Hideo Kato , Nobuo Ogawa , Eiichi Koshinaka , Tomio Suzuki , Noriyuki Yagi
发明人： Yasuo Itoh , Hideo Kato , Nobuo Ogawa , Eiichi Koshinaka , Tomio Suzuki , Noriyuki Yagi
IPC分类号： C07D401/02 , C07D215/56 , A61K31/47 , C07D401/04
CPC分类号： C07D215/56
摘要： The invention is concerned with the novel piperazinylquinoline-3-carboxylic acids represented by formula (I) ##STR1## or a pharmacologically-acceptable salt thereof, a process for the preparation of them, and a pharmaceutical composition which contains these new compounds as active ingredient and can be used as the therapeutic agent against bacteria.
摘要翻译：本发明涉及由式（I）表示的新型哌嗪基喹啉-3-羧酸或其药学上可接受的盐，其制备方法和含有这些新化合物的药物组合物作为活性成分，可以用作抗细菌的治疗剂。

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