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71. 发明授权

US06762077B2 Integrated sensor packages and methods of making the same 有权
公开(公告)号：US06762077B2
公开(公告)日：2004-07-13
申请号：US09956469
申请日：2001-09-18
申请人： Johan Schuurmans , William R. Betts , Roger Diels , Adrian Hill
发明人： Johan Schuurmans , William R. Betts , Roger Diels , Adrian Hill
IPC分类号： H01L2144
CPC分类号： G01L19/147 , B29C33/06 , B60C23/0408 , G01L19/141 , G01L19/148 , H01L21/50 , H01L21/56 , H01L23/315 , H01L31/0203 , H01L2224/48091 , H01L2224/48137 , H01L2224/8592 , H01L2924/00014 , H01L2224/45099
摘要： Elements of a sensor system are encapsulated into a single package. The sensor elements are covered with a flexible gel coat and then inserted into a molding tool cavity. Each element may be individually coated with a gel blob, or all elements may by coated with a single gel blob. One or more retractable pins are incorporated into the molding tool and in their normal position are each in contact with the gel. A molding compound is injected into the cavity so as to encapsulate the device and gel coat. When the pins are extracted and the device ejected from the molding cavity, one or more passageways in the molding are left defined by the pins. The passageways expose the flexible gel covering the device elements to the atmosphere. For pressure sensitive elements, the gel, being flexible, transfers the local air pressure to the pressure sensitive element. For optical elements, the exposed gel is preferably removed to allow for the passage of radiation to and from the device elements. Alternatively, or in addition, an optically transmitting gel is used so as to allow for the passage of radiation at specific wavelengths.

72. 发明授权

US06759331B1 Method for reducing surface zener drift 失效
标题翻译：减少表面齐纳转移的方法
公开(公告)号：US06759331B1
公开(公告)日：2004-07-06
申请号：US10438481
申请日：2003-05-15
申请人： Heikyung Min , Steven Kurihara , Robert Spence
发明人： Heikyung Min , Steven Kurihara , Robert Spence
IPC分类号： H01L2144
CPC分类号： H01L21/7685 , H01L29/866
摘要： Drift in the reverse breakdown voltage of a surface zener diode is substantially reduced by forming a layer of material that includes titanium before or after the metallization steps that are used to form the first layer of metal (the metal-1 layer) or the second layer of metal (the metal-2 layer).
摘要翻译：通过在用于形成第一金属层（金属-1层）或第二层的金属化步骤之前或之后形成包括钛的材料层，基本上减小了表面齐纳二极管的反向击穿电压的漂移的金属（金属-2层）。

73. 发明授权

US06759330B2 Method of providing a structure using self-aligned features 有权
公开(公告)号：US06759330B2
公开(公告)日：2004-07-06
申请号：US10295536
申请日：2002-11-15
申请人： Dinesh Chopra , Kevin G. Donohoe , Cem Basceri
发明人： Dinesh Chopra , Kevin G. Donohoe , Cem Basceri
IPC分类号： H01L2144
CPC分类号： H01L21/28079 , H01L21/2885 , H01L21/3212 , H01L21/7684 , H01L21/76879 , H01L28/91 , H01L29/66583
摘要： In a copper plating process, a seed layer is uniformly deposited over a surface, including lining a high aspect ratio trench defined by that surface. A mask layer is provided using a process that fails to deposit in the trench. In one exemplary embodiment, the failure is due to the decrease in the isotropic flux of neutrals toward the bottom of the trench. Copper is subsequently electroplated. Because the seed layer is exposed only within the trench, copper deposits only therein. The self-aligned mask prevents plating outside of the trench. A chemical-mechanical planarization step removes the mask and the seed layer extending beyond the trench, leaving a copper structure within the trench. The structure may serve as a conductive line, an interconnect, or a capacitor plate.

74. 发明授权

US06759275B1 Method for making high-performance RF integrated circuits 有权
标题翻译：制造高性能RF集成电路的方法
公开(公告)号：US06759275B1
公开(公告)日：2004-07-06
申请号：US09945436
申请日：2001-09-04
申请人： Jin-Yuan Lee , Mou Shiung Lin
发明人： Jin-Yuan Lee , Mou Shiung Lin
IPC分类号： H01L2144
CPC分类号： H01L23/544 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/5227 , H01L28/10 , H01L2221/68327 , H01L2221/6834 , H01L2221/6835 , H01L2924/0002 , H01L2924/12044 , H01L2924/1423 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/00
摘要： A new method and structure is provided for the creation of a semiconductor inductor. Under the first embodiment of the invention, a semiconductor substrate is provided with a scribe line in a passive surface region and active circuits surrounding the passive region. At least one bond pad is created on the passive surface of the substrate close to and on each side of the scribe line. A layer of insulation is deposited, a layer of dielectric is deposited over the layer of insulation, at least one bond pad is provided on the surface of the layer of dielectric on each side of the scribe line. At least one inductor is created on each side of the scribe line on the surface of the layer of dielectric. A layer of passivation is deposited over the layer of dielectric. The substrate is attached to a glass panel by interfacing the surface of the layer of passivation with the glass panel. The substrate is sawed from the backside of the substrate in alignment with the scribe line. The silicon that remains in place in the passive surface of the substrate underneath the scribe lines is removed by etching, the glass panel is separated along the scribe line. Under the second embodiment of the invention, the inductor is created on the surface of a thick layer of polymer that is deposited over the layer of passivation.
摘要翻译：提供了一种新的制造半导体电感器的方法和结构。在本发明的第一实施例中，半导体衬底在无源表面区域中设有划线，并且在被动区域周围设有有源电路。在基板的被动表面上至少形成一个接合垫，该接合垫靠近划线的每侧。沉积一层绝缘层，在该绝缘层上沉积一层电介质，至少一个接合焊盘设置在刻划线两边的电介质层的表面上。在电介质层的表面上的划线的每侧形成至少一个电感器。一层钝化层沉积在电介质层上。通过将钝化层的表面与玻璃面板接合来将衬底附接到玻璃面板。衬底从衬底的背面锯切，与划刻线对准。通过蚀刻去除在划线下面的衬底的被动表面中残留的位置的硅，沿着划线分离玻璃面板。在本发明的第二个实施例中，电感器被形成在沉积在钝化层上的聚合物厚层的表面上。

75. 发明授权

US06756306B2 Low temperature dielectric deposition to improve copper electromigration performance 有权
标题翻译：低温介电沉积提高铜电迁移性能
公开(公告)号：US06756306B2
公开(公告)日：2004-06-29
申请号：US10334387
申请日：2002-12-30
申请人： Steven C. Avanzino , Darrell M. Erb
发明人： Steven C. Avanzino , Darrell M. Erb
IPC分类号： H01L2144
CPC分类号： H01L21/02118 , H01L21/02167 , H01L21/02271 , H01L21/312 , H01L21/314 , H01L21/76801 , H01L21/76829 , H01L21/76834
摘要： The reliability and electromigration life-time of planarized metallization features, e.g., copper, inlaid in the surface of a layer of dielectric material, are enhanced by a chemical vapor deposition process for depositing a passivation layer over the metallization patterns which comprises maintaining on the upper surfaces of the metallization features, at or below a first temperature, an inhibiting film previously deposited thereon. The inhibiting film substantially inhibits oxide layer formation on the surface of the metallization features below the first temperature. Passivation layer deposition occurs at a second temperature higher than the first temperature such that the time interval between removal of the inhibiting film and formation of the passivation layer is short enough to substantially inhibit the formation of oxides on the surface of the metal feature.
摘要翻译：通过用于在金属化图案上沉积钝化层的化学气相沉积工艺来增强镶嵌在介电材料层的表面中的平坦化金属化特征（例如铜）的可靠性和电迁移寿命，其包括保持在上部处于或低于第一温度的金属化特征的表面是预先沉积在其上的抑制膜。抑制膜基本上抑制在第一温度以下的金属化特征的表面上形成氧化物层。钝化层沉积在高于第一温度的第二温度下发生，使得去除抑制膜和钝化层的形成之间的时间间隔足够短，从而基本上抑制金属特征表面上的氧化物的形成。

76. 发明授权

US06756295B2 Chip structure and process for forming the same 有权
标题翻译：芯片结构及其形成方法
公开(公告)号：US06756295B2
公开(公告)日：2004-06-29
申请号：US10124388
申请日：2002-04-15
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
IPC分类号： H01L2144
CPC分类号： H01L21/768 , H01L21/76807 , H01L21/76838 , H01L23/522 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/60 , H01L24/05 , H01L24/13 , H01L24/45 , H01L27/0676 , H01L27/08 , H01L28/10 , H01L28/20 , H01L2221/1036 , H01L2224/0401 , H01L2224/16 , H01L2224/45 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/15174 , H01L2924/19041 , H01L2924/19051 , H01L2924/30105 , H01L2924/3011 , H01L2224/48 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.
摘要翻译：芯片结构包括基板，第一堆叠层，钝化层和第二堆积层。基板包括放置在基板的表面上的许多电气装置。第一组合层位于基底上。第一组合层设置有第一电介质体和第一互连方案，其中第一互连方案与第一介电体内部交错并电连接到电气装置。第一互连方案由第一金属层和插塞构成，其中相邻的第一金属层通过插塞电连接。钝化层设置在第一堆叠层上并且设有暴露第一互连方案的开口。第二堆叠层形成在钝化层上。第二组合层设置有第二电介质体和第二互连方案，其中第二互连方案在第二介电体内部交织并与第一互连方案电连接。第二互连方案由至少一个第二金属层和至少一个通孔金属填料构成，其中第二金属层电连接到通孔金属填料。第二金属层的迹线的厚度，宽度和横截面积分别大于第一金属层的厚度，宽度和横截面面积。

77. 发明授权

US06756251B2 Method of manufacturing microelectronic devices, including methods of underfilling microelectronic components through an underfill aperture 有权
标题翻译：制造微电子器件的方法，包括通过底部填充孔径填充微电子元件的方法
公开(公告)号：US06756251B2
公开(公告)日：2004-06-29
申请号：US09944465
申请日：2001-08-30
申请人： Teck Kheng Lee
发明人： Teck Kheng Lee
IPC分类号： H01L2144
CPC分类号： H01L24/28 , H01L21/563 , H01L23/13 , H01L2224/05573 , H01L2224/16225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83102 , H01L2224/92125 , H01L2924/00014 , H01L2924/01013 , H01L2924/01027 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/09701 , H01L2924/14 , H01L2924/15151 , H01L2224/05599
摘要： Supports (40) of microelectronic devices (10) are provided with underfill apertures (60) which facilitate filling underfill gaps (70) with underfill material (74). The underfill aperture may have a longer first dimension (62) and a shorter second dimension (64). In some embodiments, a method of filling the underfill gap (70) employs a removable stencil (80). If so desired, a stencil (80) can be used to fill multiple underfill gaps through multiple underfill apertures in a single pass.
摘要翻译：微电子器件（10）的支撑件（40）设置有底部填充孔（60），其有利于用底部填充材料（74）填充底部填充间隙（70）。底部填充孔可以具有较长的第一尺寸（62）和较短的第二尺寸（64）。在一些实施例中，填充底部填充间隙（70）的方法采用可去除的模版（80）。如果需要，可以使用模版（80）在单次通过中通过多个底部填充孔填充多个底部填充间隙。

78. 发明授权

US06753254B2 Method for forming a metallization layer 失效
标题翻译：金属化层的形成方法
公开(公告)号：US06753254B2
公开(公告)日：2004-06-22
申请号：US10217620
申请日：2002-08-13
申请人： Gurtej Singh Sandhu , Chris Chang Yu
发明人： Gurtej Singh Sandhu , Chris Chang Yu
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/2885 , H01L21/76802 , H01L21/76838 , H01L21/76873 , H01L21/76877 , H01L21/76879 , H01L21/76885 , H01L2221/1078
摘要： A method for forming a metallization layer. A first layer is formed outwardly from a semiconductor substrate. Contact vias are formed through the first layer to the semiconductor substrate. A second layer is formed outwardly from the first layer. Portions of the second layer are selectively removed such that the remaining portion of the second layer defines the layout of the metallization layer and the contact vias. The first and second layers are electroplated by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the layers in a solution containing metal ions. The voltage and surface potentials are selected such that the metal ions are deposited on the remaining portions of the second layer. Further, metal ions deposited on the first layer during a positive duty cycle are removed from the first layer during a negative duty cycle. Finally, exposed portions of the first layer are selectively removed.
摘要翻译：一种形成金属化层的方法。第一层从半导体衬底向外形成。通过第一层到半导体衬底形成接触通孔。第二层从第一层向外形成。选择性地去除第二层的部分，使得第二层的剩余部分限定了金属化层和接触孔的布局。通过将具有正占空比和负占空比的双极调制电压施加到含有金属离子的溶液中的层来电镀第一层和第二层。选择电压和表面电位使得金属离子沉积在第二层的剩余部分上。此外，在负占空比期间，在正占空比期间沉积在第一层上的金属离子在第一层中被去除。最后，选择性地去除第一层的暴露部分。

79. 发明授权

US06753253B1 Method of making wiring and logic corrections on a semiconductor device by use of focused ion beams 失效
标题翻译：通过使用聚焦离子束在半导体器件上进行布线和逻辑校正的方法
公开(公告)号：US06753253B1
公开(公告)日：2004-06-22
申请号：US07584180
申请日：1990-09-18
申请人： Takahiko Takahashi , Fumikazu Itoh , Akira Shimase , Mikio Hongo , Satoshi Haraichi , Hiroshi Yamaguchi
发明人： Takahiko Takahashi , Fumikazu Itoh , Akira Shimase , Mikio Hongo , Satoshi Haraichi , Hiroshi Yamaguchi
IPC分类号： H01L2144
CPC分类号： H01L23/544 , H01J37/304 , H01J37/3056 , H01J2237/30466 , H01J2237/31749 , H01L21/32051 , H01L21/768 , H01L21/76879 , H01L21/76888 , H01L21/76892 , H01L21/76894 , H01L22/22 , H01L23/525 , H01L23/5254 , H01L23/552 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/45 , H01L2223/5442 , H01L2223/54426 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05027 , H01L2224/05554 , H01L2224/05572 , H01L2224/11 , H01L2224/1147 , H01L2224/13 , H01L2224/13099 , H01L2224/13111 , H01L2224/16225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48463 , H01L2224/73204 , H01L2224/73253 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01011 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/0105 , H01L2924/01057 , H01L2924/01065 , H01L2924/01068 , H01L2924/01072 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/10329 , H01L2924/12032 , H01L2924/12036 , H01L2924/1204 , H01L2924/12044 , H01L2924/1305 , H01L2924/14 , H01L2924/15312 , H01L2924/181 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025 , Y10S438/94 , H01L2924/00014 , H01L2924/00 , H01L2224/05552 , H01L2924/00012
摘要： Herein disclosed are a variety of techniques relating to the wiring and logic corrections on a chip by making use of the focused ion beam (which is shortly referred to as “FIB”) or the laser selection metal CVD. The time periods for the wiring corrections and for debugging and developing an electronic system are shortened by making use of the processing characteristics of the FIB. Illustratively, a hole is bored in an insulating film above a portion of a wiring which is to be connected to another wiring by means of a focused ion beam. The inside of the hole and a predetermined region on the insulating film are irradiated with either a laser beam or an ion beam in a metal compound gas to deposit metal in the hole and on said region and a connecting wiring is formed by means of optically pumped CVD. The present invention also relates to an IC or VLSI structure having a trial cutting region, at test etching region and an auxiliary wiring or pad, suitable for the application of such defect correction and circuit change, as well as a method of making same, a designing method using such technique, and a focused ion beam system and other systems for use in those methods.
摘要翻译：这里公开了通过利用聚焦离子束（其被简称为“FIB”）或激光选择金属CVD与芯片上的布线和逻辑校正有关的各种技术。通过利用FIB的处理特性，缩短布线校正和调试开发电子系统的时间。示例性地，在通过聚焦离子束连接到另一布线的布线的一部分上方的绝缘膜中钻孔。在绝缘膜的内部和绝缘膜上的预定区域用金属化合物气体中的激光束或离子束照射以在孔中和所述区域上沉积金属，并且通过光泵浦形成连接布线 CVD。本发明还涉及一种IC或VLSI结构，其具有在测试蚀刻区域处的试验切割区域和适于应用这种缺陷校正和电路改变的辅助布线或焊盘，以及其制造方法使用这种技术的设计方法，以及用于这些方法的聚焦离子束系统和其它系统。

80. 发明授权

US06753206B2 Dual-chip integrated circuit package with unaligned chip arrangement and method of manufacturing the same 失效
标题翻译：具有未对准芯片布置的双芯片集成电路封装及其制造方法
公开(公告)号：US06753206B2
公开(公告)日：2004-06-22
申请号：US10289796
申请日：2002-11-07
申请人： Chien-Ping Huang , Lian-Cherng Chiang , Michael Chang
发明人： Chien-Ping Huang , Lian-Cherng Chiang , Michael Chang
IPC分类号： H01L2144
CPC分类号： H01L23/4951 , H01L23/3107 , H01L23/49575 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/32014 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48639 , H01L2224/48739 , H01L2224/48839 , H01L2224/49171 , H01L2224/73215 , H01L2224/73265 , H01L2224/85439 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01079 , H01L2924/10161 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A dual-chip integrated circuit package with unaligned chip arrangement and a method of manufacturing such a dual-chip integrated circuit package are provided. The dual-chip integrated circuit package includes a leadframe having a first set of leads and a second set of leads. The dual-chip integrated circuit package is used to pack two integrated circuit chips in an unaligned chip arrangement, in which the first integrated circuit chip is mounted to one side of the inner part of the first set of leads, and the second integrated circuit chip is mounted to the other side of the same in such a manner as to allow the bonding pads on the second integrated circuit chip to be positioned in the spacing formed between the two sets of leads. This unaligned chip arrangement can help facilitate the wire-bonding process for the bonding pads on the second integrated circuit chip. An encapsulant is used for encapsulating the first integrated circuit chip, the second integrated circuit chip, the first set of bonding wires, the second set of bonding wires, the inner part of the first set of leads, and the inner part of the second set of leads. The particular structure of the dual-chip integrated circuit package allows no restriction to the relative size between the two integrated circuit chips, thus allowing flexible selection for the combination of the two integrated circuit chips. Moreover, the dual-chip integrated circuit package can help save layout space on the circuit board and offers more functionality and storage capacity.
摘要翻译：提供了具有未对准芯片布置的双芯片集成电路封装以及制造这种双芯片集成电路封装的方法。双芯片集成电路封装包括具有第一组引线和第二组引线的引线框架。双芯片集成电路封装用于以未对准的芯片布置来封装两个集成电路芯片，其中第一集成电路芯片安装在第一组引线的内部的一侧，第二集成电路芯片以这样的方式安装到其另一侧，即允许第二集成电路芯片上的接合焊盘定位在两组引线之间形成的间隔中。这种未对准的芯片布置可以帮助促进第二集成电路芯片上的焊盘的引线接合工艺。密封剂用于封装第一集成电路芯片，第二集成电路芯片，第一组接合线，第二组接合线，第一组引线的内部和第二组的内部的领导。双芯片集成电路封装的特定结构不会限制两个集成电路芯片之间的相对尺寸，因此允许灵活选择两个集成电路芯片的组合。此外，双芯片集成电路封装可以帮助节省电路板上的布局空间，并提供更多功能和存储容量。

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