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71. 发明申请

US20030116798A1 Semiconductor device having trench capacitor and method for fabricating the same 失效
标题翻译：具有沟槽电容器的半导体器件及其制造方法
公开(公告)号：US20030116798A1
公开(公告)日：2003-06-26
申请号：US10329096
申请日：2002-12-23
发明人： Cheol Soo Park
IPC分类号： H01L027/108 , H01L029/76 , H01L029/94 , H01L031/119
CPC分类号： H01L27/1087 , H01L27/10832 , H01L29/66181 , H01L29/945
摘要： A semiconductor device and a method for fabricating the same. The device comprises a silicon substrate having a conductive well; a trench formed in the conductive well; a plate electrode formed on the sidewall of the trench; a capacitor insulating film and a storage node electrode; a first storage node connector formed on the storage node electrode; an insulating film formed on the first storage node connector; a silicon layer formed on the entire structure; word lines formed on the silicon layer; source and drain regions formed in the silicon layer; a contact hole, formed in the silicon layer and the insulating film, such that the first storage node connector and the source region are exposed; and a second storage node connector, formed in the contact hole, such that the source region and the first storage node connector are connected to each other.
摘要翻译：一种半导体器件及其制造方法。该器件包括具有导电阱的硅衬底; 导电孔中形成的沟槽; 形成在沟槽的侧壁上的平板电极; 电容绝缘膜和存储节点电极; 形成在所述存储节点电极上的第一存储节点连接器; 形成在所述第一存储节点连接器上的绝缘膜; 形成在整个结构上的硅层; 形成在硅层上的字线; 源极和漏极区域形成在硅层中; 形成在所述硅层和所述绝缘膜中的接触孔，使得所述第一存储节点连接器和所述源极区域被暴露; 以及形成在所述接触孔中的第二存储节点连接器，使得所述源区域和所述第一存储节点连接器彼此连接。

72. 发明申请

US20030116795A1 Method of manufacturing a tantalum pentaoxide - aluminum oxide film and semiconductor device using the film 审中-公开
标题翻译：五氧化钽 - 氧化铝膜的制造方法和使用该膜的半导体器件
公开(公告)号：US20030116795A1
公开(公告)日：2003-06-26
申请号：US10286976
申请日：2002-11-04
发明人： Kwang Chul Joo
IPC分类号： H01L021/8242 , H01L027/108 , H01L029/76 , H01L031/119
CPC分类号： H01L21/02178 , C23C16/40 , C23C16/56 , H01L21/02183 , H01L21/02194 , H01L21/02271 , H01L21/02304 , H01L21/0234 , H01L21/02356 , H01L21/31604 , H01L21/3162 , H01L21/31683
摘要： The present invention relates to a method of manufacturing a TA2O5nullAL2O3 film and a semiconductor device using the film. Chemical vapor of a Ta component, chemical vapor of an Al component and an excess O2 gas are surface-chemical-reacted within a LPCVD chamber to form a (Ta2O5)1nullXnull(Al2O3)X film of an amorphous state on a substrate. The (Ta2O5)1nullXnull(Al2O3)X film of the amorphous state is annealed to form a (Ta2O5)1nullXnull(Al2O3)X film of a crystal state that has a high dielectric constant and a stable stoichiometry compared to an existing Ta2O5 film. At this time, the crystal (Ta2O5)1nullXnull(Al2O3)X is applied to the semiconductor device.
摘要翻译：本发明涉及一种制造TA2O5-AL2O3薄膜的方法和使用该薄膜的半导体器件。 Ta组分的化学气体，Al组分的化学气体和过量的O 2气体在LPCVD室内进行表面化学反应，以在衬底上形成非晶状态的（Ta 2 O 5）1-X-（Al 2 O 3）X膜。将非晶态的（Ta 2 O 5）1-X-（Al 2 O 3）X膜退火，形成具有高介电常数和稳定化学计量比的（Ta 2 O 5）1-X-（Al 2 O 3）X膜，现有的Ta2O5薄膜。此时，将晶体（Ta 2 O 5）1-X-（Al 2 O 3）X施加到半导体器件。

73. 发明申请

US20030111690A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20030111690A1
公开(公告)日：2003-06-19
申请号：US10075236
申请日：2002-02-15
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kanna Adachi
IPC分类号： H01L029/76 , H01L029/94 , H01L031/062 , H01L031/113 , H01L031/119
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L29/7833
摘要： An aspect of the present invention includes: a gate insulating layer formed on an n-type silicon semiconductor region; a gate electrode formed on the gate insulating layer; a channel region formed immediately below the gate electrode in the semiconductor region; p-type source/drain regions formed at both sides of the channel region in the semiconductor region; p-type diffusion layer regions formed between the channel region and the source/drain regions in the semiconductor region and having a lower impurity concentration than the source/drain regions; first impurity regions formed near surface portions of the diffusion layer regions; and second impurity regions formed in part of the p-type diffusion layer regions and near surface portions of the source/drain regions, the second impurity regions being deeper than the first impurity regions, the first and second impurity regions containing one element selected from germanium, silicon, gallium, and indium as impurity.
摘要翻译：本发明的一个方面包括：形成在n型硅半导体区域上的栅极绝缘层; 形成在所述栅极绝缘层上的栅电极; 形成在半导体区域中的栅电极正下方的沟道区; 形成在半导体区域中的沟道区域的两侧的p型源极/漏极区域; 形成在半导体区域中的沟道区域和源极/漏极区域之间并且具有比源极/漏极区域更低的杂质浓度的p型扩散层区域; 形成在扩散层区域的表面部附近的第一杂质区域; 以及形成在所述p型扩散层区域和所述源极/漏极区域的近表面部分的一部分中的第二杂质区域，所述第二杂质区域比所述第一杂质区域深，所述第一和第二杂质区域包含选自锗，硅，镓和铟作为杂质。

74. 发明申请

US20030111681A1 Semiconductor memory device and its manufacturing method 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20030111681A1
公开(公告)日：2003-06-19
申请号：US10075464
申请日：2002-02-15
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shigeru Kawanaka
IPC分类号： H01L027/108 , H01L029/76 , H01L029/94 , H01L031/119 , H01L027/01 , H01L027/11
CPC分类号： H01L21/84 , G11C11/405 , H01L27/108 , H01L27/11 , H01L27/1203 , H01L29/7841
摘要： According to one aspect of the present invention, a semiconductor memory device has: a semiconductor layer formed on an insulating film; and a memory cell array including a matrix arrangement of a plurality of memory cells each made up of first and second transistors connected in series, one side of each memory cell being connected to a bit line and the other side of each memory cell being supplied with a reference potential, and according to another aspect of the present invention, a semiconductor memory device manufacturing method includes: forming an oxide layer and a silicon active layer on a semiconductor substrate; forming an element isolation region for separating said silicon active layer into discrete element-forming regions to be substantially flush with said silicon active layer; forming gate electrode of paired two transistors by depositing a gate electrode material on said silicon active layer and patterning it; injecting predetermined ions into a region for forming a diffusion layer in, using said gate electrodes as an ion injection mask; forming said paired transistors by activating the injected ions through a heat process; and forming a first gate line connected to the gate electrode of one of said paired transistors and a second gate line connected to the gate electrode of the other of said paired transistors.
摘要翻译：根据本发明的一个方面，半导体存储器件具有：形成在绝缘膜上的半导体层; 以及包括由串联连接的第一和第二晶体管构成的多个存储单元的矩阵排列的存储单元阵列，每个存储单元的一侧连接到位线，并且每个存储单元的另一侧被提供参考电位，并且根据本发明的另一方面，半导体存储器件制造方法包括：在半导体衬底上形成氧化物层和硅有源层; 形成用于将所述硅有源层分离成离散元件形成区域以与所述硅有源层基本齐平的元件隔离区; 通过在所述硅有源层上沉积栅极材料并对其进行构图来形成成对的两个晶体管的栅电极; 将所述栅极用作离子注入掩模，将预定离子注入用于形成扩散层的区域中; 通过热过程激活注入的离子来形成所述成对晶体管; 以及形成连接到所述成对晶体管之一的栅极的第一栅极线和连接到所述成对晶体管中另一个的栅电极的第二栅极线。

75. 发明申请

US20030102510A1 Molecular detection chip including mosfet , molecular detection device employing the chip, and molecular detection method using the device 失效
标题翻译：分子检测芯片包括mosfet，采用该芯片的分子检测装置，以及使用该装置的分子检测方法
公开(公告)号：US20030102510A1
公开(公告)日：2003-06-05
申请号：US10239736
申请日：2002-09-25
发明人： Geun-Bae Lim , Chin-Sung Park , Yoon-Kyoung Cho , Sun-Hee Kim
IPC分类号： H01L029/76 , H01L029/94 , H01L031/062 , H01L031/113 , H01L031/119
CPC分类号： G01N33/5438 , B01J2219/00497 , B01J2219/00511 , B01J2219/00585 , B01J2219/00596 , B01J2219/00653 , B01J2219/00657 , B01J2219/00659 , B01J2219/00677 , B01J2219/00722 , B01J2219/00725 , B01J2219/00729 , B01J2219/00731 , B01J2219/00743 , B01L3/5027 , B82Y15/00 , B82Y30/00 , C12Q1/6837 , G01N27/4145 , G01N33/54373 , C12Q2565/607
摘要： A molecular detection chip including a metal oxide silicon-field effect transistor (MOSFET) on sidewalls of a micro-fluid channel and a molecular detection device including the molecular detection chip are provided. A molecular detection method, particularly, qualification methods for the immobilization of molecular probes and the binding of a target sample to the molecular probes, using the molecular detection device, and a nucleic acid mutation assay device and method are also provided. The formation of the MOSFET on the sidewalls of the micro-fluid channel makes easier to highly integrate a molecular detection chip. In addition, immobilization of probes directly on the surface of a gate electrode ensures the molecular detection chip to check for the immobilization of probes and coupling of a target molecule to the probes in situ.
摘要翻译：提供了包括在微流体通道的侧壁上的金属氧化物硅场效应晶体管（MOSFET）和包括分子检测芯片的分子检测装置的分子检测芯片。还提供了使用分子检测装置的分子检测方法，特别是用于固定分子探针的鉴定方法和靶样品与分子探针的结合，以及核酸突变测定装置和方法。在微流体通道的侧壁上形成MOSFET更容易高度集成分子检测芯片。此外，探针直接固定在栅电极的表面上确保了分子检测芯片，以检查探针的固定和目标分子与探针原位偶联。

76. 发明申请

US20030094659A1 METHOD OF FABRICATING DUAL THRESHOLD VOLTAGE N-CHANNEL AND P-CHANNEL MOSFETS WITH A SINGLE EXTRA MASKED IMPLANT OPERATION 有权
标题翻译：双路阈值电压N沟道和P沟道MOSFET的单一外部嵌入式植入操作的方法
公开(公告)号：US20030094659A1
公开(公告)日：2003-05-22
申请号：US09443056
申请日：1999-11-18
发明人： KAIZAD R. MISTRY , IAN R. POST
IPC分类号： H01L029/76 , H01L029/94 , H01L021/8238 , H01L031/119
CPC分类号： H01L21/823807
摘要： A method of forming an MOS integrated circuit having at least two types of NFET, each type having a different threshold voltage, and at least two types of PFET, each type having a different threshold voltage, includes forming at least four active regions in a substrate, each region having a different doping profile. A conventional two threshold voltage CMOS process is modified to produce four transistor threshold voltages with only one additional masked implant operation. This additional implant raises the threshold voltage of one type of MOSFET while lowering that of the other MOSFET type.
摘要翻译：一种形成MOS集成电路的方法，其具有至少两种类型的具有不同阈值电压的NFET，并且每种类型具有不同阈值电压的至少两种类型的PFET包括在衬底中形成至少四个有源区域，每个区域具有不同的掺杂分布。修改传统的两个阈值电压CMOS工艺以仅产生一个附加的掩模注入操作来产生四个晶体管阈值电压。这种额外的注入提高了一种类型MOSFET的阈值电压，同时降低了另一种MOSFET类型的阈值电压。

77. 发明申请

US20030092287A1 Process for forming hafnium oxide films 有权
标题翻译：形成氧化铪膜的方法
公开(公告)号：US20030092287A1
公开(公告)日：2003-05-15
申请号：US09992173
申请日：2001-11-14
发明人： Ryan C. Smith , Tiezhong Ma , Stephen A. Campbell , Wayne L. Gladfelter
IPC分类号： H01L021/336 , H01L029/76 , H01L029/94 , H01L031/062 , H01L031/113 , H01L031/119 , H01L021/3205 , H01L021/4763 , H01L021/469 , H01L021/31
CPC分类号： H01L21/02181 , C23C16/405 , H01L21/02205 , H01L21/02271 , H01L21/28202 , H01L21/31604 , H01L29/518
摘要： A process for forming a hafnium oxide-containing film on a substrate such as silicon that includes introducing an anhydrous hafnium nitrate-containing precursor into a reactor containing the substrate, and converting the precursor into the hafnium oxide-containing film on the substrate by chemical vapor deposition.
摘要翻译：一种在诸如硅的衬底上形成含氧化铪的膜的方法，包括将含无水硝酸铪的前体引入含有衬底的反应器中，并通过化学气相将所述前体转化为所述衬底上的含氧化铪膜沉积

78. 发明申请

US20030089937A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20030089937A1
公开(公告)日：2003-05-15
申请号：US10100075
申请日：2002-03-19
申请人： FUJITSU LIMITED
发明人： Hideaki Yamauchi , Daisuke Matsubara
IPC分类号： H01L027/108 , H01L029/76 , H01L029/94 , H01L031/119
CPC分类号： H01L28/40 , H01L23/5223 , H01L23/5225 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device comprises a semiconductor substrate 10; a capacitor element 40 formed above the semiconductor substrate and including a lower electrode 34, a capacitor insulation film 36 formed on the lower electrode and an upper electrode 38 formed on the capacitor insulation film; a shield layer 14; 58 formed at least either of above and below the capacitor element; and a lead-out interconnection layer 22; 50 formed between the capacitor element and the shield layer and electrically connected to the lower electrode or the upper electrode, a plurality of holes 16, 60 being formed in each of the shield layer and the lead-out interconnection layer. The shield layers are formed above and below the MIM capacitor, whereby combination of noises with the MIM capacitor can be prevented.
摘要翻译：半导体器件包括半导体衬底10; 形成在半导体衬底上方的电容器元件40，包括下电极34，形成在下电极上的电容器绝缘膜36和形成在电容器绝缘膜上的上电极38; 屏蔽层14; 58形成在电容器元件的上方和下方的至少任一个; 和引出互连层22; 50形成在电容器元件和屏蔽层之间并电连接到下电极或上电极，多个孔16,60形成在每个屏蔽层和引出互连层中。在MIM电容器的上下形成有屏蔽层，由此可以防止与MIM电容器的噪声的组合。

79. 发明申请

US20030089933A1 Cladding of a conductive interconnect for programming a MRAM device using multiple magnetic layers 失效
标题翻译：用于使用多个磁性层编程MRAM器件的导电互连的包层
公开(公告)号：US20030089933A1
公开(公告)日：2003-05-15
申请号：US10010363
申请日：2001-11-13
发明人： Jason Allen Janesky , Nicholas D. Rizzo , Bradley N. Engel
IPC分类号： H01L021/00 , H01L029/76 , H01L031/062 , H01L029/94 , H01L031/119 , H01L031/113
CPC分类号： H01L27/222 , G11C11/16
摘要： A cladded conductive interconnect for programming a magnetoresistive memory device which includes a conductive material with a length, a first barrier conductive material positioned on the conductive material, and a multi-layer cladding region positioned along the length of the conductive material wherein the multi-layer cladding region includes N ferromagnetic layers, where N is a whole number greater than or equal to two, and wherein the multi-layer cladding region further includes at least one spacer layer, wherein the spacer layer can include a metal, an insulator, or an exchange interaction material, and wherein the spacer layer is sandwiched therebetween each adjacent ferromagnetic layer.
摘要翻译：一种用于编程磁阻存储器件的包覆导电互连件，其包括具有长度的导电材料，位于导电材料上的第一阻挡导电材料，以及沿导电材料的长度定位的多层包覆区域，其中多层包层区域包括N个铁磁层，其中N是大于或等于2的整数，并且其中所述多层包覆区域还包括至少一个间隔层，其中所述间隔层可以包括金属，绝缘体或交换相互作用材料，并且其中间隔层夹在每个相邻的铁磁层之间。

80. 发明申请

US20030085429A1 Triggering of an ESD NMOS through the use of an N-type buried layer 失效
标题翻译：通过使用N型掩埋层来触发ESD NMOS
公开(公告)号：US20030085429A1
公开(公告)日：2003-05-08
申请号：US10280313
申请日：2002-10-25
发明人： Ronald B. Hulfachor
IPC分类号： H01L029/76 , H01L031/062 , H01L031/119 , H01L031/113 , H01L029/94
CPC分类号： H01L27/0277
摘要： An ESD NMOS structure with an odd number of N-type structures built into a P-type well. Buried N-type structures are positioned between the N-type structures. The center N-type structure and each alternate N-type structure are electrically connected to each other, to the buried N-type structures, and to the output contact; while the other N-type structures are electrically connected to each other and the P-well and to ground. When a positive ESD event occurs, a depletion zone is created in the P-well between the N-type buried structures and the N-type structures thereby increasing the resistivity of the structure. Moreover, when a positive ESD event occurs, the lateral NPN transistors on either side of the center N-type structure break down and snap back. The resulting current travels through the area of increased resistivity and thereby creates a larger voltage along the P-well from the center N-type structure out toward the distal N-type structures. The combination of the increased resistivity and the higher voltage act in combination to lower the triggering voltage of the ESD structure.
摘要翻译：具有内置于P型阱中的奇数N型结构的ESD NMOS结构。埋置的N型结构位于N型结构之间。中心N型结构和每个交替的N型结构彼此电连接到埋入的N型结构和输出触点; 而其他N型结构彼此电连接，并且P阱和接地。当发生正的ESD事件时，在N型掩埋结构和N型结构之间的P阱中产生耗尽区，从而增加了结构的电阻率。此外，当发生正的ESD事件时，中心N型结构两侧的侧面NPN晶体管分解并回跳。所产生的电流穿过电阻率增加的区域，从而沿着P-阱从中心N型结构向远端N型结构产生更大的电压。增加的电阻率和较高电压的组合组合起来以降低ESD结构的触发电压。

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