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71. 发明授权

US4985600A Printed circuit board having an injection molded substrate 失效
标题翻译：具有注塑基板的印刷电路板
公开(公告)号：US4985600A
公开(公告)日：1991-01-15
申请号：US406551
申请日：1989-09-13
申请人： Marcel Heerman
发明人： Marcel Heerman
IPC分类号： H05K1/02 , H05K1/09 , H05K1/11 , H05K3/10 , H05K3/18 , H05K3/34 , H05K3/42
CPC分类号： H05K3/107 , H05K1/116 , H05K2201/0376 , H05K2201/09036 , H05K2201/09118 , H05K2201/09827 , H05K2201/09845 , H05K2201/09981 , H05K2203/0574 , H05K2203/1415 , H05K3/184 , H05K3/3452 , H05K3/426 , Y10T29/4916 , Y10T29/49165
摘要： A printed circuit board includes an injection molded substrate having a pattern recessed in the substrate surface of interconnect traces, through-connections and contact rods. A trench-shaped depression is provided in the substrate surface in the region of each interconnect trace, and a planar depression is provided in the substrate surface in at least one of (a) the region of each through-connection and (b) the region of each contact surface. The pattern of recesses is covered with a conductive metal coat, and the width of each trench-shaped depression is dimensioned narrowly in comparison of the width of each planar depression, so that the metal coat fills the trench-shaped depressions to the surface of the substrate, while in the planar depressions a distance remains between the metal coat and the surface of the substrate. A solder stop lacquer can then be applied, such as by roller coating, without the necessity of photo-structuring and without filling the planar depressions.
摘要翻译：印刷电路板包括注模基板，其具有在互连轨迹，通孔和接触杆的基板表面中凹陷的图案。在每个互连迹线的区域中的衬底表面中设置沟槽状的凹部，并且在（a）每个贯通连接的区域和（b）区域中的至少一个中，在衬底表面中提供平坦的凹陷部的每个接触面。凹槽的图案被导电金属涂层覆盖，并且每个沟槽状凹陷的宽度与每个平面凹陷的宽度相比较窄地尺寸，使得金属涂层将沟槽形凹陷填充到表面的凹槽衬底，而在平面凹陷中，金属涂层和衬底表面之间保留一定距离。然后可以施加阻焊漆，例如通过辊涂，而不需要光结构并且不填充平面凹陷。

72. 发明授权

US4610758A Manufacture of printed circuit boards 失效
标题翻译：印刷电路板的制造
公开(公告)号：US4610758A
公开(公告)日：1986-09-09
申请号：US615261
申请日：1984-05-30
申请人： Geoffrey C. Wilson
发明人： Geoffrey C. Wilson
IPC分类号： H05K3/00 , H05K3/06 , H05K3/24 , H05K3/34 , H05K3/42 , B05D5/12 , C23F1/02
CPC分类号： H05K3/3452 , H05K3/243 , H05K3/427 , H05K2201/0352 , H05K2201/2081 , H05K2203/0574 , H05K3/0094 , H05K3/062 , H05K3/242 , H05K3/244 , Y10S428/901 , Y10T29/49165
摘要： A method of manufacture of a printed circuit board having plated-through holes interconnecting printed conductors formed on each of two external surfaces, includes the step of masking those areas of the external surfaces where solder will subsequently be required to adhere. The unmasked conductive areas are then coated with a material which prevents wetting by normal soldering techniques. The masking material is subsequently removed. The coating material may be electroless nickel, or electroplated nickel or suitable nickel alloys.
摘要翻译：制造具有互连形成在两个外表面中的每一个上的印刷导体的具有电镀通孔的印刷电路板的方法包括掩蔽随后需要焊料粘附的外部表面的那些区域的步骤。然后将未掩蔽的导电区域涂覆防止通过正常焊接技术润湿的材料。随后除去掩蔽材料。涂层材料可以是无电镍，或电镀镍或合适的镍合金。

73. 发明授权

US4312897A Buried resist technique for the fabrication of printed wiring 失效
标题翻译：用于制造印刷线路的掩埋抗蚀剂技术
公开(公告)号：US4312897A
公开(公告)日：1982-01-26
申请号：US157595
申请日：1980-06-09
申请人： William G. Reimann
发明人： William G. Reimann
IPC分类号： H05K1/02 , H05K3/06 , H05K3/10 , H05K3/24 , H05K3/34 , H05K3/42 , H05K3/18
CPC分类号： H05K3/243 , H05K1/0265 , H05K3/062 , H05K3/427 , H05K2201/0341 , H05K2201/0367 , H05K2201/09736 , H05K2203/0384 , H05K2203/0574 , H05K3/108 , H05K3/3473
摘要： Narrow conductors and narrow spaces therebetween, typically two or three mils wide, are fabricated on outer layers of a printed wiring board with built-up areas such as plated-through holes or conductors of widths greater than two or three mils. Gold is deposited over a copper clad substrate in a pattern defining the desired circuitry. Thereafter, solder is placed at the built-up areas and, using both the solder and the gold as resist or masks, the exposed copper is removed by etching. An organic resist material is used in lieu of solder when the built-up area comprises wide conductors or leads, e.g., power busses.
摘要翻译：典型地为2或3密耳宽的窄导体和狭窄的空间被制造在印刷线路板的外层上，其具有诸如电镀通孔或宽度大于2或3密耳的导体的组合区域。金以限定所需电路的图案沉积在铜包覆基板上。此后，将焊料放置在积聚区域，并且使用焊料和金作为抗蚀剂或掩模，通过蚀刻去除暴露的铜。当组合区域包括宽导体或引线（例如功率总线）时，使用有机抗蚀剂材料代替焊料。

74. 发明授权

US4268614A Method of making printed circuit board 失效
标题翻译：制作印刷电路板的方法
公开(公告)号：US4268614A
公开(公告)日：1981-05-19
申请号：US967388
申请日：1978-12-07
申请人： Tamotsu Ueyama , Yukihiko Wada , Masaji Homma , Hitoshi Aisawa , Takayoshi Komatsu , Tatsuhisa Shibata , Hiroharu Kamiyama
发明人： Tamotsu Ueyama , Yukihiko Wada , Masaji Homma , Hitoshi Aisawa , Takayoshi Komatsu , Tatsuhisa Shibata , Hiroharu Kamiyama
IPC分类号： H05K3/18 , H05K3/42 , G03C5/00
CPC分类号： H05K3/184 , H05K3/42 , H05K3/428 , H05K2203/025 , H05K2203/0565 , H05K2203/0574 , H05K2203/1383
摘要： A novel circuit board in which circuit portions including pad portions, through-hole portions and conductors are formed, at least at the pad portions and the through-hole portions of the circuit, in the vacant portions defined by a cured photopolymeric resin composition and the vacant portions are plated with electroless copper. When only the pad portions and through-hole portions are plated with electroless copper, the conductors are all covered with the resin composition, thereby enabling fears of mechanical and chemical damages to be eliminated. When all the circuit portions are plated with electroless copper, the amount of copper required can be considerably reduced.Such circuit board is prepared by applying onto a laminate with or without copper clad thereon a specific photopolymerizable resin composition, irradiating the resin composition-applied laminate with ultraviolet rays through a pattern mask, treating the thus irradiated laminate with a solvent to remove the unexposed portions of resin composition and applying an electroless copper plating to the unexposed portions. A durable and reliable printed circuit board having a high pecision and high density circuit pattern can be provided very simply, easily at low cost.
摘要翻译：一种新颖的电路板，其中，在由固化的光聚合树脂组合物限定的空位部分中至少在电路的焊盘部分和通孔部分处形成包括焊盘部分，通孔部分和导体的电路部分，空位部分镀有化学镀铜。当只有焊盘部分和通孔部分镀有无电镀铜时，导体都被树脂组合物覆盖，从而可以消除机械和化学损坏的恐惧。当所有电路部分都镀有化学镀铜时，所需的铜的量可以大大降低。通过在具有或不具有铜的层压板上涂布特定的光聚合性树脂组合物，通过图案掩模对紫外线照射树脂组合物施加的层压体，用溶剂处理这样照射的层压体以除去未曝光部分来制备这种电路板的树脂组合物，并对未曝光部分施加化学镀铜。可以非常简单，容易地以低成本提供具有高精度和高密度电路图案的耐用且可靠的印刷电路板。

75. 发明授权

US3745094A Two resist method for printed circuit structure 失效
标题翻译：印刷电路结构的两种电阻方法
公开(公告)号：US3745094A
公开(公告)日：1973-07-10
申请号：US3745094D
申请日：1971-03-26
申请人： IBM
发明人： GREENE K
IPC分类号： H05K3/06 , H05K3/10 , H05K3/24 , H05K3/40 , H05K3/46
CPC分类号： H05K3/243 , H05K3/062 , H05K3/108 , H05K3/4007 , H05K3/4647 , H05K2201/0367 , H05K2201/09472 , H05K2201/09736 , H05K2203/0574 , H05K2203/0588 , H05K2203/0733
摘要： AN IMPROVED METHOD IS PROVIDED FOR PLATING CONDUCTIVE MATERIAL IN A PREDETERMINED PATTERN ON A CONDUCTIVE LAYER THAT IS THEREAFTER ETCHED TO THE SAME PATTERN AS THE PLATED MATERIAL OR IS ETCHED TO THE PATTERN THAT EXTENDS BEYOND THE REGION OF PLATING. TWO LAYERS OF PHOTOSENSITIVE RESIST ARE APPLIED ONE OVER THE OTHER TO THE CONDUCTIVE LAYER. THE FIRST OR INNERMOST RESIST LAYER IS DEVELOPED TO MASK THE CONDUCTIVE LAYER IN THE AREAS THAT ARE LATER TO BE REMOVED BY ETCHING. THE SECOND RESIST LAYER IS DEVELOPED TO EXPOSE REGIONS OF THE CONDUCTIVE LAYER THAT ARE TO BE PLATED. AFTER THE PLATING HAS BEEN COMPLETED, THE SECOND RESIST IS REMOVED. THE STRUCTURE IS THEN PLATED WITH AN ETCH RESISTANT METAL IN AREAS NOT MASKED BY THE FIRST RESIST. THE FIRST RESIST IS REMOVED AND THE UNWANTED REGIONS OF THE CONDUCTIVE LAYER ARE ETCHED AWAY. THIS METHOD IS PARTICULARLY USEFUL FOR PLATING CONDUCTIVE STUDS IN A MULTI-LAYER PRINTED CIRCUIT STRUCTURE. THE SIDES OF THE STUDS ARE PROTECTED BY THE PLATED RESIST TO PREVENT THE STUDS FROM BEING ETCHED IN THE ETCH STEP.

76. 发明授权

US2872391A Method of making plated hole printed wiring boards 失效
标题翻译：电镀孔印刷电路板的制造方法
公开(公告)号：US2872391A
公开(公告)日：1959-02-03
申请号：US51846255
申请日：1955-06-28
申请人： IBM
发明人： HAUSER JOHN H , LORENZ EDWARD J
IPC分类号： A63G7/00 , B29B11/14 , H05K3/04 , H05K3/06 , H05K3/42
CPC分类号： H05K3/427 , B29B11/14 , H05K3/048 , H05K3/062 , H05K2201/0305 , H05K2203/0191 , H05K2203/0264 , H05K2203/0574 , H05K2203/1383

77. 发明公开

US20240164028A1 PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD FOR THE SAME 审中-公开
公开(公告)号：US20240164028A1
公开(公告)日：2024-05-16
申请号：US18218753
申请日：2023-07-06
申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.
发明人： Seon Ha Kang , Seung Eun Lee , Yong Hoon Kim
IPC分类号： H05K3/46 , H05K1/03 , H05K1/11 , H05K3/00 , H05K3/12
CPC分类号： H05K3/4688 , H05K1/03 , H05K1/115 , H05K3/0017 , H05K3/1258 , H05K2201/09045 , H05K2203/0574
摘要： A printed circuit board including a first insulating layer; a plurality of first circuit patterns respectively disposed on the first insulating layer; and a plurality of second circuit patterns respectively disposed on the first insulating layer and respectively having a thickness, thinner than a thickness of each of the plurality of first circuit patterns. At least one of the plurality of first circuit patterns and at least one of the plurality of second circuit patterns are alternately and repeatedly arranged, and a method for manufacturing the printed circuit board, are provided.

78. 发明公开

US20240015888A1 WIRING BOARD 审中-公开
公开(公告)号：US20240015888A1
公开(公告)日：2024-01-11
申请号：US18347086
申请日：2023-07-05
申请人： SHINKO ELECTRIC INDUSTRIES CO., LTD.
发明人： Kensuke UCHIDA
IPC分类号： H05K1/11 , H05K1/02 , H05K3/28 , H01L23/495
CPC分类号： H05K1/115 , H05K1/0298 , H05K3/284 , H01L23/49575 , H05K2203/0574 , H05K2203/049
摘要： A wiring board includes a first interconnect structure including a first interconnect layer and a first insulating layer, and a second interconnect structure, including a second interconnect layer and a second insulating layer, and disposed on the first interconnect structure. Interconnect width and spacing of the second interconnect layer are smaller than those of the first interconnect layer. The first insulating layer covers a side surface of the first interconnect layer and exposes an upper surface of the first interconnect layer. The second insulating layer covers the upper surface of the first interconnect layer and an upper surface of the first insulating layer. The first insulating layer and the second insulating layer include a filler. An average grain diameter and a maximum grain diameter of the filler included in the second insulating layer are smaller than those of the filler included in the first insulating layer.

79. 发明申请

US20170142828A1 DUMMY CORE PLUS PLATING RESIST RESTRICT RESIN PROCESS AND STRUCTURE 审中-公开
公开(公告)号：US20170142828A1
公开(公告)日：2017-05-18
申请号：US14995087
申请日：2016-01-13
申请人： Multek Technologies Limited
发明人： Pui Yin Yu , Mark Zhang , Jiawen Chen
IPC分类号： H05K1/02 , H05K3/18 , H05K3/06 , H05K1/11 , H05K3/46
CPC分类号： H05K1/0278 , H05K1/0298 , H05K1/115 , H05K3/067 , H05K3/181 , H05K3/4611 , H05K3/4691 , H05K2203/0228 , H05K2203/0574 , H05K2203/06 , H05K2203/308
摘要： A printed circuit board (PCB) has multiple layers, where select portions of inner layer circuitry, referred to as inner core circuitry, are exposed from the remaining layers. The PCB having an exposed inner core circuitry is formed using a dummy core plus plating resist process. The select inner core circuitry is part of an inner core. The inner core corresponding to the exposed inner core circuitry forms a semi-flexible PCB portion. The semi-flexible PCB portion is an extension of the remaining adjacent multiple layer PCB. The remaining portion of the multiple layer PCB is rigid. The inner core is common to both the semi-flexible PCB portion and the remaining rigid PCB portion.

80. 发明授权

US09301391B2 Substrate structure, semiconductor package device, and manufacturing method of substrate structure 有权
标题翻译：基板结构，半导体封装器件和衬底结构的制造方法
公开(公告)号：US09301391B2
公开(公告)日：2016-03-29
申请号：US13689207
申请日：2012-11-29
申请人： ADVANPACK SOLUTIONS PTE LTD.
发明人： Hwee-Seng Jimmy Chew , Shoa-Siong Raymond Lim
IPC分类号： H01L23/48 , H05K1/09 , H01L21/02 , H05K1/03 , H01L23/498 , H01L21/48 , H01L23/31
CPC分类号： H01L21/4857 , C25D5/022 , C25D7/12 , H01L21/02697 , H01L21/0273 , H01L21/2885 , H01L21/486 , H01L23/3107 , H01L23/48 , H01L23/49838 , H01L23/49861 , H01L23/49866 , H01L23/49894 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H05K1/0373 , H05K1/09 , H05K1/092 , H05K2201/09118 , H05K2203/0574 , H01L2924/00012 , H01L2924/00
摘要： A substrate structure includes first, second and third metal layers embedded in a dielectric layer between its opposite upper first and lower second surfaces. The entire upper surface of the first metal layer is exposed on the first surface of the dielectric layer, the entire lower surface of the third metal layer is exposed on the second surface of the dielectric layer, and the second metal layer is disposed between the first metal layer and the third metal layer, wherein the area of the third metal layer is larger than the area of the second metal layer.
摘要翻译：衬底结构包括在其相对的上第一和第二表面之间嵌入电介质层中的第一，第二和第三金属层。第一金属层的整个上表面暴露在电介质层的第一表面上，第三金属层的整个下表面暴露在电介质层的第二表面上，第二金属层设置在第一金属层的第一表面之间金属层和第三金属层，其中第三金属层的面积大于第二金属层的面积。

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