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71. 发明申请

US20130021058A1 SYSTEM AND METHOD FOR REDUCING RECONFIGURATION POWER USAGE 有权
公开(公告)号：US20130021058A1
公开(公告)日：2013-01-24
申请号：US13638934
申请日：2010-10-21
申请人： Randy R. Huang , Martin Voogel , Jingcao Hu , Steven Teig
发明人： Randy R. Huang , Martin Voogel , Jingcao Hu , Steven Teig
IPC分类号： H03K19/0175
CPC分类号： H03K19/0008 , G06F17/50 , G06F17/5054 , G06F17/5072 , G06F17/5077 , G06F17/5081 , G06F2217/78 , H03K19/1737 , H03K19/17748 , H03K19/17756 , H03K19/17784 , H03K19/17796
摘要： A system and method for reducing power consumption in a reconfigurable integrated circuit. Some embodiments provide placement and routing programs that reduce the number of bits to be reconfigured. Some embodiments provide placement and routing programs that increase the number of groups of circuits that do not need reconfiguration at some times. Some embodiments include circuits that selectively block reconfiguration.

72. 发明申请

US20130009667A1 SUB-THRESHOLD FPGA AND RELATED CIRCUITS AND METHODS THEREOF 有权
标题翻译：子阈值FPGA及其相关电路及其方法
公开(公告)号：US20130009667A1
公开(公告)日：2013-01-10
申请号：US13635350
申请日：2011-03-17
申请人： Benton H. Calhoun , Joseph F. Ryan
发明人： Benton H. Calhoun , Joseph F. Ryan
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17784 , H03K19/17788
摘要： A sub-VT FPGA uses a low swing, dual-VDD interconnect scheme to reduce FPGA area per LUT, delay at a constant energy, and energy at a constant delay relative to a conventional design at low voltage. These improvements are made possible by a custom asynchronous sense amp, a separated voltage for memory cells, and an improved passgate interconnect to optimize routing delay with low energy overhead. This sub-threshold FPGA design enables energy efficient and cost effective configurable logic for a wide variety of ULP applications.
摘要翻译：子VT FPGA采用低摆幅双VDD互连方案，以降低每个LUT的FPGA面积，以恒定能量延迟，而在低电压下相对于传统设计，能够以恒定的延迟。这些改进可以通过定制的异步感测放大器，用于存储器单元的分离电压以及改进的通道互连来实现，以优化具有低能量开销的路由延迟。该子阈值FPGA设计可为各种ULP应用提供高能效且具有成本效益的可配置逻辑。

73. 发明授权

US08294489B2 Programmable logic circuit 有权
标题翻译：可编程逻辑电路
公开(公告)号：US08294489B2
公开(公告)日：2012-10-23
申请号：US12404606
申请日：2009-03-16
申请人： Tetsufumi Tanamoto , Hideyuki Sugiyama , Kazutaka Ikegami , Yoshiaki Saito
发明人： Tetsufumi Tanamoto , Hideyuki Sugiyama , Kazutaka Ikegami , Yoshiaki Saito
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , G11C13/0002 , H03K19/17764 , H03K19/1778 , H03K19/17784 , H03K19/18
摘要： A programmable logic circuit includes: an input circuit configured to receive a plurality of input signals; and a programmable cell array including a plurality of unit programmable cells arranged in a matrix form, each of the unit programmable cells including a first memory circuit of resistance change type including a first transistor and a second memory circuit of resistance change type including a second transistor, the first and second memory circuits connected in parallel, each gate of the first transistors on same row respectively receiving one input signal, each gate of the second transistors on same row receiving an inverted signal of the one input signal, output terminals of the first and second memory circuits on same column being connected to a common output line.
摘要翻译：可编程逻辑电路包括：输入电路，被配置为接收多个输入信号; 以及包括以矩阵形式布置的多个单元可编程单元的可编程单元阵列，每个单元可编程单元包括电阻改变型的第一存储器电路，包括第一晶体管和包括第二晶体管的电阻变化型的第二存储器电路并联连接的第一和第二存储器电路，同一行上的第一晶体管的每个栅极分别接收一个输入信号，同一行上的第二晶体管的每个栅极接收一个输入信号的反相信号，第一个输出端的输出端并且同一列上的第二存储器电路连接到公共输出线。

74. 发明授权

US08233577B1 Apparatus and method for routing of signals 有权
标题翻译：用于信号路由的装置和方法
公开(公告)号：US08233577B1
公开(公告)日：2012-07-31
申请号：US12555237
申请日：2009-09-08
申请人： Kerry Veenstra , Krishna Rangasayee , Robert Bielby
发明人： Kerry Veenstra , Krishna Rangasayee , Robert Bielby
IPC分类号： H04L25/40 , H04L23/00 , H03D3/24
CPC分类号： H03L7/187 , H03K19/17736 , H03K19/17744 , H03K19/17784 , H04L25/0272 , H04L25/0282
摘要： A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.
摘要翻译：信号路由装置包括用于存储一组数据信号的寄存器组。延迟锁定环产生一组相移位时钟信号。相位控制的读取电路响应于相移位的时钟信号顺序地将来自寄存器组的数据信号组传送。连接到相位控制读取电路的低压差分信号缓冲器以低电压差分信号传输数据信号。相移位的时钟信号代替更高的时钟频率，以便降低功耗。

75. 发明申请

US20120098569A1 HARDENED PROGRAMMABLE DEVICES 有权
公开(公告)号：US20120098569A1
公开(公告)日：2012-04-26
申请号：US13338701
申请日：2011-12-28
申请人： Andy L. Lee , Jeffrey T. Watt
发明人： Andy L. Lee , Jeffrey T. Watt
IPC分类号： H03K19/173
CPC分类号： H03K19/173 , G11C5/005 , H01L27/0207 , H03K19/1736 , H03K19/17784
摘要： Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data.

76. 发明授权

US08044682B2 FPGA having low power, fast carry chain 有权
标题翻译： FPGA具有功耗低，携带速度快
公开(公告)号：US08044682B2
公开(公告)日：2011-10-25
申请号：US12476155
申请日：2009-06-01
申请人： John Birkner , Andrew Ka Lab Chan
发明人： John Birkner , Andrew Ka Lab Chan
IPC分类号： H03K19/173 , H03K19/21
CPC分类号： H03K19/17736 , H03K19/0013 , H03K19/17728 , H03K19/17784
摘要： An in-FPGA carry chain is provided that does not exhibit significant leakage current. In particular, parts of the carry chain can be switched on/off when desired. In this manner, carry chain parts can have their leakage currents substantially disabled when they are not in use, thus saving power. Additionally, there is provided a carry chain whose logic is separate from the other parts (e.g., LUTs) of the logic blocks that perform the remaining arithmetic functions, and whose inputs are the input data to be added, rather than data that is output in delayed fashion from the other parts (e.g., LUTs) of the logic blocks. Such a configuration reduces latency by allowing the carry chain to operate directly on the received input data without need to wait on results from the other parts (e.g., LUTs) of the logic blocks.
摘要翻译：提供了不具有显着泄漏电流的FPGA内进位链。特别地，当需要时可以打开/关闭进位链的部分。以这种方式，携带链部件在不使用时可以使其泄漏电流基本上被禁用，从而节省电力。此外，还提供了一种进位链，其逻辑与执行剩余运算功能的逻辑块的其他部分（例如，LUT）分离，并且其输入是要添加的输入数据，而不是输出的数据来自逻辑块的其他部分（例如，LUT）的延迟时间。这样的配置通过允许进位链直接在所接收的输入数据上操作而不需要等待逻辑块的其他部分（例如，LUT）的结果来减少等待时间。

77. 发明申请

US20110175646A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110175646A1
公开(公告)日：2011-07-21
申请号：US13005557
申请日：2011-01-13
申请人： Yasuhiko TAKEMURA , Shunpei YAMAZAKI
发明人： Yasuhiko TAKEMURA , Shunpei YAMAZAKI
IPC分类号： H03K19/177
CPC分类号： H03K19/0013 , H01L27/0629 , H01L29/7869 , H01L2924/0002 , H03K17/161 , H03K19/173 , H03K19/17724 , H03K19/17736 , H03K19/1776 , H03K19/17772 , H03K19/17784 , H01L2924/00
摘要： It is an object to provide a semiconductor device in which power consumption can be reduced. It is another object to provide a highly reliable semiconductor device using a programming cell, such as a programmable logic device (PLD). In accordance with a change in a configuration of connections between basic blocks, power supply voltage furnishing to the basic blocks is changed. That is, when the structure of connections between the basic blocks is such that a basic block does not contribute to a circuit, the supply of the power supply voltage to this basic block is stopped. Further, the supply of the power supply voltage to the basic blocks is controlled using a programming cell formed using a field effect transistor whose channel formation region is formed using an oxide semiconductor, the field effect transistor having extremely low off-state current or extremely low leakage current.
摘要翻译：本发明的目的是提供能够降低功耗的半导体装置。另一个目的是提供使用诸如可编程逻辑器件（PLD）之类的编程单元的高度可靠的半导体器件。根据基本块之间的连接配置的变化，改变基本块的供电电压。也就是说，当基本块之间的连接结构使得基本块不对电路有贡献时，停止向该基本块提供电源电压。此外，使用使用使用氧化物半导体形成沟道形成区域的场效应晶体管形成的编程单元来控制对基本块的电源电压的供给，场效应晶体管具有极低的截止电流或极低漏电流。

78. 发明授权

US07893712B1 Integrated circuit with a selectable interconnect circuit for low power or high performance operation 有权
标题翻译：具有可选择的互连电路的集成电路，用于低功耗或高性能运行
公开(公告)号：US07893712B1
公开(公告)日：2011-02-22
申请号：US12556959
申请日：2009-09-10
申请人： Chin Hua Tan , Shankar Lakka , Ronald L. Cline , James B. Anderson , Wayne E. Wennekamp
发明人： Chin Hua Tan , Shankar Lakka , Ronald L. Cline , James B. Anderson , Wayne E. Wennekamp
IPC分类号： H03K19/173
CPC分类号： H03K19/17784 , H03K19/17792
摘要： An integrated circuit, such as a field programmable gate array or other configurable logic device, has an interconnect circuit selectively configurable to operate in a high-speed mode or in a low-power mode. The interconnect circuit is operable from a higher voltage supply or a lower voltage supply to change operating modes without reconfiguring data paths.
摘要翻译：诸如现场可编程门阵列或其他可配置逻辑器件的集成电路具有可选择地配置为以高速模式或低功率模式操作的互连电路。互连电路可以从较高电压电源或较低电压电源工作，以改变操作模式，而不重新配置数据路径。

79. 发明授权

US07880505B2 Low power reconfigurable circuits with delay compensation 有权
标题翻译：具有延迟补偿功能的低功率可重构电路
公开(公告)号：US07880505B2
公开(公告)日：2011-02-01
申请号：US12709227
申请日：2010-02-19
申请人： Sunil Papanchand Khatri , Sheila Vaidya , Timothy Kevin Griffin , Nikhil Jayakumar
发明人： Sunil Papanchand Khatri , Sheila Vaidya , Timothy Kevin Griffin , Nikhil Jayakumar
IPC分类号： H03K19/00
CPC分类号： H03K19/17736 , H03K19/17784
摘要： According to one aspect of the present disclosure, a circuit includes a semiconductor device including a plurality of logic blocks and a plurality of programmable interconnects. A delay detector generates a delay signal responsive to a measured delay of an output signal, wherein the output signal is from at least one of the plurality of logic blocks. A biasing circuit responsive to the delay signal to adjust subsequent measured delays toward a predetermined value.
摘要翻译：根据本公开的一个方面，电路包括包括多个逻辑块和多个可编程互连的半导体器件。响应于测量的输出信号的延迟，延迟检测器产生延迟信号，其中输出信号来自多个逻辑块中的至少一个。响应于延迟信号的偏置电路将随后的测量延迟调整到预定值。

80. 发明授权

US07839165B2 User-accessible freeze-logic for dynamic power reduction and associated methods 有权
标题翻译：用户可访问的冻结逻辑，用于动态功率降低和相关方法
公开(公告)号：US07839165B2
公开(公告)日：2010-11-23
申请号：US12577061
申请日：2009-10-09
申请人： Michael D. Hutton , Andy L. Lee
发明人： Michael D. Hutton , Andy L. Lee
IPC分类号： H03K19/173
CPC分类号： H03K19/17748 , H03K19/17784
摘要： A programmable logic device (PLD) includes a configuration circuit, and first and second freeze-logic circuits. The configuration circuit provides configuration data for configuring programmable resources of the PLD during a configuration mode of the PLD. One of the two freeze-logic circuits provides a freeze logic signal during the configuration mode of the PLD. The other freeze-logic circuit provides a freeze logic signal during a user mode of the PLD.
摘要翻译：可编程逻辑器件（PLD）包括配置电路以及第一和第二冻结逻辑电路。配置电路提供用于在PLD的配置模式期间配置PLD的可编程资源的配置数据。两个冻结逻辑电路之一在PLD的配置模式期间提供冻结逻辑信号。另一个冻结逻辑电路在PLD的用户模式期间提供冻结逻辑信号。

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