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1. 发明授权

US08912831B1 Apparatus and method for routing of signals 有权
标题翻译：用于信号路由的装置和方法
公开(公告)号：US08912831B1
公开(公告)日：2014-12-16
申请号：US13541964
申请日：2012-07-05
申请人： Kerry Veenstra , Krishna Rangasayee , Robert Bielby
发明人： Kerry Veenstra , Krishna Rangasayee , Robert Bielby
IPC分类号： H03L7/06 , H03L7/187
CPC分类号： H03L7/187 , H03K19/17736 , H03K19/17744 , H03K19/17784 , H04L25/0272 , H04L25/0282
摘要： A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.
摘要翻译：信号路由装置包括用于存储一组数据信号的寄存器组。延迟锁定环产生一组相移位时钟信号。相位控制的读取电路响应于相移位的时钟信号顺序地将来自寄存器组的数据信号组传送。连接到相位控制读取电路的低压差分信号缓冲器以低电压差分信号传输数据信号。相移位的时钟信号代替更高的时钟频率，以便降低功耗。

2. 发明授权

US06956920B1 Apparatus and method for low power routing of signals in a Low Voltage Differential Signaling system 失效
标题翻译：低电压差分信号系统中信号低功率布线的装置和方法
公开(公告)号：US06956920B1
公开(公告)日：2005-10-18
申请号：US09531862
申请日：2000-03-21
申请人： Kerry Veenstra , Krishna Rangasayee , Robert Bielby
发明人： Kerry Veenstra , Krishna Rangasayee , Robert Bielby
IPC分类号： H03K19/173 , H03K19/177 , H03L7/06 , H04L25/02 , H04L25/40
CPC分类号： H03L7/187 , H03K19/17736 , H03K19/17744 , H03K19/17784 , H04L25/0272 , H04L25/0282
摘要： A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.
摘要翻译：信号路由装置包括用于存储一组数据信号的寄存器组。延迟锁定环产生一组相移位时钟信号。相位控制的读取电路响应于相移位的时钟信号顺序地将来自寄存器组的数据信号组传送。连接到相位控制读取电路的低压差分信号缓冲器以低电压差分信号传输数据信号。相移位的时钟信号代替更高的时钟频率，以便降低功耗。

3. 发明授权

US07593499B1 Apparatus and method for low power routing of signals in a low voltage differential signaling system 失效
标题翻译：低电压差分信号系统信号低功率路由的装置和方法
公开(公告)号：US07593499B1
公开(公告)日：2009-09-22
申请号：US11198097
申请日：2005-08-04
申请人： Kerry Veenstra , Krishna Rangasayee , Robert Bielby
发明人： Kerry Veenstra , Krishna Rangasayee , Robert Bielby
IPC分类号： H04L24/40 , H04L23/00 , H03D3/24
CPC分类号： H03L7/187 , H03K19/17736 , H03K19/17744 , H03K19/17784 , H04L25/0272 , H04L25/0282
摘要： A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.
摘要翻译：信号路由装置包括用于存储一组数据信号的寄存器组。延迟锁定环产生一组相移位时钟信号。相位控制的读取电路响应于相移位的时钟信号顺序地将来自寄存器组的数据信号组传送。连接到相位控制读取电路的低压差分信号缓冲器以低电压差分信号传输数据信号。相移位的时钟信号代替更高的时钟频率，以便降低功耗。

4. 发明授权

US08233577B1 Apparatus and method for routing of signals 有权
标题翻译：用于信号路由的装置和方法
公开(公告)号：US08233577B1
公开(公告)日：2012-07-31
申请号：US12555237
申请日：2009-09-08
申请人： Kerry Veenstra , Krishna Rangasayee , Robert Bielby
发明人： Kerry Veenstra , Krishna Rangasayee , Robert Bielby
IPC分类号： H04L25/40 , H04L23/00 , H03D3/24
CPC分类号： H03L7/187 , H03K19/17736 , H03K19/17744 , H03K19/17784 , H04L25/0272 , H04L25/0282
摘要： A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.
摘要翻译：信号路由装置包括用于存储一组数据信号的寄存器组。延迟锁定环产生一组相移位时钟信号。相位控制的读取电路响应于相移位的时钟信号顺序地将来自寄存器组的数据信号组传送。连接到相位控制读取电路的低压差分信号缓冲器以低电压差分信号传输数据信号。相移位的时钟信号代替更高的时钟频率，以便降低功耗。

5. 发明授权

US6163166A Programmable logic device with selectable schmitt-triggered and threshold-triggered buffers 有权
标题翻译：可编程逻辑器件，具有可选的施密特触发和阈值触发缓冲器
公开(公告)号：US6163166A
公开(公告)日：2000-12-19
申请号：US321257
申请日：1999-05-26
申请人： Robert Bielby , Krishna Rangasayee , Brad Ishihara
发明人： Robert Bielby , Krishna Rangasayee , Brad Ishihara
IPC分类号： H03K19/177 , G06F7/38
CPC分类号： H03K19/17764 , H03K19/17744 , H03K19/1778
摘要： A programmable logic device has buffers that may be selectively programmed for Schmitt-triggered and threshold-triggered operation. The programmable Schmitt-triggered buffers are connected to circuit nodes that are sensitive to noisy environments. The programmable threshold-triggered buffers are connected to circuit nodes that have critical timing requirements.
摘要翻译：可编程逻辑器件具有可以选择性地编程用于施密特触发和阈值触发操作的缓冲器。可编程施密特触发缓冲器连接到对噪声环境敏感的电路节点。可编程门限触发缓冲器连接到具有关键时序要求的电路节点。

6. 发明授权

US06232893B1 Method and apparatus for programmably providing a power supply voltage to an integrated circuit 有权
标题翻译：用于可编程地向集成电路提供电源电压的方法和装置
公开(公告)号：US06232893B1
公开(公告)日：2001-05-15
申请号：US09311208
申请日：1999-05-12
申请人： Richard Cliff , Robert Bielby
发明人： Richard Cliff , Robert Bielby
IPC分类号： H03M700
CPC分类号： H03K19/1776 , G05F1/465 , G11C5/147 , H03K19/1778 , H03K19/17784
摘要： The invention relates to programmable voltage regulator that programmably provides a desired operating voltage to a power pin based upon operating voltage configuration data. The programmable voltage regulator includes an operating voltage configuration data decoder arranged to decode the operating voltage configuration data. The programmable voltage regulator also includes a programmable voltage down converter connected to the operating voltage configuration data decoder. The programmable voltage down converter uses the decoded operating voltage configuration data to convert the first voltage to the desired operating voltage which is then output to the power pin.
摘要翻译：本发明涉及可编程电压调节器，其可编程地基于工作电压配置数据向电源引脚提供期望的工作电压。可编程电压调节器包括布置成解码工作电压配置数据的工作电压配置数据解码器。可编程稳压器还包括连接到工作电压配置数据解码器的可编程降压转换器。可编程降压转换器使用解码的工作电压配置数据将第一电压转换成期望的工作电压，然后将其输出到电源引脚。

7. 发明授权

US06366224B2 Programmable voltage regulator 有权
标题翻译：可编程稳压器
公开(公告)号：US06366224B2
公开(公告)日：2002-04-02
申请号：US09814435
申请日：2001-03-21
申请人： Richard Cliff , Robert Bielby
发明人： Richard Cliff , Robert Bielby
IPC分类号： H03M700
CPC分类号： H03K19/1776 , G05F1/465 , G11C5/147 , H03K19/1778 , H03K19/17784
摘要： The invention relates to programmable voltage regulator that programmably provides a desired operating voltage to a power pin based upon operating voltage configuration data. The programmable voltage regulator includes an operating voltage configuration data decoder arranged to decode the operating voltage configuration data. The programmable voltage regulator also includes a programmable voltage down converter connected to the operating voltage configuration data decoder. The programmable voltage down converter uses the decoded operating voltage configuration data to convert the first voltage to the desired operating voltage which is then output to the power pin.
摘要翻译：本发明涉及可编程电压调节器，其可编程地基于工作电压配置数据向电源引脚提供期望的工作电压。可编程电压调节器包括布置成解码工作电压配置数据的工作电压配置数据解码器。可编程稳压器还包括连接到工作电压配置数据解码器的可编程降压转换器。可编程降压转换器使用解码的工作电压配置数据将第一电压转换成期望的工作电压，然后将其输出到电源引脚。

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