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1. 发明授权

US07893712B1 Integrated circuit with a selectable interconnect circuit for low power or high performance operation 有权
标题翻译：具有可选择的互连电路的集成电路，用于低功耗或高性能运行
公开(公告)号：US07893712B1
公开(公告)日：2011-02-22
申请号：US12556959
申请日：2009-09-10
申请人： Chin Hua Tan , Shankar Lakka , Ronald L. Cline , James B. Anderson , Wayne E. Wennekamp
发明人： Chin Hua Tan , Shankar Lakka , Ronald L. Cline , James B. Anderson , Wayne E. Wennekamp
IPC分类号： H03K19/173
CPC分类号： H03K19/17784 , H03K19/17792
摘要： An integrated circuit, such as a field programmable gate array or other configurable logic device, has an interconnect circuit selectively configurable to operate in a high-speed mode or in a low-power mode. The interconnect circuit is operable from a higher voltage supply or a lower voltage supply to change operating modes without reconfiguring data paths.
摘要翻译：诸如现场可编程门阵列或其他可配置逻辑器件的集成电路具有可选择地配置为以高速模式或低功率模式操作的互连电路。互连电路可以从较高电压电源或较低电压电源工作，以改变操作模式，而不重新配置数据路径。

2. 发明授权

US08438357B1 Method and apparatus for calculating number of memory access cycles when transferring data to or from a memory 有权
标题翻译：用于在将数据传送到存储器或从存储器传送数据时计算存储器访问周期数的方法和装置
公开(公告)号：US08438357B1
公开(公告)日：2013-05-07
申请号：US12690856
申请日：2010-01-20
申请人： Adam Elkins , Wayne E. Wennekamp , Roger D. Flateau, Jr.
发明人： Adam Elkins , Wayne E. Wennekamp , Roger D. Flateau, Jr.
IPC分类号： G06F13/00
CPC分类号： H03K19/1776 , H03K19/17736 , H03K19/1774
摘要： A technique applicable during the transfer of data to and from a memory involves: operating a memory interface using memory access cycles that each transfer a quantity of data D across the memory interface; receiving a request to transfer a quantity of data Q across the memory interface; and calculating a value M as a function of a plurality of parameters, M being a minimum number of the memory access cycles needed to carry out the transfer of the quantity of data Q across the memory interface, wherein the calculating includes determining a logarithm of one of the parameters, and then determining the value M as a function of the logarithm.
摘要翻译：在将数据传送到存储器和从存储器传送数据时适用的技术包括：使用存储器访问周期来操作存储器接口，每个存储器存储周期在存储器接口上传送数据量D; 接收在所述存储器接口上传送数据量Q的请求; 以及计算作为多个参数的函数的值M，M是在所述存储器接口上执行所述数据量Q的传送所需的存储器访问周期的最小数量，其中所述计算包括确定一个对数的对数的参数，然后确定值M作为对数的函数。

3. 发明授权

US08222923B1 Method and apparatus for memory control with a programmable device 有权
标题翻译：用可编程器件进行存储器控制的方法和装置
公开(公告)号：US08222923B1
公开(公告)日：2012-07-17
申请号：US12694615
申请日：2010-01-27
申请人： Schuyler E. Shimanek , Wayne E. Wennekamp , Joe E. Leyba , Adam Elkins , Thomas H. Strader , Chidamber R. Kulkarni , Mikhail A. Wolf , Steven E. McNeil
发明人： Schuyler E. Shimanek , Wayne E. Wennekamp , Joe E. Leyba , Adam Elkins , Thomas H. Strader , Chidamber R. Kulkarni , Mikhail A. Wolf , Steven E. McNeil
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/17736 , H03K19/1774
摘要： A technique is provided for memory control in a device having programmable circuitry, including providing a dedicated memory controller circuit in the device before the programmable circuitry is field programmed. Another technique involves fabricating a device, where the fabricating involves forming programmable circuitry that includes a dedicated memory controller circuit before the circuitry is field programmed.
摘要翻译：提供了一种用于具有可编程电路的器件中的存储器控制的技术，包括在可编程电路被现场编程之前在器件中提供专用存储器控制器电路。另一技术涉及制造一种器件，其中制造涉及在电路被现场编程之前形成包括专用存储器控制器电路的可编程电路。

4. 发明授权

US07425843B1 Programmable logic device multi-boot state machine for serial peripheral interface (SPI) programmable read only memory (PROM) 有权
标题翻译：可编程逻辑器件多引导状态机，用于串行外设接口（SPI）可编程只读存储器（PROM）
公开(公告)号：US07425843B1
公开(公告)日：2008-09-16
申请号：US11890822
申请日：2007-08-07
申请人： Eric E. Edwards , Wayne E. Wennekamp
发明人： Eric E. Edwards , Wayne E. Wennekamp
IPC分类号： H03K19/173
CPC分类号： G06F15/7867 , H03K19/17756 , H03K19/17776
摘要： Multiple configurations are provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA), when connected to a serial peripheral interface programmable read only memory (SPI PROM) by using a programmable SPI address register incorporated into a SPI state machine of the PLD. A read command followed by a first address corresponding to first configuration data is sent from the SPI address register of the SPI state machine of the PLD to the SPI PROM. Data starting at the first address in the SPI PROM is then read by the PLD from the SPI PROM along with a second address corresponding to second configuration data. The first configuration data is stored in the PLD memory, and the second address is stored in the SPI address register. These steps may be repeated for subsequent boots of the PLD for additional configurations of the PLD.
摘要翻译：当可编程逻辑器件（PLD），例如现场可编程门阵列（FPGA）通过使用可编程SPI地址寄存器连接到SPI中而连接到串行外设接口可编程只读存储器（SPI PROM）时，提供多种配置 PLD的状态机。对应于第一配置数据的第一个地址的读命令从PLD的SPI状态机的SPI地址寄存器发送到SPI PROM。从SPI PROM开始的第一个地址开始的数据由PLD从SPI PROM读取，以及与第二个配置数据对应的第二个地址。第一个配置数据存储在PLD存储器中，第二个地址存储在SPI地址寄存器中。对于PLD的后续引导，可以重复这些步骤以用于PLD的附加配置。

5. 发明授权

US08587337B1 Method and apparatus for capturing and synchronizing data 有权
标题翻译：用于捕获和同步数据的方法和装置
公开(公告)号：US08587337B1
公开(公告)日：2013-11-19
申请号：US12689558
申请日：2010-01-19
申请人： Schuyler E. Shimanek , Adam Elkins , Wayne E. Wennekamp
发明人： Schuyler E. Shimanek , Adam Elkins , Wayne E. Wennekamp
IPC分类号： H03K19/173 , H04B1/00 , H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H03K19/1776 , H03K19/17736 , H03K19/1774
摘要： An embodiment of a technique to capture and locally synchronize data is disclosed. The technique includes receiving first and second signals through a first interface, and receiving a third signal through a second interface where the third signal is unsynchronized with respect to the second signal. The technique further includes detecting a first phase difference between the second and third signals, and generating a fourth signal in a manner so that a second phase difference between the fourth signal and one of the second or third signals is a function of the first phase difference. In addition, the technique includes storing a state of the first signal in response to the fourth signal, and thereafter supplying the stored state of the first signal to the second interface.
摘要翻译：公开了捕获和本地同步数据的技术的实施例。该技术包括通过第一接口接收第一和第二信号，以及通过第二接口接收第三信号，其中第三信号相对于第二信号不同步。该技术还包括检测第二和第三信号之间的第一相位差，并且以这样的方式生成第四信号，使得第四信号和第二或第三信号中的一个之间的第二相位差是第一相位差的函数。此外，该技术包括响应于第四信号存储第一信号的状态，然后将第一信号的存储状态提供给第二接口。

6. 发明授权

US07831415B1 Circuit for testing input signals and a method of testing input signals coupled to a circuit 有权
标题翻译：用于测试输入信号的电路和测试耦合到电路的输入信号的方法
公开(公告)号：US07831415B1
公开(公告)日：2010-11-09
申请号：US12035388
申请日：2008-02-21
申请人： Joe Eddie Leyba, II , Wayne E. Wennekamp , Schuyler E. Shimanek
发明人： Joe Eddie Leyba, II , Wayne E. Wennekamp , Schuyler E. Shimanek
IPC分类号： G06F15/00
CPC分类号： G01R31/31715
摘要： A method of testing input signals coupled to a circuit for performing a predetermined function is disclosed. The method comprises coupling input signals to inputs of the circuit by way of programmable interconnects; controlling the paths of the input signals within the circuit from the inputs to an output of the circuit; maintaining the states of the input signals coupled to the inputs of the circuit and routed to the output of the circuit; and testing output signals of the circuit to determine whether the correct input signals were provided to the inputs of the circuit by way of the programmable interconnects. A device having programmable logic which enables testing of input signals is also disclosed.
摘要翻译：公开了一种测试耦合到用于执行预定功能的电路的输入信号的方法。该方法包括通过可编程互连将输入信号耦合到电路的输入; 控制从电路的输入到电路的输出的电路内的输入信号的路径; 保持耦合到电路的输入端的输入信号的状态并被路由到电路的输出; 并测试电路的输出信号，以确定是否通过可编程互连将正确的输入信号提供给电路的输入。还公开了一种具有能够测试输入信号的可编程逻辑的装置。

7. 发明授权

US07225373B1 Data transfer validation system 有权
标题翻译：数据传输验证系统
公开(公告)号：US07225373B1
公开(公告)日：2007-05-29
申请号：US10741689
申请日：2003-12-18
申请人： Eric E. Edwards , Schuyler E. Shimanek , Phillip A. Young , Steven T. Reilly , Wayne E. Wennekamp
发明人： Eric E. Edwards , Schuyler E. Shimanek , Phillip A. Young , Steven T. Reilly , Wayne E. Wennekamp
IPC分类号： G01R31/28
CPC分类号： H04L1/0083 , H04L1/0061
摘要： System and apparatus for data validation is described. An initialization controller includes an initialization state machine. The initialization state machine is configured to cause configuration data to be transferred from memory internal or external to the integrated circuit to other memory internal to the integrated circuit. The configuration data is stored in the integrated circuit, read back from storage in the integrated circuit, and compressed by the integrated circuit after being read back. The configuration data is compressed into a signature, which may be compared with an expected result for the signature.
摘要翻译：描述用于数据验证的系统和装置。初始化控制器包括初始化状态机。初始化状态机被配置为使配置数据从集成电路的内部或外部的存储器传输到集成电路内部的其他存储器。配置数据存储在集成电路中，从集成电路中的存储器读回，并在读回后由集成电路压缩。配置数据被压缩成签名，其可以与签名的预期结果进行比较。

8. 发明授权

US08307182B1 Method and apparatus for transferring data to or from a memory 有权
标题翻译：用于将数据传送到存储器或从存储器传送数据的方法和装置
公开(公告)号：US08307182B1
公开(公告)日：2012-11-06
申请号：US12689604
申请日：2010-01-19
申请人： Roger D. Flateau, Jr. , Thomas H. Strader , Adam Elkins , Wayne E. Wennekamp , Schuyler E. Shimanek
发明人： Roger D. Flateau, Jr. , Thomas H. Strader , Adam Elkins , Wayne E. Wennekamp , Schuyler E. Shimanek
IPC分类号： G06F13/00
CPC分类号： H03K19/1776 , H03K19/17736 , H03K19/1774
摘要： An embodiment of a technique to transfer data includes: operating a memory interface using memory access cycles that each include T successive time slots each provided for transfer of B bits of data, where T and B are positive integers; selecting one of first or second predetermined integers as one of T or B; and transferring a quantity of data Q between the memory interface and another interface. The transferring includes: automatically determining a value of M memory access cycles as a function of the one of T or B; causing a data transfer sequence on the memory interface that includes M successive memory access cycles and thus M·T time slots; automatically determining a subset of the M·T time slots as a function of the one of T or B; and transferring the quantity of data Q through the memory interface during the subset of time slots.
摘要翻译：传输数据的技术的实施例包括：使用存储器访问周期操作存储器接口，每个存储器存储周期包括每个提供用于传输B位数据的T个连续时隙，其中T和B是正整数; 选择第一或第二预定整数之一作为T或B之一; 以及在存储器接口和另一个接口之间传送数据量Q。转移包括：根据T或B之一自动确定M个存储器访问周期的值; 在存储器接口上产生包括M个连续存储器访问周期以及因此M·T个时隙的数据传输序列; 根据T或B之一自动确定M·T时隙的子集; 并且在时隙的子集期间通过存储器接口传送数据量Q。

9. 发明授权

US08200874B1 Method and apparatus for arbitration among multiple ports 有权
标题翻译：多个端口仲裁的方法和装置
公开(公告)号：US08200874B1
公开(公告)日：2012-06-12
申请号：US12694665
申请日：2010-01-27
申请人： Wayne E. Wennekamp , Adam Elkins , Schuyler E. Shimanek , Thomas H. Strader , Steven E. McNeil
发明人： Wayne E. Wennekamp , Adam Elkins , Schuyler E. Shimanek , Thomas H. Strader , Steven E. McNeil
IPC分类号： G06F12/00
CPC分类号： H03K19/1776 , H03K19/17736 , H03K19/1774
摘要： A device has first circuitry and also second circuitry that includes an interface and command ports that can each receive commands from the first circuitry, each command requesting an information transfer through the interface. A technique relating to the device involves dynamically enabling and disabling at least one of the command ports under control of the first circuitry, and using a priority list specifying an order of priority for a group of the command ports to identify and cause a command to be accepted from the command port of highest priority that contains a command and is currently enabled.
摘要翻译：设备具有第一电路，并且还包括第二电路，其包括可以从第一电路接收命令的接口和命令端口，每个命令请求通过接口进行信息传输。与设备相关的技术涉及在第一电路的控制下动态地启用和禁用至少一个命令端口，并且使用指定一组命令端口的优先级顺序的优先级列表来识别并使命令成为从包含命令的最高优先级的命令端口接受并且当前已启用。

10. 发明授权

US08063660B1 Method and apparatus for configurable address translation 有权
标题翻译：用于可配置地址转换的方法和装置
公开(公告)号：US08063660B1
公开(公告)日：2011-11-22
申请号：US12695341
申请日：2010-01-28
申请人： Thomas H. Strader , Roger D. Flateau, Jr. , Schuyler E. Shimanek , Wayne E. Wennekamp , Adam Elkins
发明人： Thomas H. Strader , Roger D. Flateau, Jr. , Schuyler E. Shimanek , Wayne E. Wennekamp , Adam Elkins
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/17736 , H03K19/1774
摘要： A technique is applicable to a device having programmable circuitry that includes a first interface having a plurality of first address terminals, a second interface having a plurality of second address terminals, and a configurable interconnect structure coupled between the first and second interfaces. The technique includes configuring the interconnect structure during field programming to electrically couple each of the address terminals in a first subset of the first address terminals to respective address terminals in a second subset of the second address terminals according to a selected one of a plurality of different mapping functions.
摘要翻译：一种技术适用于具有可编程电路的设备，该可编程电路包括具有多个第一地址终端的第一接口，具有多个第二地址终端的第二接口以及耦合在第一和第二接口之间的可配置互连结构。该技术包括在现场编程期间配置互连结构，以将第一地址终端的第一子集中的每个地址终端电耦合到第二地址终端的第二子集中的相应地址终端，根据多个不同的选择的一个映射功能。

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