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71. 发明授权

US07197607B2 Non-volatile memory with concurrent write and read operation to differing banks 有权
标题翻译：非易失性存储器，并行写入和读取操作到不同的存储区
公开(公告)号：US07197607B2
公开(公告)日：2007-03-27
申请号：US11135803
申请日：2005-05-24
申请人： Frankie F. Roohparvar
发明人： Frankie F. Roohparvar
IPC分类号： G06F12/06
CPC分类号： G11C7/1015 , G06F12/0246 , G06F2212/7206 , G11C7/1072 , G11C16/10 , G11C16/26 , G11C2207/2281 , G11C2207/229 , G11C2216/22
摘要： A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. A write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections. The memory can write data to one location, such as a memory array block, while data is read from a second location, such as a second memory array block. The write and read operations are performed on a common addressable row of the array blocks.
摘要翻译：同步闪速存储器包括非易失性存储器单元阵列。存储器阵列以行和列布置，并且可以进一步布置在可寻址块中。数据通信连接用于与外部设备（例如处理器或其他存储器控制器）的双向数据通信。写锁存器耦合在数据缓冲器和存储器阵列之间以锁存数据通信连接上提供的数据。存储器可以将数据写入到诸如存储器阵列块的一个位置，同时从诸如第二存储器阵列块的第二位置读取数据。写和读操作在数组块的公共可寻址行上执行。

72. 发明授权

US07164610B2 Microcomputer having a flush memory that can be temporarily interrupted during an erase process 失效
标题翻译：具有可在擦除过程中暂时中断的闪存的微型计算机
公开(公告)号：US07164610B2
公开(公告)日：2007-01-16
申请号：US10323771
申请日：2002-12-20
申请人： Hiroyuki Kimura , Kunio Tani , Tetsu Tashiro , Makoto Yamamoto , Toshihiro Sezaki
发明人： Hiroyuki Kimura , Kunio Tani , Tetsu Tashiro , Makoto Yamamoto , Toshihiro Sezaki
IPC分类号： G06F9/312
CPC分类号： G11C16/16 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/344 , G11C2216/22
摘要： A microcomputer with a built-in non-volatile semiconductor memory, which can automatically perform a work of temporarily interrupting automatic writing or automatic erase and accepting an interruption process when an interruption occurs during the automatic writing or automatic erase by using an interrupt request signal for a microcomputer as an external input for controlling automatic writing or automatic erase of a flash memory.
摘要翻译：具有内置非易失性半导体存储器的微型计算机，其可以在自动写入或自动擦除期间通过使用中断请求信号自动执行临时中断自动写入或自动擦除和接受中断处理的工作作为用于控制闪存的自动写入或自动擦除的外部输入的微计算机。

73. 发明授权

US07149120B2 Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations 有权
公开(公告)号：US07149120B2
公开(公告)日：2006-12-12
申请号：US11011304
申请日：2004-12-14
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/14 , G11C16/16 , G11C16/3445 , G11C2216/18 , G11C2216/22 , H01L27/11521 , H01L27/11524
摘要： A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.

74. 发明授权

US07093064B2 Programming suspend status indicator for flash memory 有权
标题翻译：为闪存设置暂停状态指示灯
公开(公告)号：US07093064B2
公开(公告)日：2006-08-15
申请号：US10927338
申请日：2004-08-25
申请人： Vishram P. Dalvi , Rodney R. Rozman
发明人： Vishram P. Dalvi , Rodney R. Rozman
IPC分类号： G06F12/02 , G06F12/14 , G11C7/00
CPC分类号： G06F12/1433 , G06F12/023 , G11C16/10 , G11C16/26 , G11C2216/20 , G11C2216/22
摘要： A status register for a memory device. The status register provides a programming suspend status signal and a protection status signal. The programming suspend status signal indicates whether a programming operation is suspended. If the processor knows that a programming operation to a specific memory location is suspended, then the processor may request that a data modification operation to another memory location be performed while the programming operation is suspended. The protection status signal indicates whether an attempted data modification operation failed due to a protected memory block versus another type of device failure. Protecting or locking a memory block prevents the modification of data stored in a particular memory block.
摘要翻译：存储器设备的状态寄存器。状态寄存器提供编程挂起状态信号和保护状态信号。编程暂停状态信号指示是否暂停编程操作。如果处理器知道对特定存储器位置的编程操作被暂停，则处理器可以请求在编程操作被暂停时执行对另一个存储器位置的数据修改操作。保护状态信号指示尝试的数据修改操作是否由于受保护的存储器块与其他类型的设备故障而失败。保护或锁定存储器块可防止存储在特定存储器块中的数据的修改。

75. 发明授权

US07092289B1 Efficient redundancy system for flash memories with uniformly sized blocks 有权
标题翻译：具有均匀尺寸块的闪存的高效冗余系统
公开(公告)号：US07092289B1
公开(公告)日：2006-08-15
申请号：US10611465
申请日：2003-06-30
申请人： Sau Ching Wong
发明人： Sau Ching Wong
IPC分类号： G11C16/08 , G11C16/06 , G11C29/00 , G11C8/10
CPC分类号： G11C29/82 , G11C5/025 , G11C11/56 , G11C15/00 , G11C15/04 , G11C29/844 , G11C2216/22
摘要： A Flash memory that stores data, code, and parameters and performs parallel operations employs uniform-size blocks in array planes. A redundancy system for the Flash memory uses a CAM and a RAM for address comparison and substitution when replacing addresses corresponding to defective memory elements. The uniform block size allows block replacement where spare blocks in the array planes replace defective blocks. To reduce access delays from signal propagation through the CAM and RAM, part of the input address such as the row address goes directly to decoders while another part of the input address such as the block address goes to the CAM array for comparison.
摘要翻译：存储数据，代码和参数并执行并行操作的闪存在阵列平面中使用均匀大小的块。当替换与缺陷存储器元件相对应的地址时，闪存的冗余系统使用CAM和RAM进行地址比较和替换。统一块大小允许块替换，其中阵列平面中的备用块替换有缺陷的块。为了减少通过CAM和RAM的信号传播的访问延迟，诸如行地址的输入地址的一部分直接进入解码器，而另一部分输入地址（如块地址）则转到CAM阵列进行比较。

76. 发明申请

US20060158947A1 Reference sense amplifier for non-volatile memory 有权
标题翻译：用于非易失性存储器的参考读出放大器
公开(公告)号：US20060158947A1
公开(公告)日：2006-07-20
申请号：US11321953
申请日：2005-12-28
申请人： Siu Chan , Raul-Adrian Cernea
发明人： Siu Chan , Raul-Adrian Cernea
IPC分类号： G11C7/02
CPC分类号： G11C7/062 , G11C7/04 , G11C7/067 , G11C7/08 , G11C7/227 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/26 , G11C16/28 , G11C2211/5621 , G11C2216/14 , G11C2216/22
摘要： One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.
摘要翻译：用于感测非易失性存储器的传导电流的一个或多个感测放大器由具有相似特性和操作条件的参考读出放大器定时的信号控制。在一个方面，感测周期由感测参考电流的参考读出放大器何时检测到预期状态来确定。在另一方面，放大输出的积分周期由参考读出放大器何时输出预期状态来确定。当这些确定的定时用于控制一个或多个感测放大器时，跟踪环境和系统变化。

77. 发明授权

US07079417B2 Read-while-write flash memory devices having local row decoder circuits activated by separate read and write signals 有权
标题翻译：具有由单独的读取和写入信号激活的本地行解码器电路的读写闪存器件
公开(公告)号：US07079417B2
公开(公告)日：2006-07-18
申请号：US10622278
申请日：2003-07-18
申请人： Ga-pyo Nam , Seung-Keun Lee
发明人： Ga-pyo Nam , Seung-Keun Lee
IPC分类号： G11C16/04
CPC分类号： G11C8/10 , G11C8/12 , G11C16/08 , G11C2216/22
摘要： A flash memory device can include a local row decoder circuit that is configured to drive word lines coupled to a bank of a flash memory responsive to separate read and write control signals provided thereto from outside the local row decoder circuit. Multiple local row decoder circuits can, therefore, be controlled by a single global row decoder circuit that provides the separate read and write control signals to each of the local row decoder circuits. By locating the combinatorial logic circuits used for decoding addresses in the global row decoder circuit, rather than in the local row decoder circuits, the local row decoder circuits may have reduced size, thereby allowing further reductions in the size of the flash memory device. For example, in some embodiments according to the invention, a NAND logic circuit used for address decoding is located in the global row decoder circuit, thereby allowing the area allocated to the local row decoder circuit to be reduced. Furthermore, because the may be many local row decoder circuits implemented in the flash memory device, the total size of the flash memory may be reduced.
摘要翻译：闪速存储器件可以包括本地行解码器电路，其被配置为响应于从本地行解码器电路外部提供的分离的读取和写入控制信号来驱动耦合到闪速存储体的字线。因此，多个本地行解码器电路可以由单个全局行解码器电路控制，该电路为每个本地行解码器电路提供单独的读取和写入控制信号。通过将用于解码地址的组合逻辑电路定位在全局行解码器电路中，而不是在本地行解码器电路中，本地行解码器电路可以具有减小的尺寸，从而允许进一步减小闪存器件的尺寸。例如，在根据本发明的一些实施例中，用于地址解码的NAND逻辑电路位于全局行解码器电路中，从而允许减小分配给本地行解码器电路的区域。此外，由于可能是在闪速存储器件中实现的许多本地行解码器电路，所以可以减少闪存的总大小。

78. 发明申请

US20060067148A1 Semiconductor device and data write method 有权
标题翻译：半导体器件和数据写入方式
公开(公告)号：US20060067148A1
公开(公告)日：2006-03-30
申请号：US11228777
申请日：2005-09-16
申请人： Kazuhide Kurosaki
发明人： Kazuhide Kurosaki
IPC分类号： G11C7/02
CPC分类号： G11C7/1006 , G11C7/1048 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device is provided that can perform simultaneous writing of a large number of bits, without an increase in chip size. This semiconductor device includes: a write data bus via which data are written into memory cells; a read data bus via which the data are read from the memory cells; a first write amplifier that writes data into the memory cells via the read data bus at the time of high-speed writing; a second write amplifier that writes data into the memory cells via the write data bus at the time of high-speed writing; a first sense amplifier that reads verified data from the memory cells via the read data bus; and a second sense amplifier that reads verified data from the memory cells via the write data bus.
摘要翻译：提供一种可以执行大量位的同时写入而不增加芯片尺寸的半导体器件。该半导体器件包括：数据写入存储器单元的写入数据总线; 读取数据总线，通过该数据总线从存储器单元读取数据; 第一写放大器，其在高速写入时通过读数据总线将数据写入存储单元; 第二写放大器，其在高速写入时通过写数据总线将数据写入存储单元; 第一读出放大器，经由读取数据总线从存储器单元读取经过验证的数据; 以及第二读出放大器，其经由写数据总线从存储器单元读取经验证的数据。

79. 发明申请

US20050262291A1 Method to write in a non-volatile memory and system to implement such method 审中-公开
标题翻译：在非易失性存储器和系统中写入实现这种方法的方法
公开(公告)号：US20050262291A1
公开(公告)日：2005-11-24
申请号：US10519394
申请日：2003-06-27
申请人： Christoph Siegelin , Laurent Csatillo
发明人： Christoph Siegelin , Laurent Csatillo
IPC分类号： G06F12/00 , G06F12/02 , G06F12/06 , G11C16/10
CPC分类号： G11C16/102 , G11C2216/22
摘要： This invention concerns a method to write in a Flash type memory of an electronic module. The method consists in: associating at least two physical areas of said memory, called mirror areas, with the same logical area and during a write in said logical area, in programming the content of said logical area in one of said blank mirror areas; erasing the content of all mirror area used in a single operation at a convenient time. This invention also concerns the smart card in which the method is implemented.
摘要翻译：本发明涉及一种写入电子模块的闪存型存储器的方法。该方法包括：将所述存储器的称为镜像区域的至少两个物理区域与相同的逻辑区域以及在所述逻辑区域的写入期间，在所述空白镜像区域之一中对所述逻辑区域的内容进行编程; 在方便的时间擦除单个操作中使用的所有镜像区域的内容。本发明还涉及实现该方法的智能卡。

80. 发明授权

US06957297B1 Simultaneous execution command modes in a flash memory device 有权
标题翻译：闪存设备中的同时执行命令模式
公开(公告)号：US06957297B1
公开(公告)日：2005-10-18
申请号：US10603136
申请日：2003-06-23
申请人： Lee E. Cleveland , Kendra Nguyen
发明人： Lee E. Cleveland , Kendra Nguyen
IPC分类号： G11C16/10 , G11C16/26 , G06F12/02
CPC分类号： G11C16/26 , G11C16/10 , G11C2216/22
摘要： A method for operating a flash memory includes, in response to a received operation command, initiating an embedded operation of the flash memory and subsequently, during execution of the embedded operation, in response to a received read command, initiating a burst read operation of the flash memory.
摘要翻译：一种用于操作闪速存储器的方法包括：响应于所接收的操作命令，启动闪速存储器的嵌入式操作，随后在执行嵌入式操作期间，响应于接收到的读取命令，启动闪存读取操作闪存

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