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1. 发明授权

US07079417B2 Read-while-write flash memory devices having local row decoder circuits activated by separate read and write signals 有权
标题翻译：具有由单独的读取和写入信号激活的本地行解码器电路的读写闪存器件
公开(公告)号：US07079417B2
公开(公告)日：2006-07-18
申请号：US10622278
申请日：2003-07-18
申请人： Ga-pyo Nam , Seung-Keun Lee
发明人： Ga-pyo Nam , Seung-Keun Lee
IPC分类号： G11C16/04
CPC分类号： G11C8/10 , G11C8/12 , G11C16/08 , G11C2216/22
摘要： A flash memory device can include a local row decoder circuit that is configured to drive word lines coupled to a bank of a flash memory responsive to separate read and write control signals provided thereto from outside the local row decoder circuit. Multiple local row decoder circuits can, therefore, be controlled by a single global row decoder circuit that provides the separate read and write control signals to each of the local row decoder circuits. By locating the combinatorial logic circuits used for decoding addresses in the global row decoder circuit, rather than in the local row decoder circuits, the local row decoder circuits may have reduced size, thereby allowing further reductions in the size of the flash memory device. For example, in some embodiments according to the invention, a NAND logic circuit used for address decoding is located in the global row decoder circuit, thereby allowing the area allocated to the local row decoder circuit to be reduced. Furthermore, because the may be many local row decoder circuits implemented in the flash memory device, the total size of the flash memory may be reduced.
摘要翻译：闪速存储器件可以包括本地行解码器电路，其被配置为响应于从本地行解码器电路外部提供的分离的读取和写入控制信号来驱动耦合到闪速存储体的字线。因此，多个本地行解码器电路可以由单个全局行解码器电路控制，该电路为每个本地行解码器电路提供单独的读取和写入控制信号。通过将用于解码地址的组合逻辑电路定位在全局行解码器电路中，而不是在本地行解码器电路中，本地行解码器电路可以具有减小的尺寸，从而允许进一步减小闪存器件的尺寸。例如，在根据本发明的一些实施例中，用于地址解码的NAND逻辑电路位于全局行解码器电路中，从而允许减小分配给本地行解码器电路的区域。此外，由于可能是在闪速存储器件中实现的许多本地行解码器电路，所以可以减少闪存的总大小。

2. 发明授权

US07142457B2 Non-volatile semiconductor memory device 失效
公开(公告)号：US07142457B2
公开(公告)日：2006-11-28
申请号：US11327045
申请日：2006-01-06
申请人： Seung-Won Lee , Seung-Keun Lee
发明人： Seung-Won Lee , Seung-Keun Lee
IPC分类号： G11C16/26
CPC分类号： G11C7/062 , G11C7/18 , G11C16/04 , G11C16/28 , G11C29/24 , G11C29/50004
摘要： A memory device in accordance with embodiments of the present invention includes a reference cell array and a plurality of banks. Each of the banks includes memory cells. A plurality of current copier circuits corresponds to the banks, respectively. Each of the current copier circuits copies a reference current flowing through a reference cell array to generate a reference voltage. A plurality of sense blocks correspond to the banks, respectively. Each of the sense blocks includes a plurality of sense amplifiers for sensing data from a corresponding bank in response to the reference voltage from the corresponding current copier circuit. Memory cell lay-out area is reduced, and sense speed is increased.

3. 发明申请

US20060092707A1 Bitline bias circuit and nor flash memory device including the bitline bias circuit 有权
标题翻译：位线偏置电路和不包括位线偏置电路的闪存器件
公开(公告)号：US20060092707A1
公开(公告)日：2006-05-04
申请号：US11265218
申请日：2005-11-02
申请人： Hong-Soo Jeon , Seung-Keun Lee
发明人： Hong-Soo Jeon , Seung-Keun Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/24 , G11C5/145
摘要： The NOR flash memory device according to the present invention is operated by a high voltage supplied from bitline selection transistors and includes a bitline bias circuit for supplying a bias voltage of a constant level to the bitline bias transistor. In accordance with the present invention, it is possible to stably supply a desired voltage closing to a power voltage to the bitline bias transistor.
摘要翻译：根据本发明的NOR闪速存储器件通过从位线选择晶体管提供的高电压来操作，并且包括用于向位线偏置晶体管提供恒定电平的偏置电压的位线偏置电路。根据本发明，可以稳定地向位线偏置晶体管提供关闭到电源电压的期望电压。

4. 发明申请

US20050111261A1 Non-volatile semiconductor memory device having sense amplifier with increased speed 有权
标题翻译：具有增加速度的读出放大器的非易失性半导体存储器件
公开(公告)号：US20050111261A1
公开(公告)日：2005-05-26
申请号：US10991042
申请日：2004-11-16
申请人： Seung-Keun Lee , Jin-Sung Park
发明人： Seung-Keun Lee , Jin-Sung Park
IPC分类号： G11C16/06 , G11C16/04 , G11C16/26 , G11C16/28
CPC分类号： G11C16/28
摘要： In the non-volatile semiconductor memory device having a sense amplifier for sensing data stored in a selected memory cell by comparing cell current differences from a reference cell, a current sink unit coupled in parallel with a reference line and a data line are provided. The reference line connects between the reference cell and the sense amplifier, and the data line connects between the selected memory cell and the sense amplifier, where the current sink unit together increases currents of the reference line and the data line. Also, the device includes a sink current control unit having a configuration of a current mirror with the current sink unit, the sink current control unit consisting of a switching unit and being for controlling a sink current of the current sink unit. The device improves data sensing speed and controls sensing current in conformity with the characteristics of a memory cell.
摘要翻译：在具有读出放大器的非易失性半导体存储器件中，提供了用于通过比较来自参考单元的单元电流差异来感测存储在所选存储单元中的数据的读出放大器，提供与参考线和数据线并联耦合的电流宿单元。参考线连接在参考单元和读出放大器之间，数据线连接在所选择的存储单元和读出放大器之间，其中电流吸收单元一起增加参考线和数据线的电流。此外，该装置包括具有电流反射镜与电流吸收单元的配置的宿电流控制单元，宿电流控制单元由开关单元组成并用于控制电流宿单元的宿电流。该器件提高了数据感测速度，并根据存储单元的特性来控制感应电流。

5. 发明授权

US06867628B2 Semiconductor memory delay circuit 失效
标题翻译：半导体存储延迟电路
公开(公告)号：US06867628B2
公开(公告)日：2005-03-15
申请号：US10405357
申请日：2003-04-03
申请人： Ji-Ho Cho , Seung-Keun Lee
发明人： Ji-Ho Cho , Seung-Keun Lee
IPC分类号： G11C8/00 , G11C8/18 , H03K5/08 , H03K5/13 , H03K5/1534 , H03H11/26
CPC分类号： G11C8/18 , H03K5/082 , H03K5/1534
摘要： A circuit includes an input for receiving an input signal, a delay chain connected to the input for delaying the input signal, and a circuit configuration connected to the delay chain downstream of the input, the circuit configuration for supplying a voltage to the delay chain in response to the input signal.
摘要翻译：电路包括用于接收输入信号的输入端，连接到输入端的用于延迟输入信号的延迟链，以及连接到输入下游延迟链路的电路配置，用于向延迟链提供电压的电路配置响应输入信号。

6. 发明申请

US20050007187A1 Charge pump circuit operating responsive to a mode 失效
标题翻译：电荷泵电路响应于模式运行
公开(公告)号：US20050007187A1
公开(公告)日：2005-01-13
申请号：US10888667
申请日：2004-07-08
申请人： Pyung-Moon Zhang , Seung-Keun Lee
发明人： Pyung-Moon Zhang , Seung-Keun Lee
IPC分类号： H03L7/00 , H02M3/07 , G05F3/02
CPC分类号： H02M3/073
摘要： Disclosed is a charge pump circuit that operates responsive to a test or general operation mode. The charge pump circuit includes at least one charge pump part. A voltage level sensing block generates a level sensing signal by sensing an output voltage. An oscillator generates complementary pulse signals responsive to the level sensing signal. And a selecting circuit block generates a selected voltage that is one of a high voltage and a supply voltage to the at least one charge pump part, the high voltage having a level higher than the supply voltage.
摘要翻译：公开了一种响应于测试或一般操作模式操作的电荷泵电路。电荷泵电路包括至少一个电荷泵部分。电压电平检测块通过检测输出电压来产生电平检测信号。振荡器响应于电平感测信号产生互补的脉冲信号。并且选择电路块产生对至少一个电荷泵部分的高电压和电源电压之一的选定电压，高电压具有高于电源电压的电平。

7. 发明授权

US06442079B2 Voltage regulator circuit for a semiconductor memory device 失效
标题翻译：半导体存储器件的稳压电路
公开(公告)号：US06442079B2
公开(公告)日：2002-08-27
申请号：US09765692
申请日：2001-01-19
申请人： Byeong-Hoon Lee , Seung-Keun Lee
发明人： Byeong-Hoon Lee , Seung-Keun Lee
IPC分类号： G11C700
CPC分类号： G11C16/30
摘要： A word line voltage generating circuit has a high voltage generator for generating a high voltage is response to an activation signal. In addition it has a regulator circuit that includes two successive regulators. The first regulator receives the high voltage and outputs an intermediate voltage in response to a reference voltage and the activation signal. The first regulator receives the reference voltage, and adjusts the high voltage to deliver a word line voltage. The second stage includes has a depletion-type NMOS transistor, which can clamp the high voltage to a voltage of a required level.
摘要翻译：字线电压发生电路具有用于产生高电压的高电压发生器是对激活信号的响应。此外，它具有包括两个连续调节器的调节器电路。第一调节器接收高电压并响应于参考电压和激活信号输出中间电压。第一个调节器接收参考电压，并调节高电压以输出字线电压。第二级包括具有耗尽型NMOS晶体管，其可以将高电压钳位到所需电平的电压。

8. 发明授权

US5663920A Semiconductor memory word line driver circuit 失效
标题翻译：半导体存储器字线驱动电路
公开(公告)号：US5663920A
公开(公告)日：1997-09-02
申请号：US661109
申请日：1996-06-10
申请人： Seung-Keun Lee
发明人： Seung-Keun Lee
IPC分类号： G11C11/407 , G11C8/08 , G11C16/06 , G11C13/00
CPC分类号： G11C8/08
摘要： A driving circuit having an output terminal includes an input terminal coupled to a first control signal; a first transistor having a current path connected between a pumping voltage and the output terminal and having a control electrode coupled to the first control signal; a second transistor having a current path connected to the output terminal and having a control electrode coupled to the first control signal; and a node connected to the output terminal through the current path of the second transistor and being responsive to a second control signal.
摘要翻译：具有输出端的驱动电路包括耦合到第一控制信号的输入端; 第一晶体管，具有连接在泵浦电压和输出端之间的电流路径，并具有耦合到第一控制信号的控制电极; 第二晶体管，其电流路径连接到所述输出端并且具有耦合到所述第一控制信号的控制电极; 以及通过第二晶体管的电流路径连接到输出端并且响应于第二控制信号的节点。

9. 发明授权

US07327609B2 Methods of program-verifying a multi-bit nonvolatile memory device and circuit thereof 失效
标题翻译：程序验证多位非易失性存储器件及其电路的方法
公开(公告)号：US07327609B2
公开(公告)日：2008-02-05
申请号：US11241291
申请日：2005-09-30
申请人： Bo-Geun Kim , Seung-Keun Lee
发明人： Bo-Geun Kim , Seung-Keun Lee
IPC分类号： G11C16/34
CPC分类号： G11C16/3436
摘要： Methods of verifying a program state may be provided for a non-volatile memory device including a multi-bit memory cell transistor providing more than two different program states. More particularly, the multi-bit memory cell transistor may be programmed from a first program state to a second program state, and a reference memory cell corresponding to the second program state may be selected. After programming the multi-bit memory cell transistor to the second program state and after selecting the reference memory cell corresponding to the second program state, a current flowing through the multi-bit memory cell transistor programmed to the second memory state and a current flowing through the reference memory cell may be compared. Programming the multi-bit memory cell transistor to the second program state may then be verified responsive to comparing the currents flowing through the multi-bit memory cell and the reference memory cell.
摘要翻译：可以为包括提供多于两个不同程序状态的多位存储单元晶体管的非易失性存储器件提供验证程序状态的方法。更具体地，可以将多位存储单元晶体管从第一编程状态编程到第二编程状态，并且可以选择与第二编程状态相对应的参考存储单元。在将多位存储单元晶体管编程到第二编程状态之后，并且在选择与第二编程状态相对应的参考存储单元之后，流过被编程到第二存储器状态的多位存储单元晶体管中的电流和流过第可以比较参考存储单元。响应于比较流过多位存储器单元和参考存储单元的电流，可以将多位存储单元晶体管编程到第二编程状态。

10. 发明授权

US07254061B2 Memory devices using tri-state buffers to discharge data lines, and methods of operating same 失效
标题翻译：使用三态缓冲器来释放数据线的存储器件，以及操作方法
公开(公告)号：US07254061B2
公开(公告)日：2007-08-07
申请号：US11153508
申请日：2005-06-15
申请人： Sang-Wan Nam , Seung-Keun Lee
发明人： Sang-Wan Nam , Seung-Keun Lee
IPC分类号： G11C16/00
CPC分类号： G11C16/26 , G11C7/1051 , G11C7/1057 , G11C7/106
摘要： A memory device includes a sense amplifier circuit, a tri-state buffer, a data latch circuit and a data line. The sense amplifier circuit senses and amplifies a current of a memory cell. The tri-state buffer receives an output of the sense amplifier circuit. The data latch circuit latches an output of the tri-state buffer. The data line connects the tri-state buffer and the data latch circuit. The memory device removes charge on the data line using a latch enable signal, which is applied to the tri-state buffer before a read operation.
摘要翻译：存储器件包括读出放大器电路，三态缓冲器，数据锁存电路和数据线。感测放大器电路感测并放大存储器单元的电流。三态缓冲器接收读出放大器电路的输出。数据锁存电路锁存三态缓冲器的输出。数据线连接三态缓冲器和数据锁存电路。存储器件使用锁存使能信号去除数据线上的电荷，该信号在读取操作之前被施加到三态缓冲器。

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