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1. 发明授权

US09196346B2 Non-volatile memory with LPDRAM 有权
标题翻译：带有LPDRAM的非易失性存储器
公开(公告)号：US09196346B2
公开(公告)日：2015-11-24
申请号：US12018550
申请日：2008-01-23
申请人： Frankie F. Roohparvar
发明人： Frankie F. Roohparvar
IPC分类号： G06F12/12 , G11C11/406 , G06F12/02
CPC分类号： G06F3/0634 , G06F3/0625 , G06F3/0685 , G06F12/023 , G06F13/4068 , G11C11/406 , G11C11/40615 , Y02D10/14 , Y02D10/151
摘要： Memory, systems and devices are disclosed where a non-volatile memory device (such as a Flash memory device) is paired with a LPDRAM memory device or array and configures the LPDRAM by utilizing routines stored in the non-volatile memory executing on a controller or state machine of the either the LPDRAM or non-volatile memory. This allows the configuration of the LPDRAM to be self contained and occur under local control of the controller or state machine of the non-volatile memory (or LPDRAM) utilizing these pre-stored LPDRAM configuration routines, eliminating the need for the system designer to have to account for and configure the LPDRAM and its specific configuration and/or routines with the system processor or operating system.
摘要翻译：公开了存储器，系统和设备，其中非易失性存储器设备（例如闪存设备）与LPDRAM存储器设备或阵列配对，并且通过利用存储在控制器上执行的非易失性存储器中的例程来配置LPDRAM， LPDRAM或非易失性存储器的状态机。这允许LPDRAM的配置是自包含的，并且在使用这些预先存储的LPDRAM配置例程的非易失性存储器（或LPDRAM）的控制器或状态机的本地控制下发生，从而不需要系统设计者具有说明和配置LPDRAM及其与系统处理器或操作系统的特定配置和/或例程。

2. 发明授权

US08797796B2 Cell operation monitoring 有权
标题翻译：电池操作监控
公开(公告)号：US08797796B2
公开(公告)日：2014-08-05
申请号：US13447551
申请日：2012-04-16
申请人： Frankie F. Roohparvar
发明人： Frankie F. Roohparvar
IPC分类号： G11C16/04
CPC分类号： G11C29/52 , G11C11/5628 , G11C11/5642 , G11C16/04 , G11C16/0483 , G11C27/005 , G11C29/00 , G11C29/028 , G11C29/765 , G11C2029/0409 , G11C2211/5646
摘要： Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Atypical cell, block, string, column, row, etc. . . . operation is monitored and locations and type of atypical operation stored. Adjustment of operation is performed based upon the atypical cell operation.
摘要翻译：适于处理和产生表示两个或更多位信息的数据值的模拟数据信号的存储器件有助于相对于器件处理和仅产生指示各个位的二进制数据信号的数据传输速率的增加。这种存储器件的编程包括编程到表示所需位图案的目标阈值电压范围。读取这样的存储器件包括产生指示目标存储器单元的阈值电压的模拟数据信号。非典型单元格，块，字符串，列，行等。。。监视操作并存储非典型操作的位置和类型。基于非典型单元操作执行操作的调整。

3. 发明授权

US08787103B2 Analog-to-digital and digital-to-analog conversion window adjustment based on reference cells in a memory device 有权
标题翻译：基于存储器件中的参考单元的模数和数模转换窗口调整
公开(公告)号：US08787103B2
公开(公告)日：2014-07-22
申请号：US13187665
申请日：2011-07-21
申请人： Vishal Sarin , Jung-Sheng Hoei , Frankie F. Roohparvar
发明人： Vishal Sarin , Jung-Sheng Hoei , Frankie F. Roohparvar
IPC分类号： G11C7/02
CPC分类号： G11C16/06 , G11C7/16 , G11C11/5621 , G11C16/0483 , G11C27/005 , G11C2211/5634
摘要： An analog-to-digital conversion window is defined by reference voltages stored in reference memory cells of a memory device. A first reference voltage is read to define an upper limit of the conversion window and a second reference voltage is read to define a lower limit of the conversion window. An analog voltage representing a digital bit pattern is read from a memory cell and converted to the digital bit pattern by an analog-to-digital conversion process using the conversion window as the limits for the sampling process. This scheme helps in real time tracking of the ADC window with changes in the program window of the memory array.
摘要翻译：模数转换窗口由存储在存储器件的参考存储单元中的参考电压定义。读取第一参考电压以限定转换窗口的上限，并且读取第二参考电压以定义转换窗口的下限。表示数字位模式的模拟电压从存储单元读取，并通过使用转换窗口作为采样处理的限制的模数转换处理转换为数字位模式。该方案通过存储器阵列的程序窗口的改变，有助于实时跟踪ADC窗口。

4. 发明授权

US08773912B2 Soft landing for desired program threshold voltage 有权
标题翻译：软着陆所需的程序阈值电压
公开(公告)号：US08773912B2
公开(公告)日：2014-07-08
申请号：US13547559
申请日：2012-07-12
申请人： Vishal Sarin , Frankie F. Roohparvar , Jung-Sheng Hoei , Jonathan Pabustan
发明人： Vishal Sarin , Frankie F. Roohparvar , Jung-Sheng Hoei , Jonathan Pabustan
IPC分类号： G11C16/04 , G11C11/56
CPC分类号： G11C11/5621 , G11C11/5628 , G11C16/10 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： Methods of programming memory cells are disclosed. In at least one embodiment, programming is accomplished by applying a first set of programming pulses to program to an initial threshold voltage, and applying a second set of programming pulses to program to a final threshold voltage.
摘要翻译：公开了编程存储器单元的方法。在至少一个实施例中，通过应用第一组编程脉冲来编程到初始阈值电压，以及施加第二组编程脉冲来编程到最终阈值电压来实现编程。

5. 发明授权

US08644065B2 Memory system with user configurable density/performance option 有权
标题翻译：具有用户可配置密度/性能选项的内存系统
公开(公告)号：US08644065B2
公开(公告)日：2014-02-04
申请号：US12434371
申请日：2009-05-01
申请人： Frankie F. Roohparvar
发明人： Frankie F. Roohparvar
IPC分类号： G11C11/34 , G06F12/00
CPC分类号： G06F12/0246 , G11C11/5621 , G11C16/0483 , G11C2211/5641
摘要： The memory system has one or more memory dies coupled to a processor or other system controller. Each die has a separate memory array organized into multiple memory blocks. The different memory blocks of each die can be assigned a different memory density by the end user, depending on the desired memory performance and/or memory density. The user configurable density/performance option can be adjusted with special read/write operations or a configuration register having a memory density configuration bit for each memory block.
摘要翻译：存储器系统具有耦合到处理器或其他系统控制器的一个或多个存储器管芯。每个管芯具有组织成多个存储器块的单独的存储器阵列。根据期望的存储器性能和/或存储器密度，每个管芯的不同存储器块可被最终用户分配不同的存储器密度。用户可配置的密度/性能选项可以通过特殊的读/写操作或具有每个存储块的存储器密度配置位的配置寄存器进行调整。

6. 发明授权

US08472254B2 Memory arrays and memory devices 有权
标题翻译：内存阵列和内存设备
公开(公告)号：US08472254B2
公开(公告)日：2013-06-25
申请号：US12824822
申请日：2010-06-28
申请人： Frankie F. Roohparvar
发明人： Frankie F. Roohparvar
IPC分类号： G11C16/04 , G11C5/02 , G11C5/06 , G11C7/18
CPC分类号： G11C16/26 , G11C16/0483
摘要： Strings of series-coupled memory cells selectively coupled to the same bit line may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional memory array architectures. Reading of the memory cells may be accomplished using charge sharing techniques similar to read operations in a DRAM device.
摘要翻译：与传统的存储器阵列架构相比，选择性地耦合到相同位线的串联耦合存储器单元的串可以有助于增加存储器密度，减少的制造步骤和更快的读取操作。可以使用类似于DRAM设备中的读取操作的电荷共享技术来实现对存储器单元的读取。

7. 发明授权

US08400826B2 Coarse and fine programming in a solid state memory 有权
公开(公告)号：US08400826B2
公开(公告)日：2013-03-19
申请号：US13590376
申请日：2012-08-21
申请人： Frankie F. Roohparvar , Vishal Sarin , Jung S. Hoei
发明人： Frankie F. Roohparvar , Vishal Sarin , Jung S. Hoei
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3418
摘要： Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage.

8. 发明授权

US08363473B2 Analog read and write paths in a solid state memory device 有权
标题翻译：固态存储器件中的模拟读写路径
公开(公告)号：US08363473B2
公开(公告)日：2013-01-29
申请号：US13295388
申请日：2011-11-14
申请人： Frankie F. Roohparvar , Vishal Sarin
发明人： Frankie F. Roohparvar , Vishal Sarin
IPC分类号： G11C16/06
CPC分类号： G11C7/10 , G11C7/1048 , G11C11/5628 , G11C16/0483 , G11C27/005 , G11C27/02 , G11C2207/101 , G11C2211/5621
摘要： A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface comprises a plurality of analog data paths that each includes a capacitor for storing charge corresponding to a target voltage to which a selected memory cell, coupled to its respective data path, is to be programmed. A plurality of comparators can be included in the I/O interface, with each such comparator coupled to a respective bit line. Such a comparator can compare a threshold voltage of a selected memory cell to its target voltage and inhibits further programming when the threshold voltage equals or exceeds the target voltage.
摘要翻译：存储器件中的存储器阵列被耦合到模拟I / O数据接口，使得能够将模拟电压电平写入存储器阵列。 I / O接口包括多个模拟数据路径，每个模拟数据路径包括用于存储对应于目标电压的电荷的电容器，耦合到其相应数据路径的所选择的存储器单元将被编程到该目标电压。多个比较器可以包括在I / O接口中，每个这样的比较器耦合到相应的位线。这样的比较器可以将所选存储单元的阈值电压与其目标电压进行比较，并且当阈值电压等于或超过目标电压时禁止进一步的编程。

9. 发明申请

US20130010542A1 PROGRAMMING METHODS AND MEMORIES 有权
标题翻译：编程方法和记忆
公开(公告)号：US20130010542A1
公开(公告)日：2013-01-10
申请号：US13176886
申请日：2011-07-06
申请人： Vishal Sarin , William H. Radke , Frankie F. Roohparvar
发明人： Vishal Sarin , William H. Radke , Frankie F. Roohparvar
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C16/3454
摘要： Methods of programming a memory and memories are disclosed. In at least one embodiment, a memory is programmed by determining a pretarget threshold voltage for a selected cell, wherein the pretarget threshold voltage is determined using pretarget threshold voltage values for at least one neighbor cell of the selected cell.
摘要翻译：公开了对存储器和存储器进行编程的方法。在至少一个实施例中，通过确定所选择的单元的预定阈值电压来对存储器进行编程，其中使用所选单元的至少一个相邻单元的预定阈值电压值来确定预定阈值电压。

10. 发明申请

US20120307576A1 ANALOG SENSING OF MEMORY CELLS WITH A SOURCE FOLLOWER DRIVER IN A SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：用半导体存储器件中的源极驱动器对存储器电池进行模拟感测
公开(公告)号：US20120307576A1
公开(公告)日：2012-12-06
申请号：US13572174
申请日：2012-08-10
申请人： Vishal Sarin , Jung-Sheng Hoei , Frankie F. Roohparvar
发明人： Vishal Sarin , Jung-Sheng Hoei , Frankie F. Roohparvar
IPC分类号： G11C7/00
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/28 , G11C16/3481 , G11C27/02 , G11C27/024 , G11C2211/5634
摘要： Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations.
摘要翻译：公开了存储器件，方法和采样和保持电路，包括包括耦合到位线的采样和保持电路的存储器件。一个这样的采样和保持电路包括读取电路，验证电路和参考电路。读取电路存储从所选存储单元读取的读取阈值电压。验证电路存储与读取的阈值电压相比较的目标阈值电压，以在目标和读取阈值电压基本相等时产生禁止信号。参考电路存储参考阈值电压，该参考阈值电压可用于转换读取阈值电压以补偿晶体管电压降和/或温度变化。

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