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1. 发明授权

US07164610B2 Microcomputer having a flush memory that can be temporarily interrupted during an erase process 失效
标题翻译：具有可在擦除过程中暂时中断的闪存的微型计算机
公开(公告)号：US07164610B2
公开(公告)日：2007-01-16
申请号：US10323771
申请日：2002-12-20
申请人： Hiroyuki Kimura , Kunio Tani , Tetsu Tashiro , Makoto Yamamoto , Toshihiro Sezaki
发明人： Hiroyuki Kimura , Kunio Tani , Tetsu Tashiro , Makoto Yamamoto , Toshihiro Sezaki
IPC分类号： G06F9/312
CPC分类号： G11C16/16 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/344 , G11C2216/22
摘要： A microcomputer with a built-in non-volatile semiconductor memory, which can automatically perform a work of temporarily interrupting automatic writing or automatic erase and accepting an interruption process when an interruption occurs during the automatic writing or automatic erase by using an interrupt request signal for a microcomputer as an external input for controlling automatic writing or automatic erase of a flash memory.
摘要翻译：具有内置非易失性半导体存储器的微型计算机，其可以在自动写入或自动擦除期间通过使用中断请求信号自动执行临时中断自动写入或自动擦除和接受中断处理的工作作为用于控制闪存的自动写入或自动擦除的外部输入的微计算机。

2. 发明授权

US06459640B1 Nonvolatile semiconductor memory and automatic erasing/writing method thereof 有权
标题翻译：非易失性半导体存储器及其自动擦除/写入方法
公开(公告)号：US06459640B1
公开(公告)日：2002-10-01
申请号：US09931243
申请日：2001-08-17
申请人： Kunio Tani , Tomohisa Iba , Tetsu Tashiro , Katsunobu Hongo , Tsutomu Tanaka , Mikio Kamiya , Toshihiro Sezaki , Hiroyuki Kimura
发明人： Kunio Tani , Tomohisa Iba , Tetsu Tashiro , Katsunobu Hongo , Tsutomu Tanaka , Mikio Kamiya , Toshihiro Sezaki , Hiroyuki Kimura
IPC分类号： G11C700
CPC分类号： G11C29/846 , G11C16/0416 , G11C16/10 , G11C16/22
摘要： A nonvolatile semiconductor memory includes a memory block composed of a memory array having a plurality of memory cells arranged in a matrix form, each of the memory cells being composed of a nonvolatile transistor; a memory decoder necessary for erasing/writing/reading data of the nonvolatile transistor in the memory array; a charge pump necessary for erasing/writing/reading the data of the nonvolatile transistor in the memory array; a register having each of a plurality of control signals for controlling the memory decoder and the charge pump allocated to register 1 bit; and an updating device for updating a content of the register by a data processor coupled to the register. By using this updating device to update the content of the register, the memory decoder and the charge pump are controlled, the data of the memory block is erased, and data is written in/read from the nonvolatile transistor. Thus a selecting device other than a laser can be applied for suppressing the increase of an LSI circuit size in the same chip as that for a dedicated control circuit, verifying the disconnected state of a FUSE circuit in the memory, and trimming the FUSE circuit.
摘要翻译：非易失性半导体存储器包括由具有以矩阵形式布置的多个存储单元的存储器阵列组成的存储块，每个存储单元由非易失性晶体管构成; 用于擦除/写入/读取存储器阵列中的非易失性晶体管的数据所需的存储器解码器; 用于擦除/写入/读取存储器阵列中的非易失性晶体管的数据所需的电荷泵; 具有用于控制分配给寄存器1位的存储器解码器和电荷泵的多个控制信号中的每一个的寄存器; 以及更新装置，用于通过耦合到所述寄存器的数据处理器来更新所述寄存器的内容。通过使用该更新装置来更新寄存器的内容，对存储器解码器和电荷泵进行控制，擦除存储块的数据，并且从非易失性晶体管写入/读取数据。因此，可以应用激光以外的选择装置来抑制与专用控制电路相同的芯片中的LSI电路尺寸的增加，验证存储器中的FUSE电路的断开状态以及修整FUSE电路。

3. 发明授权

US06587916B2 Microcomputer with built-in programmable nonvolatile memory 有权
公开(公告)号：US06587916B2
公开(公告)日：2003-07-01
申请号：US09948042
申请日：2001-09-07
申请人： Katsunobu Hongo , Tsutomu Tanaka , Toshihiro Sezaki , Hiroyuki Kimura , Mikio Kamiya , Yasuhiro Ami , Kunio Tani , Tomohisa Iba
发明人： Katsunobu Hongo , Tsutomu Tanaka , Toshihiro Sezaki , Hiroyuki Kimura , Mikio Kamiya , Yasuhiro Ami , Kunio Tani , Tomohisa Iba
IPC分类号： G06F1300
CPC分类号： G06F15/7814
摘要： A microcomputer comprises: a flash memory for storing rewriting control F/W and user S/F; a command register for specifying content of rewriting control; a address register to be subjected to rewriting-control; a data register for specifying data to be written; a power-supply pump circuit in the flash memory; and a control signal register for specifying/outputting a control signal to a memory decoder. A CPU of the microcomputer is capable of accessing these four registers to perform writing or reading. A given bit of the control signal register corresponds to a given control signal. A value written to the register becomes a control signal that will be directly supplied to both of the power supply circuit and the memory decoder, in the flash memory, to control them. By rewriting a set value of this control signal register using the rewriting control F/W according to a specified sequence, processing such as “erase” and “program” of the flash memory is performed. As a result, a layout area of an automatic sequence circuit is decreased, and a change in a sequence is also facilitated.

4. 发明申请

US20050210215A1 Semiconductor device permitting rapid data reading and writing between processor and memory 审中-公开
标题翻译：半导体器件允许在处理器和存储器之间快速读取和写入数据
公开(公告)号：US20050210215A1
公开(公告)日：2005-09-22
申请号：US11081643
申请日：2005-03-17
申请人： Toshihiro Sezaki , Yuji Ueki , Yoshikazu Masao
发明人： Toshihiro Sezaki , Yuji Ueki , Yoshikazu Masao
IPC分类号： G11C11/417 , G06F12/00 , G06F13/16
CPC分类号： G06F13/1689 , Y02D10/14
摘要： In a read operation, a memory circuit successively performs precharge, sense operation and data output operation, each in 0.5 cycle of a clock signal. A write detection circuit, in response to switching from a write operation to a read operation, sends a signal to the memory circuit to make it delay the read operation. The memory circuit delays the read operation by one cycle of the clock signal to prevent destruction of write data. Further, the write detection circuit sends to a processor a signal for switching whether to access the data bus or not, and causes the processor to stop access to the data bus while the read operation is being delayed. Thus, a semiconductor device that can increase data read speed while guaranteeing sufficient data read time from the memory circuit to the data bus is provided.
摘要翻译：在读取操作中，存储器电路在时钟信号的0.5个周期中连续执行预充电，检测操作和数据输出操作。写入检测电路响应于从写入操作到读取操作的切换，向存储器电路发送信号以使其延迟读取操作。存储器电路将读取操作延迟一个周期的时钟信号，以防止写入数据的破坏。此外，写检测电路向处理器发送用于切换是否访问数据总线的信号，并且在读取操作被延迟的同时使处理器停止对数据总线的访问。因此，提供了可以提高数据读取速度同时保证从存储器电路到数据总线的足够的数据读取时间的半导体器件。

5. 发明授权

US06601131B2 Flash memory access control via clock and interrupt management 有权
标题翻译：通过时钟和中断管理进行闪存访问控制
公开(公告)号：US06601131B2
公开(公告)日：2003-07-29
申请号：US09735621
申请日：2000-12-14
申请人： Toshihiro Sezaki , Katsunobu Hongo , Masato Koura
发明人： Toshihiro Sezaki , Katsunobu Hongo , Masato Koura
IPC分类号： G06F1316
CPC分类号： G06F15/7814
摘要： A microcomputer with a built-in flash memory includes a flash controller for controlling writing/erasing of the flash memory in accordance with a command from a CPU. The flash controller produces a CPU rewriting mode designating signal and a busy signal during writing/erasing of the flash memory. In response to the two signals, awaiting mode controller implements a waiting mode by outputting a control signal to open and close an AND gate using the control signal, thereby halting a supply of a clock signal to the CPU in the waiting mode. The microcomputer can reduce the load on software for writing/erasing of the flash memory, and the load on developing software.
摘要翻译：具有内置闪存的微型计算机包括闪存控制器，用于根据来自CPU的命令控制闪存的写入/擦除。闪存控制器在写入/擦除闪存期间产生CPU重写模式指定信号和忙信号。响应于这两个信号，等待模式控制器通过输出控制信号来执行等待模式，以使用控制信号来打开和关闭与门，从而在等待模式中停止向CPU提供时钟信号。微型计算机可以减少软件写入/擦除的负担，以及开发软件的负担。

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