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71. 发明授权

US07817455B2 Random access electrically programmable e-fuse ROM 有权
标题翻译：随机存取电可编程电子熔丝ROM
公开(公告)号：US07817455B2
公开(公告)日：2010-10-19
申请号：US12065202
申请日：2006-08-30
申请人： Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
发明人： Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/165 , G11C29/027
摘要： A one-time-programmable-read-only-memory (OTPROM) is implemented in a two-dimensional array of aggressively scaled suicide migratable e-fuses. Word line selection is performed by decoding logic operating at VDD while the bit line drive is switched between VDD and a higher voltage, Vp, for programming. The OTPROM is thus compatible with and can be integrated with other technologies without a cost adder and supports optimization of the high current path for minimal voltage drop during fuse programming. A differential sense amplifier with a programmable reference is used for improved sense margins and can support an entire bit line rather than sense amplifiers being provided for individual fuses.
摘要翻译：一次性可编程只读存储器（OTPROM）在二维阵列中实现，这些阵列具有大规模的自杀可迁移电子保险丝。通过在VDD处工作的解码逻辑执行字线选择，同时位线驱动器在VDD和较高电压Vp之间切换，用于编程。因此，OTPROM与其他技术兼容，并且可以与其他技术集成，而无需使用成本加法器，并支持在熔丝编程期间最小化电压降的高电流路径的优化。具有可编程参考的差分读出放大器用于改进的检测余量，并且可以支持整个位线，而不是为各个保险丝提供感测放大器。

72. 发明授权

US07816189B2 Vertically stacked field programmable nonvolatile memory and method of fabrication 有权
标题翻译：垂直堆叠现场可编程非易失性存储器和制造方法
公开(公告)号：US07816189B2
公开(公告)日：2010-10-19
申请号：US11925723
申请日：2007-10-26
申请人： Vivek Subramanian , James M. Cleeves
发明人： Vivek Subramanian , James M. Cleeves
IPC分类号： H01L21/82
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
摘要翻译：公开了一种非常高密度的现场可编程存储器。阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。自动对准技术的最大限度地使光刻限制最小化。在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。

73. 发明授权

US07795899B1 Enabling on-chip features via efuses 有权
标题翻译：通过efuses实现片上功能
公开(公告)号：US07795899B1
公开(公告)日：2010-09-14
申请号：US12420056
申请日：2009-04-08
申请人： Gregory F. Grohoski , Christopher H. Olson , Thomas Alan Ziaja , Lawrence A. Spracklen
发明人： Gregory F. Grohoski , Christopher H. Olson , Thomas Alan Ziaja , Lawrence A. Spracklen
IPC分类号： H03K19/00
CPC分类号： G11C17/16 , G11C7/1045 , G11C17/165 , G11C17/18
摘要： Systems and methods for enabling on-chip features via efuses. A system comprises an electronic fuse (Efuse) array (EFA) coupled to each features capability register (FCR) within an instantiated computational block. The EFA comprises a plurality of rows wherein programming an row comprises blowing one or more Efuses of the row. A valid row comprises programmed Efuses corresponding to one or more on-chip enabled features. The EFA is further configured to prevent enabling of disabled on-chip features from occurring subsequent to a predetermined point in time, such as the time of shipping the chip to the field for use by end-users, by establishing a particular default state for electronic fuses and rendering unusable any unprogrammed entries of the EFA. In one embodiment, some features correspond to on-chip hardware cryptographic acceleration. By preventing the ability to re-enable these features after shipping, it is possible to send semiconductor chips to foreign countries with only predetermined features enabled and no threat of disabled features being later enabled.
摘要翻译：通过efuses启用片上功能的系统和方法。系统包括耦合到实例计算块内的每个特征能力寄存器（FCR）的电子熔丝（Efuse）阵列（EFA）。 EFA包括多行，其中编程行包括吹送行的一个或多个Efus。有效的行包括对应于一个或多个片上使能特征的编程的Efuses。 EFA还被配置为防止在预定时间点之后发生禁用的片上特征的启用，诸如将芯片运送到终端用户使用的领域的时间，通过建立电子的特定默认状态保险丝和使得无法使用任何未编程的全民教育条目。在一个实施例中，一些特征对应于片上硬件加密加速。通过防止在运输后重新启用这些功能的能力，可以将半导体芯片发送到国外，只启用预定功能，并且不会启用禁用功能的威胁。

74. 发明申请

US20100195367A1 NONVOLATILE MEMORY AND WRITING METHOD THEREOF, AND SEMICONDUCTOR DEVICE 有权
标题翻译：非易失性存储器及其写入方法及半导体器件
公开(公告)号：US20100195367A1
公开(公告)日：2010-08-05
申请号：US12756342
申请日：2010-04-08
申请人： Kiyoshi Kato
发明人： Kiyoshi Kato
IPC分类号： G11C17/12 , G11C7/22
CPC分类号： H01L27/1266 , G11C7/24 , G11C8/08 , G11C17/14 , G11C17/165 , G11C17/18 , G11C29/787 , G11C29/816 , G11C29/848 , H01L27/1214
摘要： A write-once memory can be written only once to each memory cell; therefore, a defective bit cannot be detected by an actual inspection of writing. Accordingly, as described above, the measures, in which a redundant circuit is provided and the defective bit is modified before shipping, cannot be taken; thus, it is difficult to provide a memory with few defects. It is an object of the present invention to provide a write-once memory where the probability of a defect is reduced considerably. A nonvolatile memory that can be written only once includes a redundant memory cell, a first circuit which allocates an address to the redundant memory cell, a second circuit which outputs a determination signal that expresses whether writing is performed normally or not, and a third circuit, to which the determination signal is inputted, which controls the first circuit and the second circuit.
摘要翻译：一次写入存储器只能写入每个存储单元一次; 因此，实际的写入检查不能检测到有缺陷的位。因此，如上所述，不能采取在运输之前提供冗余电路和有缺陷的位被修改的措施; 因此难以提供缺少缺陷的记忆体。本发明的一个目的是提供一种一次写入的存储器，其中缺陷的概率显着降低。只能写入一次的非易失性存储器包括冗余存储单元，向冗余存储单元分配地址的第一电路，输出表示是否正常执行写入的确定信号的第二电路，以及第三电路，其中输入了确定信号，其控制第一电路和第二电路。

75. 发明授权

US07750335B2 Phase change material structure and related method 有权
标题翻译：相变材料结构及相关方法
公开(公告)号：US07750335B2
公开(公告)日：2010-07-06
申请号：US11839724
申请日：2007-08-16
申请人： Lawrence A. Clevenger , Bruce G. Elmegreen , Deok-Kee Kim , Chandrasekharan Kothandaraman , Lia Krusin-Elbaum , Chung H. Lam , Dennis M. Newns
发明人： Lawrence A. Clevenger , Bruce G. Elmegreen , Deok-Kee Kim , Chandrasekharan Kothandaraman , Lia Krusin-Elbaum , Chung H. Lam , Dennis M. Newns
IPC分类号： H01L47/00
CPC分类号： H01L45/1683 , G11C13/0004 , G11C17/16 , G11C17/165 , H01L45/06 , H01L45/1206 , H01L45/122 , H01L45/126 , H01L45/144 , H01L45/148
摘要： A structure including a phase change material and a related method are disclosed. The structure may include a first electrode; a second electrode; a third electrode; a phase change material electrically connecting the first, second and third electrodes for passing a first current through two of the first, second and third electrodes; and a refractory metal barrier heater layer about the phase change material for converting the phase change material between an amorphous, insulative state and a crystalline, conductive state by application of a second current to the phase change material. The structure may be used as a fuse or a phase change material random access memory (PRAM).
摘要翻译：公开了包括相变材料和相关方法的结构。该结构可以包括第一电极; 第二电极; 第三电极; 相变材料，电连接第一，第二和第三电极，用于使第一电流通过第一，第二和第三电极中的两个; 以及围绕所述相变材料的难熔金属阻挡加热器层，用于通过向相变材料施加第二电流来在非晶态绝缘状态和结晶导电状态之间转换相变材料。该结构可以用作保险丝或相变材料随机存取存储器（PRAM）。

76. 发明申请

US20100165715A1 PROTECTION REGISTER FOR A PHASE-CHANGE MEMORY 有权
标题翻译：相变存储器的保护寄存器
公开(公告)号：US20100165715A1
公开(公告)日：2010-07-01
申请号：US12346504
申请日：2008-12-30
申请人： Enzo Michele Donze , Salvatore Polizzi , Greg Komoto
发明人： Enzo Michele Donze , Salvatore Polizzi , Greg Komoto
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/0059 , G11C16/225 , G11C17/16 , G11C17/165
摘要： A memory device including a memory array comprising a set of phase change memory cells configured to store data. The memory device further includes a protection register including a set of protection cells configured to store protection information of the memory cells. The protection cells of the protection register are memory cells of the memory array.
摘要翻译：一种包括存储器阵列的存储器件，所述存储器阵列包括被配置为存储数据的一组相变存储器单元。存储装置还包括保护寄存器，其包括被配置为存储存储器单元的保护信息的一组保护单元。保护寄存器的保护单元是存储器阵列的存储单元。

77. 发明申请

US20100142299A1 ANTI-FUSE REPAIR CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING DRAM HAVING THE SAME 失效
标题翻译：防熔丝修复控制电路和半导体器件，其中包括具有相同功能的DRAM
公开(公告)号：US20100142299A1
公开(公告)日：2010-06-10
申请号：US12704674
申请日：2010-02-12
申请人： Shin Ho CHU , Sun Mo AN
发明人： Shin Ho CHU , Sun Mo AN
IPC分类号： G11C29/00 , G11C17/18
CPC分类号： G11C17/18 , G11C17/165 , G11C29/44 , G11C29/4401 , G11C29/785 , G11C2229/763
摘要： In an anti-fuse repair control circuit, a semiconductor memory device is integrated into a multi-chip package to perform an anti-fuse repair. An anti-fuse repair control circuit includes a data mask signal input circuit, a cell address enable unit a repair enable unit, and a repair unit. The data mask signal input circuit receives and outputs a data mask signal upon receiving a test control signal for an anti-fuse repair. The cell address enable unit receives an anti-fuse repair address to enable a cell address of an anti-fuse cell to be repaired upon receiving the data mask signal outputted from the data mask signal input circuit. The repair enable unit codes the cell address and output a repair enable signal and a drive signal according to whether or not an anti-fuse cell corresponding to the cell address is enabled. The repair unit supplies a repair voltage to the anti-fuse cell when the repair enable signal, the address, and the drive signal are enabled.
摘要翻译：在反熔丝修复控制电路中，将半导体存储器件集成到多芯片封装中以进行抗熔丝修复。反熔丝修复控制电路包括数据掩模信号输入电路，单元地址使能单元，修复使能单元和修复单元。数据屏蔽信号输入电路在接收到用于反熔丝修复的测试控制信号时，接收并输出数据屏蔽信号。单元地址使能单元接收到反熔丝修复地址，以便在接收到从数据屏蔽信号输入电路输出的数据屏蔽信号时，使反熔丝单元的单元地址能够被修复。修复使能单元根据是否启用与单元地址对应的反熔丝单元，对单元地址进行编码并输出修复使能信号和驱动信号。当修复使能信号，地址和驱动信号被使能时，维修单元向反熔丝单元提供修复电压。

78. 发明授权

US07706177B2 Method of programming cross-point diode memory array 有权
标题翻译：交叉点二极管存储器阵列编程方法
公开(公告)号：US07706177B2
公开(公告)日：2010-04-27
申请号：US12003571
申请日：2007-12-28
申请人： Christopher J. Petti
发明人： Christopher J. Petti
IPC分类号： G11C11/00
CPC分类号： G11C11/5692 , G11C13/00 , G11C13/0023 , G11C13/0069 , G11C17/16 , G11C17/165 , G11C2013/009 , G11C2213/33 , G11C2213/71 , G11C2213/72
摘要： A method of programming a nonvolatile memory array including a plurality of nonvolatile memory cells, a plurality of bit lines, and a plurality of word lines, wherein each memory cell comprises a diode, or a diode and a resistivity switching element is disclosed. The method includes both bias programming the memory cells of the device.
摘要翻译：一种编程包括多个非易失性存储单元，多个位线和多个字线的非易失性存储器阵列的方法，其中每个存储单元包括二极管，或二极管和电阻率开关元件。该方法包括对设备的存储器单元的偏置编程。

79. 发明授权

US07696779B2 System LSI 有权
标题翻译：系统LSI
公开(公告)号：US07696779B2
公开(公告)日：2010-04-13
申请号：US11526816
申请日：2006-09-26
申请人： Yasuhiro Agata , Toshiaki Kawasaki , Masanori Shirahama , Ryuji Nishihara , Shinichi Sumi , Yasue Yamamoto , Hirohito Kikukawa
发明人： Yasuhiro Agata , Toshiaki Kawasaki , Masanori Shirahama , Ryuji Nishihara , Shinichi Sumi , Yasue Yamamoto , Hirohito Kikukawa
IPC分类号： H03K19/173
CPC分类号： G11C5/063 , G11C5/14 , G11C17/165 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.
摘要翻译：系统LSI包括输入/输出部分和逻辑电路部分。输入/输出部分包括具有高于用于逻辑电路部分的电源的电源电压的I / O电源单元和设置有I / O电源线的多个I / O单元，用于提供来自I / O电源单元的源电源。逻辑电路部分包括使用I / O电源单元作为电源的I / O功耗电路。 I / O消耗电路连接到从多个I / O单元中的至少一个中的I / O电源线引出的线。

80. 发明申请

US20100011266A1 PROGRAM VERIFY METHOD FOR OTP MEMORIES 有权
标题翻译： OTP记忆的程序验证方法
公开(公告)号：US20100011266A1
公开(公告)日：2010-01-14
申请号：US12442274
申请日：2007-12-20
申请人： Wlodek Kurjanowicz
发明人： Wlodek Kurjanowicz
IPC分类号： G11C29/52 , G06F11/07 , G11C7/10 , G11C7/00 , G11C8/00 , G11C17/00
CPC分类号： G11C29/52 , G11C5/143 , G11C16/3454 , G11C16/3459 , G11C17/14 , G11C17/16 , G11C17/165 , G11C19/00 , G11C29/027 , G11C2029/0407
摘要： A method for executing a program verify operation in a non-volatile memory. A data register having master and slave latching circuits is used for concurrently storing two different words of data. In a program operation, the master latch stores program data which is used for programming selected memory cells. In a program verify operation, the data programmed to the memory cells are read out and stored in the slave latches. In each data register stage, the logic states of both latches are compared to each other, and a status signal corresponding to a program pass condition is generated if opposite logic states are stored in both latches. The master latch in each stage is inverted if programming was successful, in order to prevent re-programming of that bit of data.
摘要翻译：一种用于在非易失性存储器中执行程序验证操作的方法。具有主和从锁存电路的数据寄存器用于同时存储两个不同的数据字。在程序操作中，主锁存器存储用于编程所选存储单元的程序数据。在程序验证操作中，将编程到存储单元的数据读出并存储在从锁存器中。在每个数据寄存器级中，两个锁存器的逻辑状态彼此进行比较，并且如果相反的逻辑状态存储在两个锁存器中，则产生与程序通过条件相对应的状态信号。如果编程成功，每级中的主锁存器将被反转，以防止该位数据的重新编程。

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