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1. 发明授权

US07795899B1 Enabling on-chip features via efuses 有权
标题翻译：通过efuses实现片上功能
公开(公告)号：US07795899B1
公开(公告)日：2010-09-14
申请号：US12420056
申请日：2009-04-08
申请人： Gregory F. Grohoski , Christopher H. Olson , Thomas Alan Ziaja , Lawrence A. Spracklen
发明人： Gregory F. Grohoski , Christopher H. Olson , Thomas Alan Ziaja , Lawrence A. Spracklen
IPC分类号： H03K19/00
CPC分类号： G11C17/16 , G11C7/1045 , G11C17/165 , G11C17/18
摘要： Systems and methods for enabling on-chip features via efuses. A system comprises an electronic fuse (Efuse) array (EFA) coupled to each features capability register (FCR) within an instantiated computational block. The EFA comprises a plurality of rows wherein programming an row comprises blowing one or more Efuses of the row. A valid row comprises programmed Efuses corresponding to one or more on-chip enabled features. The EFA is further configured to prevent enabling of disabled on-chip features from occurring subsequent to a predetermined point in time, such as the time of shipping the chip to the field for use by end-users, by establishing a particular default state for electronic fuses and rendering unusable any unprogrammed entries of the EFA. In one embodiment, some features correspond to on-chip hardware cryptographic acceleration. By preventing the ability to re-enable these features after shipping, it is possible to send semiconductor chips to foreign countries with only predetermined features enabled and no threat of disabled features being later enabled.
摘要翻译：通过efuses启用片上功能的系统和方法。系统包括耦合到实例计算块内的每个特征能力寄存器（FCR）的电子熔丝（Efuse）阵列（EFA）。 EFA包括多行，其中编程行包括吹送行的一个或多个Efus。有效的行包括对应于一个或多个片上使能特征的编程的Efuses。 EFA还被配置为防止在预定时间点之后发生禁用的片上特征的启用，诸如将芯片运送到终端用户使用的领域的时间，通过建立电子的特定默认状态保险丝和使得无法使用任何未编程的全民教育条目。在一个实施例中，一些特征对应于片上硬件加密加速。通过防止在运输后重新启用这些功能的能力，可以将半导体芯片发送到国外，只启用预定功能，并且不会启用禁用功能的威胁。

2. 发明授权

US08654970B2 Apparatus and method for implementing instruction support for the data encryption standard (DES) algorithm 有权
标题翻译：用于实现数据加密标准（DES）算法的指令支持的装置和方法
公开(公告)号：US08654970B2
公开(公告)日：2014-02-18
申请号：US12414755
申请日：2009-03-31
申请人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
发明人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
IPC分类号： H04K1/00 , H04L9/00
CPC分类号： G06F21/72 , G06F9/30007 , H04L9/0625 , H04L2209/122 , H04L2209/125 , H04L2209/24
摘要： A processor including instruction support for implementing the Data Encryption Standard (DES) block cipher algorithm may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include one or more DES instructions defined within the ISA. In addition, the DES instructions may be executable by the cryptographic unit to implement portions of an DES cipher that is compliant with Federal Information Processing Standards Publication 46-3 (FIPS 46-3). In response to receiving a DES key expansion instruction defined within the ISA, the cryptographic unit may generate one or more expanded cipher keys of the DES cipher key schedule from an input key.
摘要翻译：包括用于实现数据加密标准（DES）块密码算法的指令支持的处理器可以从定义的指令集体系结构（ISA）发出执行编程器可选择的指令。处理器可以包括可以接收执行指令的密码单元。指令包括在ISA内定义的一个或多个DES指令。此外，DES指令可以由加密单元执行，以实现符合联邦信息处理标准出版物46-3（FIPS 46-3）的DES密码的部分。响应于接收到在ISA内定义的DES密钥扩展指令，密码单元可以从输入密钥生成DES密码密钥调度的一个或多个扩展密码密钥。

3. 发明授权

US08417961B2 Apparatus and method for implementing instruction support for performing a cyclic redundancy check (CRC) 有权
标题翻译：用于执行用于执行循环冗余校验（CRC）的指令支持的装置和方法
公开(公告)号：US08417961B2
公开(公告)日：2013-04-09
申请号：US12725243
申请日：2010-03-16
申请人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
发明人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
IPC分类号： G06F11/30
CPC分类号： G06F9/3861 , G06F9/30007 , G06F9/30018 , G06F9/3851 , G06F9/3885 , G06F11/1004 , G06F21/72 , H03M13/09 , H03M13/096 , H03M13/158 , H04L1/0041 , H04L1/0061 , H04L9/0631
摘要： Techniques relating to a processor including instruction support for implementing a cyclic redundancy check (CRC) operation. The processor may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit configured to receive instructions that include a first instance of a cyclic redundancy check (CRC) instruction defined within the ISA, where the first instance of the CRC instruction is executable by the cryptographic unit to perform a first CRC operation on a set of data that produces a checksum value. In one embodiment, the cryptographic unit is configured to generate the checksum value using a generator polynomial of 0x11EDC6F41. In some embodiments, the first instance of the CRC instruction specifies an initial value to be used in performing the first CRC operation, the set of data, and a storage location in which the cryptographic unit is configured to store the checksum value produced by the first CRC operation.
摘要翻译：涉及包括执行循环冗余校验（CRC）操作的指令支持的处理器的技术。处理器可以从定义的指令集体系结构（ISA）发出执行编程器可选择的指令。处理器可以包括被配置为接收包括在ISA内定义的循环冗余校验（CRC）指令的第一实例的指令的加密单元，其中CRC指令的第一实例可由密码单元执行以执行第一CRC操作在产生校验和值的一组数据上。在一个实施例中，密码单元被配置为使用生成器多项式0x11EDC6F41生成校验和值。在一些实施例中，CRC指令的第一实例指定用于执行第一CRC操作，数据集合以及存储位置的初始值，其中密码单元被配置为存储由第一个CRC操作产生的校验和值 CRC操作。

4. 发明申请

US20100250964A1 APPARATUS AND METHOD FOR IMPLEMENTING INSTRUCTION SUPPORT FOR THE CAMELLIA CIPHER ALGORITHM 有权
标题翻译：用于实施CAMELLIA CIPHER算法的指导性支持的装置和方法
公开(公告)号：US20100250964A1
公开(公告)日：2010-09-30
申请号：US12414831
申请日：2009-03-31
申请人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
发明人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30003 , G06F9/30007 , G06F9/30018 , G06F9/30167 , G06F9/382 , G06F9/3851 , G06F9/3877 , H04L9/0625 , H04L2209/122 , H04L2209/125 , H04L2209/24
摘要： A processor including instruction support for implementing the Camellia block cipher algorithm may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include one or more Camellia instructions defined within the ISA. In addition, the Camellia instructions may be executable by the cryptographic unit to implement portions of a Camellia cipher that is compliant with Internet Engineering Task Force (IETF) Request For Comments (RFC) 3713. In response to receiving a Camellia F( )-operation instruction defined within the ISA, the cryptographic unit may perform an F( ) operation, as defined by the Camellia cipher, upon a data input operand and a subkey operand, in which the data input operand and subkey operand may be specified by the Camellia F( )-operation instruction.
摘要翻译：包括用于实现Camellia块密码算法的指令支持的处理器可以从定义的指令集体系结构（ISA）发出用于执行编程器可选择指令的执行。处理器可以包括可以接收执行指令的密码单元。说明书包括在ISA内定义的一个或多个Camellia指令。另外，山茶花指令可以由加密单元执行，以实现符合因特网工程任务组（IETF）请求注释（RFC）3713的Camellia密码的部分。响应于接收到Camellia F（）操作在ISA内定义的指令中，加密单元可以在数据输入操作数和子键操作数上执行由Camellia密码定义的F（）操作，其中数据输入操作数和子键操作数可以由Camellia F （）操作指令。

5. 发明授权

US09317286B2 Apparatus and method for implementing instruction support for the camellia cipher algorithm 有权
标题翻译：用于实现山茶密码算法的指令支持的装置和方法
公开(公告)号：US09317286B2
公开(公告)日：2016-04-19
申请号：US12414831
申请日：2009-03-31
申请人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
发明人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
IPC分类号： G06F9/30 , G06F9/38 , H04L9/06 , G06F15/00
CPC分类号： G06F9/30145 , G06F9/30003 , G06F9/30007 , G06F9/30018 , G06F9/30167 , G06F9/382 , G06F9/3851 , G06F9/3877 , H04L9/0625 , H04L2209/122 , H04L2209/125 , H04L2209/24
摘要： A processor including instruction support for implementing the Camellia block cipher algorithm may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include one or more Camellia instructions defined within the ISA. In addition, the Camellia instructions may be executable by the cryptographic unit to implement portions of a Camellia cipher that is compliant with Internet Engineering Task Force (IETF) Request For Comments (RFC) 3713. In response to receiving a Camellia F( )-operation instruction defined within the ISA, the cryptographic unit may perform an F( ) operation, as defined by the Camellia cipher, upon a data input operand and a subkey operand, in which the data input operand and subkey operand may be specified by the Camellia F( )-operation instruction.
摘要翻译：包括用于实现Camellia块密码算法的指令支持的处理器可以从定义的指令集体系结构（ISA）发出用于执行编程器可选择指令的执行。处理器可以包括可以接收执行指令的密码单元。说明书包括在ISA内定义的一个或多个Camellia指令。另外，山茶花指令可以由加密单元执行，以实现符合因特网工程任务组（IETF）请求注释（RFC）3713的Camellia密码的部分。响应于接收到Camellia F（）操作在ISA内定义的指令中，加密单元可以在数据输入操作数和子键操作数上执行由Camellia密码定义的F（）操作，其中数据输入操作数和子键操作数可以由Camellia F （）操作指令。

6. 发明申请

US20100246815A1 APPARATUS AND METHOD FOR IMPLEMENTING INSTRUCTION SUPPORT FOR THE KASUMI CIPHER ALGORITHM 审中-公开
标题翻译：用于实施KASUMI CIPHER算法的指导性支持的装置和方法
公开(公告)号：US20100246815A1
公开(公告)日：2010-09-30
申请号：US12414871
申请日：2009-03-31
申请人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
发明人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
IPC分类号： H04L9/28 , G06F9/30 , G06F9/312
CPC分类号： G09C1/00 , G06F7/483 , G06F7/722 , G06F9/30007 , G06F9/30018 , G06F9/30145 , G06F9/30167 , G06F9/382 , G06F9/3851 , G06F9/3877 , H04L9/0625 , H04L9/0631 , H04L2209/12 , H04L2209/24
摘要： A processor including instruction support for implementing the Kasumi block cipher algorithm may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include one or more Kasumi instructions defined within the ISA. In addition, the Kasumi instructions may be executable by the cryptographic unit to implement portions of a Kasumi cipher that is compliant with 3rd Generation Partnership Project (3GPP) Technical Specification TS 35.202 version 8.0.0. In response to receiving a Kasumi FL( )-operation instruction defined within the ISA, the cryptographic unit may perform an FL( ) operation, as defined by the Kasumi cipher, upon a data input operand and a subkey operand in which the data input operand and subkey operand may be specified by the Kasumi FL( )-operation instruction.
摘要翻译：包括用于实现Kasumi块密码算法的指令支持的处理器可以从定义的指令集体系结构（ISA）发出用于执行编程器可选择指令的执行。处理器可以包括可以接收执行指令的密码单元。说明包括在ISA内定义的一个或多个Kasumi指令。此外，Kasumi指令可以由密码单元执行，以实现符合第三代合作伙伴计划（3GPP）技术规范TS 35.202版本8.0.0的Kasumi密码的部分。响应于接收到在ISA内定义的Kasumi FL（）操作指令，加密单元可以对数据输入操作数和数据输入操作数的子键操作数执行如Kasumi密码所定义的FL（）操作并且子键操作数可以由Kasumi FL（）操作指令指定。

7. 发明申请

US20100246814A1 APPARATUS AND METHOD FOR IMPLEMENTING INSTRUCTION SUPPORT FOR THE DATA ENCRYPTION STANDARD (DES) ALGORITHM 有权
标题翻译：用于实施数据加密标准（DES）算法的指令支持的装置和方法
公开(公告)号：US20100246814A1
公开(公告)日：2010-09-30
申请号：US12414755
申请日：2009-03-31
申请人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
发明人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
IPC分类号： H04L9/06
CPC分类号： G06F21/72 , G06F9/30007 , H04L9/0625 , H04L2209/122 , H04L2209/125 , H04L2209/24
摘要： A processor including instruction support for implementing the Data Encryption Standard (DES) block cipher algorithm may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include one or more DES instructions defined within the ISA. In addition, the DES instructions may be executable by the cryptographic unit to implement portions of an DES cipher that is compliant with Federal Information Processing Standards Publication 46-3 (FIPS 46-3). In response to receiving a DES key expansion instruction defined within the ISA, the cryptographic unit may generate one or more expanded cipher keys of the DES cipher key schedule from an input key.
摘要翻译：包括用于实现数据加密标准（DES）块密码算法的指令支持的处理器可以从定义的指令集体系结构（ISA）发出执行编程器可选择的指令。处理器可以包括可以接收执行指令的密码单元。指令包括在ISA内定义的一个或多个DES指令。此外，DES指令可以由加密单元执行，以实现符合联邦信息处理标准出版物46-3（FIPS 46-3）的DES密码的部分。响应于接收到在ISA内定义的DES密钥扩展指令，密码单元可以从输入密钥生成DES密码密钥调度的一个或多个扩展密码密钥。

8. 发明申请

US20110231636A1 APPARATUS AND METHOD FOR IMPLEMENTING INSTRUCTION SUPPORT FOR PERFORMING A CYCLIC REDUNDANCY CHECK (CRC) 有权
标题翻译：实施循环冗余检查（CRC）的指导性支持的装置和方法
公开(公告)号：US20110231636A1
公开(公告)日：2011-09-22
申请号：US12725243
申请日：2010-03-16
申请人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
发明人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
IPC分类号： H03M13/09 , H04L9/00 , G06F11/10 , G06F9/302
CPC分类号： G06F9/3861 , G06F9/30007 , G06F9/30018 , G06F9/3851 , G06F9/3885 , G06F11/1004 , G06F21/72 , H03M13/09 , H03M13/096 , H03M13/158 , H04L1/0041 , H04L1/0061 , H04L9/0631
摘要： Techniques relating to a processor including instruction support for implementing a cyclic redundancy check (CRC) operation. The processor may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit configured to receive instructions that include a first instance of a cyclic redundancy check (CRC) instruction defined within the ISA, where the first instance of the CRC instruction is executable by the cryptographic unit to perform a first CRC operation on a set of data that produces a checksum value. In one embodiment, the cryptographic unit is configured to generate the checksum value using a generator polynomial of 0x11EDC6F41. In some embodiments, the first instance of the CRC instruction specifies an initial value to be used in performing the first CRC operation, the set of data, and a storage location in which the cryptographic unit is configured to store the checksum value produced by the first CRC operation.
摘要翻译：涉及包括执行循环冗余校验（CRC）操作的指令支持的处理器的技术。处理器可以从定义的指令集体系结构（ISA）发出执行编程器可选择的指令。处理器可以包括被配置为接收包括在ISA内定义的循环冗余校验（CRC）指令的第一实例的指令的加密单元，其中CRC指令的第一实例可由密码单元执行以执行第一CRC操作在产生校验和值的一组数据上。在一个实施例中，密码单元被配置为使用生成器多项式0x11EDC6F41生成校验和值。在一些实施例中，CRC指令的第一实例指定用于执行第一CRC操作，数据集合和存储位置的初始值，其中密码单元被配置为存储由第一个CRC操作产生的校验和值 CRC操作。

9. 发明申请

US20100257338A1 METHODS AND MECHANISMS TO SUPPORT MULTIPLE FEATURES FOR A NUMBER OF OPCODES 有权
标题翻译：支持多个操作系统的多种功能的方法和机制
公开(公告)号：US20100257338A1
公开(公告)日：2010-10-07
申请号：US12420054
申请日：2009-04-07
申请人： Lawrence A. Spracklen , Gregory F. Grohoski , Christopher H. Olson , Robert T. Golla
发明人： Lawrence A. Spracklen , Gregory F. Grohoski , Christopher H. Olson , Robert T. Golla
IPC分类号： G06F9/30 , G06F9/00
CPC分类号： G06F9/30145 , G06F9/30101 , G06F9/30167 , G06F9/45504
摘要： Systems and methods for efficient instruction support of an multiple features for opcodes of an instruction set. A processor detects a fetched instruction of a computer program comprises an opcode corresponding to a plurality of functions. Each function corresponds to a different type of operation. The processor determines the received instruction corresponds to a feature requested by the computer program, such as a cryptographic algorithm. A determination is made as to whether hardware support exists for the feature. If hardware support exists for the feature, the instruction is executed on-chip by the hardware. Otherwise, software performs the operation corresponding to the instruction.
摘要翻译：用于指令集的操作码的多个特征的有效指令支持的系统和方法。处理器检测计算机程序的获取指令包括对应于多个功能的操作码。每个功能对应于不同类型的操作。处理器确定接收到的指令对应于计算机程序所请求的特征，例如加密算法。确定是否存在该功能的硬件支持。如果该功能存在硬件支持，则该指令由硬件在片上执行。否则，软件将执行与该指令相对应的操作。

10. 发明授权

US08195923B2 Methods and mechanisms to support multiple features for a number of opcodes 有权
标题翻译：支持多个操作码的多个功能的方法和机制
公开(公告)号：US08195923B2
公开(公告)日：2012-06-05
申请号：US12420054
申请日：2009-04-07
申请人： Lawrence A. Spracklen , Gregory F. Grohoski , Christopher H. Olson , Robert T. Golla
发明人： Lawrence A. Spracklen , Gregory F. Grohoski , Christopher H. Olson , Robert T. Golla
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30101 , G06F9/30167 , G06F9/45504
摘要： Systems and methods for efficient instruction support of an multiple features for opcodes of an instruction set. A processor detects a fetched instruction of a computer program comprises an opcode corresponding to a plurality of functions. Each function corresponds to a different type of operation. The processor determines the received instruction corresponds to a feature requested by the computer program, such as a cryptographic algorithm. A determination is made as to whether hardware support exists for the feature. If hardware support exists for the feature, the instruction is executed on-chip by the hardware. Otherwise, software performs the operation corresponding to the instruction.
摘要翻译：用于指令集的操作码的多个特征的有效指令支持的系统和方法。处理器检测计算机程序的获取指令包括对应于多个功能的操作码。每个功能都对应于不同类型的操作。处理器确定接收到的指令对应于计算机程序所请求的特征，例如加密算法。确定是否存在该功能的硬件支持。如果该功能存在硬件支持，则该指令由硬件在片上执行。否则，软件将执行与该指令相对应的操作。

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