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1. 发明授权

US07920437B2 Address control circuit of semiconductor memory apparatus 有权
标题翻译：半导体存储装置的地址控制电路
公开(公告)号：US07920437B2
公开(公告)日：2011-04-05
申请号：US12494474
申请日：2009-06-30
申请人： Sun Mo An
发明人： Sun Mo An
IPC分类号： G11C8/00
CPC分类号： G11C8/18 , G11C11/401 , G11C11/406 , G11C29/02 , G11C29/023 , G11C29/50016
摘要： An address control circuit for a semiconductor memory apparatus so as to make a refresh operation test possible by designating a refresh address is presented. The circuit includes a buffer block, a decoder, and a latch block. The buffer block receives coding information coded testing address information in accordance to a test signal. The decoder generates a test refresh address by decoding the coding information. The latch block latches the test refresh address depending on the test signal.
摘要翻译：提出了一种用于半导体存储装置的地址控制电路，以便通过指定刷新地址进行刷新操作测试。电路包括缓冲块，解码器和锁存块。缓冲块根据测试信号接收编码信息编码的测试地址信息。解码器通过解码编码信息来生成测试刷新地址。锁存块根据测试信号锁存测试刷新地址。

2. 发明申请

US20100309739A1 SEMICONDUCTOR MEMORY APPARATUS AND PROBE TEST CONTROL CIRCUIT THEREFOR 失效
标题翻译：半导体存储器和探头测试控制电路
公开(公告)号：US20100309739A1
公开(公告)日：2010-12-09
申请号：US12642429
申请日：2009-12-18
申请人： Sun Mo AN
发明人： Sun Mo AN
IPC分类号： G11C29/00 , G11C8/00 , G11C8/10
CPC分类号： G11C29/02 , G11C2029/1202
摘要： Disclosed probe test control circuit includes: a bank active circuit configured to generate a bank active signal in response to a bank address and bank-by-bank test control signals; and a mat active circuit configured to generate a mat-by-mat sub-wordline selection signal and provide the mat-by-mat sub-wordline selection signal to a selected memory bank, in response to a row address signal, a row address enable signal and a mat-by-mat test control signal.
摘要翻译：公开的探针测试控制电路包括：存储体有源电路，被配置为响应于存储体地址和逐行测试控制信号产生存储体有效信号; 以及垫活动电路，被配置为响应于行地址信号，生成按字母顺序的子字线选择信号并且将逐个子字符子字线选择信号提供给所选存储体，行地址使能信号和mat-by-mat测试控制信号。

3. 发明申请

US20100142299A1 ANTI-FUSE REPAIR CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING DRAM HAVING THE SAME 失效
标题翻译：防熔丝修复控制电路和半导体器件，其中包括具有相同功能的DRAM
公开(公告)号：US20100142299A1
公开(公告)日：2010-06-10
申请号：US12704674
申请日：2010-02-12
申请人： Shin Ho CHU , Sun Mo AN
发明人： Shin Ho CHU , Sun Mo AN
IPC分类号： G11C29/00 , G11C17/18
CPC分类号： G11C17/18 , G11C17/165 , G11C29/44 , G11C29/4401 , G11C29/785 , G11C2229/763
摘要： In an anti-fuse repair control circuit, a semiconductor memory device is integrated into a multi-chip package to perform an anti-fuse repair. An anti-fuse repair control circuit includes a data mask signal input circuit, a cell address enable unit a repair enable unit, and a repair unit. The data mask signal input circuit receives and outputs a data mask signal upon receiving a test control signal for an anti-fuse repair. The cell address enable unit receives an anti-fuse repair address to enable a cell address of an anti-fuse cell to be repaired upon receiving the data mask signal outputted from the data mask signal input circuit. The repair enable unit codes the cell address and output a repair enable signal and a drive signal according to whether or not an anti-fuse cell corresponding to the cell address is enabled. The repair unit supplies a repair voltage to the anti-fuse cell when the repair enable signal, the address, and the drive signal are enabled.
摘要翻译：在反熔丝修复控制电路中，将半导体存储器件集成到多芯片封装中以进行抗熔丝修复。反熔丝修复控制电路包括数据掩模信号输入电路，单元地址使能单元，修复使能单元和修复单元。数据屏蔽信号输入电路在接收到用于反熔丝修复的测试控制信号时，接收并输出数据屏蔽信号。单元地址使能单元接收到反熔丝修复地址，以便在接收到从数据屏蔽信号输入电路输出的数据屏蔽信号时，使反熔丝单元的单元地址能够被修复。修复使能单元根据是否启用与单元地址对应的反熔丝单元，对单元地址进行编码并输出修复使能信号和驱动信号。当修复使能信号，地址和驱动信号被使能时，维修单元向反熔丝单元提供修复电压。

4. 发明申请

US20100032669A1 SEMICONDUCTOR INTEGRATED CIRCUIT CAPABLE OF CONTROLLING TEST MODES WITHOUT STOPPING TEST 有权
标题翻译：无停止测试控制测试模式的半导体集成电路
公开(公告)号：US20100032669A1
公开(公告)日：2010-02-11
申请号：US12483372
申请日：2009-06-12
申请人： Sun Mo AN , Shin Ho CHU
发明人： Sun Mo AN , Shin Ho CHU
IPC分类号： H01L23/58
CPC分类号： G11C29/46
摘要： A semiconductor integrated circuit capable of controlling test modes without stopping testing of the semiconductor integrated circuit is presented. The semiconductor integrated circuit includes a test mode control unit configured to produce, in response to address decoding signals, a plurality of test mode signals of a first group and a plurality of test mode signals of a second group. The test mode control unit selectively inactivates the test mode signals of the first group by providing a reset signal using the test mode signals of the second group. Therefore, the testing time of the semiconductor integrated circuit can be reduced by inactivating the previous test mode using the reset signal and by executing a new test mode without disconnecting the test mode state.
摘要翻译：提出了能够控制测试模式而不停止半导体集成电路测试的半导体集成电路。半导体集成电路包括：测试模式控制单元，被配置为响应于地址解码信号产生第一组的多个测试模式信号和第二组的多个测试模式信号。测试模式控制单元通过使用第二组的测试模式信号提供复位信号来选择性地使第一组的测试模式信号失效。因此，可以通过使用复位信号使先前的测试模式失效并且通过执行新的测试模式而不断开测试模式状态来减少半导体集成电路的测试时间。

5. 发明授权

US09368237B2 Semiconductor integrated circuit capable of controlling test modes without stopping test 有权
标题翻译：半导体集成电路能够在不停止测试的情况下控制测试模式
公开(公告)号：US09368237B2
公开(公告)日：2016-06-14
申请号：US12483372
申请日：2009-06-12
申请人： Sun Mo An , Shin Ho Chu
发明人： Sun Mo An , Shin Ho Chu
IPC分类号： G11C29/46
CPC分类号： G11C29/46
摘要： A semiconductor integrated circuit capable of controlling test modes without stopping testing of the semiconductor integrated circuit is presented. The semiconductor integrated circuit includes a test mode control unit configured to produce, in response to address decoding signals, a plurality of test mode signals of a first group and a plurality of test mode signals of a second group. The test mode control unit selectively inactivates the test mode signals of the first group by providing a reset signal using the test mode signals of the second group. Therefore, the testing time of the semiconductor integrated circuit can be reduced by inactivating the previous test mode using the reset signal and by executing a new test mode without disconnecting the test mode state.
摘要翻译：提出了能够控制测试模式而不停止半导体集成电路测试的半导体集成电路。半导体集成电路包括：测试模式控制单元，被配置为响应于地址解码信号产生第一组的多个测试模式信号和第二组的多个测试模式信号。测试模式控制单元通过使用第二组的测试模式信号提供复位信号来选择性地使第一组的测试模式信号失效。因此，可以通过使用复位信号使先前的测试模式失效并且通过执行新的测试模式而不断开测试模式状态来减少半导体集成电路的测试时间。

6. 发明授权

US08542548B2 Semiconductor memory device and thermal code output circuit capable of correctly measuring thermal codes 失效
标题翻译：半导体存储器件和能够正确测量热代码的热代码输出电路
公开(公告)号：US08542548B2
公开(公告)日：2013-09-24
申请号：US12228819
申请日：2008-08-15
申请人： Sun Mo An
发明人： Sun Mo An
IPC分类号： G11C7/04
CPC分类号： G11C7/1051 , G11C5/143 , G11C7/04 , G11C7/1063 , G11C11/401 , G11C29/02 , G11C2029/5002
摘要： A thermal code output circuit is provided, comprising a pulse signal generator configured to receive multiple period signals and generate a pulse signal in response to a test mode signal, a thermal code output unit configured to output multiple thermal codes in response to the pulse signal, and a strobing signal output unit configured to output the pulse signal or a reference voltage selectively as a strobing signal in response to the test mode signal.
摘要翻译：提供一种热代码输出电路，包括：脉冲信号发生器，被配置为响应于测试模式信号接收多个周期信号并产生脉冲信号;热代码输出单元，被配置为响应于脉冲信号输出多个热代码，以及选通信号输出单元，被配置为响应于测试模式信号而选择性地输出脉冲信号或参考电压作为选通信号。

7. 发明授权

US08023347B2 Anti-fuse repair control circuit and semiconductor device including DRAM having the same 失效
标题翻译：防熔丝修复控制电路和包括具有相同功能的DRAM的半导体器件
公开(公告)号：US08023347B2
公开(公告)日：2011-09-20
申请号：US12704674
申请日：2010-02-12
申请人： Shin Ho Chu , Sun Mo An
发明人： Shin Ho Chu , Sun Mo An
IPC分类号： G11C7/00
CPC分类号： G11C17/18 , G11C17/165 , G11C29/44 , G11C29/4401 , G11C29/785 , G11C2229/763
摘要： In an anti-fuse repair control circuit, a semiconductor memory device is integrated into a multi-chip package to perform an anti-fuse repair. An anti-fuse repair control circuit includes a data mask signal input circuit, a cell address enable unit a repair enable unit, and a repair unit. The data mask signal input circuit receives and outputs a data mask signal upon receiving a test control signal for an anti-fuse repair. The cell address enable unit receives an anti-fuse repair address to enable a cell address of an anti-fuse cell to be repaired upon receiving the data mask signal outputted from the data mask signal input circuit. The repair enable unit codes the cell address and output a repair enable signal and a drive signal according to whether or not an anti-fuse cell corresponding to the cell address is enabled. The repair unit supplies a repair voltage to the anti-fuse cell when the repair enable signal, the address, and the drive signal are enabled.
摘要翻译：在反熔丝修复控制电路中，将半导体存储器件集成到多芯片封装中以进行抗熔丝修复。反熔丝修复控制电路包括数据掩模信号输入电路，单元地址使能单元，修复使能单元和修复单元。数据屏蔽信号输入电路在接收到用于反熔丝修复的测试控制信号时，接收并输出数据屏蔽信号。单元地址使能单元接收到反熔丝修复地址，以便在接收到从数据屏蔽信号输入电路输出的数据屏蔽信号时，使反熔丝单元的单元地址能够被修复。修复使能单元根据是否启用与单元地址对应的反熔丝单元，对单元地址进行编码并输出修复使能信号和驱动信号。当修复使能信号，地址和驱动信号被使能时，维修单元向反熔丝单元提供修复电压。

8. 发明授权

US07864613B2 Thermal code transmission circuit and semiconductor memory device using the same 有权
标题翻译：热代码传输电路和半导体存储器件使用相同
公开(公告)号：US07864613B2
公开(公告)日：2011-01-04
申请号：US12156836
申请日：2008-06-05
申请人： Sun Mo An , Youk Hee Kim
发明人： Sun Mo An , Youk Hee Kim
IPC分类号： G11C13/00 , G11C1/12
CPC分类号： G11C7/04 , G11C7/1051 , G11C7/1063 , G11C11/406 , G11C11/40626 , G11C11/4093 , G11C2211/4061
摘要： Disclosed are a thermal code transmission circuit and a semiconductor memory device using the same. The thermal code transmission circuit includes a select signal generator which generates a select signal in response to a first enable signal, a level signal generator which receives the first enable signal to generate a level signal, an update signal generator which receives the level signal and a first update signal to generate a second update signal, a latch unit which receives a thermal code in response to the second update signal and outputs the thermal code as an output thermal code, and a thermal code output unit which selectively outputs the output thermal code in response to the select signal.
摘要翻译：公开了热代码传输电路和使用其的半导体存储器件。热代码传输电路包括响应于第一使能信号产生选择信号的选择信号发生器，接收第一使能信号以产生电平信号的电平信号发生器，接收电平信号的更新信号发生器和第一更新信号以产生第二更新信号;锁存单元，其响应于所述第二更新信号接收热代码并输出所述热代码作为输出热代码;以及热代码输出单元，其选择性地输出所述输出热代码响应选择信号。

9. 发明申请

US20090268777A1 Thermal code output circuit and semiconductor memory device 失效
标题翻译：热代码输出电路和半导体存储器件
公开(公告)号：US20090268777A1
公开(公告)日：2009-10-29
申请号：US12228819
申请日：2008-08-15
申请人： Sun Mo An
发明人： Sun Mo An
IPC分类号： G01K7/00 , G01K13/00
CPC分类号： G11C7/1051 , G11C5/143 , G11C7/04 , G11C7/1063 , G11C11/401 , G11C29/02 , G11C2029/5002
摘要： A thermal code output circuit is provided, comprising a pulse signal generator configured to receive multiple period signals and generate a pulse signal in response to a test mode signal, a thermal code output unit configured to output multiple thermal codes in response to the pulse signal, and a strobing signal output unit configured to output the pulse signal or a reference voltage selectively as a strobing signal in response to the test mode signal.
摘要翻译：提供一种热代码输出电路，包括：脉冲信号发生器，被配置为响应于测试模式信号接收多个周期信号并产生脉冲信号;热代码输出单元，被配置为响应于脉冲信号输出多个热代码，以及选通信号输出单元，被配置为响应于测试模式信号而选择性地输出脉冲信号或参考电压作为选通信号。

10. 发明申请

US20090046524A1 MULTI-COLUMN DECODER STRESS TEST CIRCUIT 有权
标题翻译：多列解码器应力测试电路
公开(公告)号：US20090046524A1
公开(公告)日：2009-02-19
申请号：US12168611
申请日：2008-07-07
申请人： Shin-Ho Chu , Sun-Mo An
发明人： Shin-Ho Chu , Sun-Mo An
IPC分类号： G11C29/00 , G11C8/00
CPC分类号： G11C29/02 , G11C8/10 , G11C29/024 , G11C29/025 , G11C2029/1204 , G11C2029/2602
摘要： The embodiments described herein are directed to providing a multi-column decoder stress test circuit capable of reducing a column stress test time while sufficiently performing a stress test by using column selection signals. The multi-column decoder stress test circuit comprising a control unit configured to receive at least one column test signal and to generate a multi-column enable signal, and a multi-enable decoding unit configured to receive the multi-column enable signal and to generate a plurality of enabled column selection signals.
摘要翻译：本文描述的实施例涉及提供一种多列解码器应力测试电路，其能够通过使用列选择信号来充分执行应力测试来减少列应力测试时间。所述多列解码器应力测试电路包括被配置为接收至少一个列测试信号并产生多列使能信号的控制单元，以及多使能解码单元，被配置为接收所述多列使能信号并产生多个启用列选择信号。

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