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1. 发明授权

US08453075B2 Automated lithographic hot spot detection employing unsupervised topological image categorization 失效
标题翻译：自动光刻热点检测采用无监督的拓扑图像分类
公开(公告)号：US08453075B2
公开(公告)日：2013-05-28
申请号：US13224402
申请日：2011-09-02
申请人： Wei Guo , Alan J. Leslie
发明人： Wei Guo , Alan J. Leslie
IPC分类号： G06F17/50
CPC分类号： G03F1/70
摘要： A method for proactively preventing lithographic problems is disclosed, which employs information generated from layout patterns including hot spots in a first technology node to identify hot spots in a second technology node employing a scaled down minimum dimension. In this proactive approach, problematic patterns or complex product geometries are identified in a chip design layout of the second technology node based on detection, in the chip design layout, of topological features that are similar to topological features of known hot spots in the first technology node. The identified patterns are potential hot spots in the chip design layout for the second technology node. Known hot spots in layout patterns in the first technology node are topologically categorized to provide a database for performing the fault detection and diagnosis on the chip design layout.
摘要翻译：公开了一种用于主动防止光刻问题的方法，其采用从包括第一技术节点中的热点的布局模式生成的信息来识别采用缩小的最小尺寸的第二技术节点中的热点。在这种主动的方法中，基于在芯片设计布局中基于第一技术中已知热点的拓扑特征的拓扑特征的检测，在第二技术节点的芯片设计布局中识别有问题的模式或复杂的产品几何形状节点。识别的图案是第二技术节点的芯片设计布局中的潜在热点。第一个技术节点中布局模式的已知热点被拓扑分类，以提供用于在芯片设计布局上执行故障检测和诊断的数据库。

2. 发明申请

US20130061184A1 AUTOMATED LITHOGRAPHIC HOT SPOT DETECTION EMPLOYING UNSUPERVISED TOPOLOGICAL IMAGE CATEGORIZATION 失效
标题翻译：使用自动化的地理热点检测采用不间断的拓扑图像分类
公开(公告)号：US20130061184A1
公开(公告)日：2013-03-07
申请号：US13224402
申请日：2011-09-02
申请人： Wei Guo , Alan J. Leslie
发明人： Wei Guo , Alan J. Leslie
IPC分类号： G06F17/50
CPC分类号： G03F1/70
摘要： A method for proactively preventing lithographic problems is disclosed, which employs information generated from layout patterns including hot spots in a first technology node to identify hot spots in a second technology node employing a scaled down minimum dimension. In this proactive approach, problematic patterns or complex product geometries are identified in a chip design layout of the second technology node based on detection, in the chip design layout, of topological features that are similar to topological features of known hot spots in the first technology node. The identified patterns are potential hot spots in the chip design layout for the second technology node. Known hot spots in layout patterns in the first technology node are topologically categorized to provide a database for performing the fault detection and diagnosis on the chip design layout.
摘要翻译：公开了一种用于主动防止光刻问题的方法，其采用从包括第一技术节点中的热点的布局模式生成的信息来识别采用缩小的最小尺寸的第二技术节点中的热点。在这种主动的方法中，基于在芯片设计布局中基于第一技术中已知热点的拓扑特征的拓扑特征的检测，在第二技术节点的芯片设计布局中识别有问题的模式或复杂的产品几何形状节点。识别的图案是第二技术节点的芯片设计布局中的潜在热点。第一个技术节点中布局模式的已知热点被拓扑分类，以提供用于在芯片设计布局上执行故障检测和诊断的数据库。

3. 发明授权

US07609577B2 Design structure for improving sensing margin of electrically programmable fuses 有权
标题翻译：用于提高电可编程保险丝感应裕度的设计结构
公开(公告)号：US07609577B2
公开(公告)日：2009-10-27
申请号：US11872273
申请日：2007-10-15
申请人： Darren L. Anand , Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
发明人： Darren L. Anand , Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
IPC分类号： G11C7/06
CPC分类号： G11C7/065 , G11C17/165 , G11C17/18 , G11C29/027
摘要： A design structure embodied in a machine readable medium used in a design process includes an apparatus for sensing the state of a programmable resistive memory element device, the apparatus further including a latch device coupled to a fuse node and a reference node, the fuse node included within a fuse leg and the reference node configured within a reference resistance leg, the latch device configured to detect a differential signal developed between the reference node and the fuse node as the result of sense current passed through the fuse leg and the reference resistance leg; and the fuse and reference resistance legs further configured for first and second sensing modes, wherein the second sensing mode utilizes a different level of current than the first sensing mode.
摘要翻译：在设计过程中使用的机器可读介质中体现的设计结构包括用于感测可编程电阻性存储元件装置的状态的装置，该装置还包括耦合到熔丝节点和参考节点的锁存装置，所述熔丝节点包括所述锁存装置被配置为检测在所述参考节点和所述熔丝节点之间产生的差动信号，这是由于感测电流通过所述保险丝腿和所述参考电阻腿的结果; 并且熔丝和参考电阻腿进一步配置用于第一和第二感测模式，其中第二感测模式利用与第一感测模式不同的电流电平。

4. 发明授权

US07525831B2 Method for improving sensing margin of electrically programmable fuses 有权
标题翻译：提高电可编程保险丝感应裕度的方法
公开(公告)号：US07525831B2
公开(公告)日：2009-04-28
申请号：US11868046
申请日：2007-10-05
申请人： Darren L. Anand , Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
发明人： Darren L. Anand , Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
IPC分类号： G11C11/00
CPC分类号： G11C7/065 , G11C17/165 , G11C17/18 , G11C29/027
摘要： A method for determining the state of a programmable resistive memory element includes passing a first level of current through a fuse leg and a reference resistance leg of a test circuit including the programmable resistive memory element; detecting a differential signal developed between a reference node and a fuse node of the test circuit as a result of the first level of current; passing a second level of current through the fuse leg and the reference leg of a test circuit, the second level of current being higher than the first level of current so as to enable detection of trip resistance of the test circuit at a lower value than with respect to the first level of current; and detecting a differential signal developed between the reference node and the fuse node of the test circuit as a result of the second level of current.
摘要翻译：用于确定可编程电阻性存储元件的状态的方法包括使第一电平电流通过包括可编程电阻存储器元件的测试电路的熔丝支脚和参考电阻支路; 检测作为第一电流电平的结果，在测试电路的参考节点和熔丝节点之间产生的差分信号; 使第二电流通过保险丝支脚和测试电路的参考支路，第二电平电流高于第一电流电平，以便能够以比与第一电平相比更低的值检测测试电路的跳闸电阻尊重目前的一级; 以及作为所述第二电流电平的结果，检测在所述参考节点和所述测试电路的所述熔丝节点之间产生的差分信号。

5. 发明授权

US07307911B1 Apparatus and method for improving sensing margin of electrically programmable fuses 有权
标题翻译：用于提高电气可编程保险丝传感距离的装置和方法
公开(公告)号：US07307911B1
公开(公告)日：2007-12-11
申请号：US11460464
申请日：2006-07-27
申请人： Darren L. Anand , Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
发明人： Darren L. Anand , Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
IPC分类号： G11C7/06
CPC分类号： G11C7/065 , G11C17/165 , G11C17/18 , G11C29/027
摘要： An apparatus for sensing the state of a programmable resistive memory element device includes a latch device is coupled to a fuse node and a reference node, the fuse node included within a fuse leg and the reference node configured within a reference resistance leg. The latch device is configured to detect a differential signal developed between the reference node and the fuse node as the result of sense current passed through the fuse leg and the reference resistance leg. The fuse and reference resistance legs are further configured for first and second sensing modes, wherein the second sensing mode utilizes a different level of current than the first sensing mode.
摘要翻译：一种用于感测可编程电阻式存储元件器件的状态的装置包括一个锁存器件耦合到一个熔丝节点和一个参考节点，该熔断器节点包含在一个保险丝支脚内，而该参考节点配置在一个参考电阻支路内。闩锁装置被配置为检测由于感测电流通过保险丝腿和参考电阻腿而导致在参考节点和熔丝节点之间产生的差分信号。熔丝和参考电阻支腿进一步配置用于第一和第二感测模式，其中第二感测模式利用与第一感测模式不同的电流水平。

6. 发明授权

US07817455B2 Random access electrically programmable e-fuse ROM 有权
标题翻译：随机存取电可编程电子熔丝ROM
公开(公告)号：US07817455B2
公开(公告)日：2010-10-19
申请号：US12065202
申请日：2006-08-30
申请人： Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
发明人： Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/165 , G11C29/027
摘要： A one-time-programmable-read-only-memory (OTPROM) is implemented in a two-dimensional array of aggressively scaled suicide migratable e-fuses. Word line selection is performed by decoding logic operating at VDD while the bit line drive is switched between VDD and a higher voltage, Vp, for programming. The OTPROM is thus compatible with and can be integrated with other technologies without a cost adder and supports optimization of the high current path for minimal voltage drop during fuse programming. A differential sense amplifier with a programmable reference is used for improved sense margins and can support an entire bit line rather than sense amplifiers being provided for individual fuses.
摘要翻译：一次性可编程只读存储器（OTPROM）在二维阵列中实现，这些阵列具有大规模的自杀可迁移电子保险丝。通过在VDD处工作的解码逻辑执行字线选择，同时位线驱动器在VDD和较高电压Vp之间切换，用于编程。因此，OTPROM与其他技术兼容，并且可以与其他技术集成，而无需使用成本加法器，并支持在熔丝编程期间最小化电压降的高电流路径的优化。具有可编程参考的差分读出放大器用于改进的检测余量，并且可以支持整个位线，而不是为各个保险丝提供感测放大器。

7. 发明申请

US20080316789A1 Random Access Electrically Programmable E-Fuse Rom 有权
标题翻译：随机存取电子可编程电子保险丝
公开(公告)号：US20080316789A1
公开(公告)日：2008-12-25
申请号：US12065202
申请日：2006-08-30
申请人： Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
发明人： Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
IPC分类号： G11C17/00 , G11C17/16
CPC分类号： G11C17/16 , G11C17/165 , G11C29/027
摘要： A one-time-programmable-read-only-memory (OTPROM) is implemented in a two-dimensional array of aggressively scaled suicide migratable e-fuses. Word line selection is performed by decoding logic operating at VDD while the bit line drive is switched between VDD and a higher voltage, Vp for programming. The OTPROM is thus compatible with and can be integrated with other technologies without a cost adder and supports optimization of the high current path for minimal voltage drop during fuse programming. A differential sense amplifier with a programmable reference is used for improved sense margins and can support an entire bit line rather than sense amplifiers being provided for individual fuses.
摘要翻译：一次性可编程只读存储器（OTPROM）在二维阵列中实现，这些阵列具有大规模的自杀可迁移电子保险丝。字线选择通过在VDD处工作的解码逻辑进行，而位线驱动器在VDD和较高电压Vp之间切换，用于编程。因此，OTPROM与其他技术兼容，并且可以与其他技术集成，而无需使用成本加法器，并支持在熔丝编程期间最小化电压降的高电流路径的优化。具有可编程参考的差分读出放大器用于改进的检测余量，并且可以支持整个位线，而不是为各个保险丝提供感测放大器。

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