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71. 发明授权

US06542991B1 Multiple-thread processor with single-thread interface shared among threads 有权
公开(公告)号：US06542991B1
公开(公告)日：2003-04-01
申请号：US09309734
申请日：1999-05-11
申请人： William N. Joy , Marc Tremblay , Gary Lauterbach , Joseph I. Chamdani
发明人： William N. Joy , Marc Tremblay , Gary Lauterbach , Joseph I. Chamdani
IPC分类号： G06F1212
CPC分类号： G06F9/30141 , G06F9/30127 , G06F9/3804 , G06F9/3851 , G06F9/3885 , G06F9/4843 , G06F12/0842
摘要： A processor includes logic for tagging a thread identifier (TID) for usage with processor blocks that are not stalled. Pertinent non-stalling blocks include caches, translation look-aside buffers (TLB), a load buffer asynchronous interface, an external memory management unit (MMU) interface, and others. A processor includes a cache that is segregated into a plurality of N cache parts. Cache segregation avoids interference, “pollution”, or “cross-talk” between threads. One technique for cache segregation utilizes logic for storing and communicating thread identification (TID) bits. The cache utilizes cache indexing logic. For example, the TID bits can be inserted at the most significant bits of the cache index.

72. 发明申请

US20020138717A1 Multiple-thread processor with single-thread interface shared among threads 有权
标题翻译：线程之间共享单线程接口的多线程处理器
公开(公告)号：US20020138717A1
公开(公告)日：2002-09-26
申请号：US10154076
申请日：2002-05-23
发明人： William N. Joy , Marc Tremblay , Gary Lauterbach , Joseph I. Chamdani
IPC分类号： G06F009/00
CPC分类号： G06F9/30141 , G06F9/30127 , G06F9/3804 , G06F9/3851 , G06F9/3885 , G06F9/4843 , G06F12/0842
摘要： A processor includes logic for tagging a thread identifier (TID) for usage with processor blocks that are not stalled. Pertinent non-stalling blocks include caches, translation look-aside buffers (TLB), a load buffer asynchronous interface, an external memory management unit (MMU) interface, and others. A processor includes a cache that is segregated into a plurality of N cache parts. Cache segregation avoids interference, nullpollutionnull, or nullcross-talknull between threads. One technique for cache segregation utilizes logic for storing and communicating thread identification (TID) bits. The cache utilizes cache indexing logic. For example, the TID bits can be inserted at the most significant bits of the cache index.
摘要翻译：处理器包括用于标记线程标识符（TID）的逻辑，用于未被停止的处理器块的使用。相关的非停滞块包括缓存，翻译后备缓冲器（TLB），加载缓冲器异步接口，外部存储器管理单元（MMU）接口等。处理器包括分离成多个N个高速缓存部分的高速缓存。缓存隔离避免线程间的干扰，“污染”或“串扰”。用于缓存分离的一种技术利用用于存储和传送线程标识（TID）位的逻辑。缓存使用高速缓存索引逻辑。例如，TID位可以插入高速缓存索引的最高有效位。

73. 发明申请

US20020091916A1 Embedded-DRAM-DSP architecture 失效
标题翻译：嵌入式DRAM-DSP架构
公开(公告)号：US20020091916A1
公开(公告)日：2002-07-11
申请号：US10074779
申请日：2002-02-13
发明人： Eric M. Dowling
IPC分类号： G06F015/00 , G06F009/00
CPC分类号： G06F9/3814 , G06F9/30032 , G06F9/3012 , G06F9/30138 , G06F9/30141 , G06F9/3802 , G06F9/3804 , G06F9/383 , G06F9/3842 , G06F9/3851 , G06F12/0862 , G06F15/7821 , G06F2212/6022
摘要： An embedded-DRAM (dynamic random access memory) processor architecture includes a set of DRAM arrays, a set of register files, set of functional units, and a data assembly unit. The data assembly unit includes a set of row-address registers and is responsive to commands to activate and deactivate DRAM rows and to control the movement of data throughout the system. With the present invention, large SRAM (static random access memory) caches and traditional caching policies are replaced with a pipelined data assembly approach so that the functional units perform register-to-register operations, and so that the data assembly unit performs all load/store operations using very wide data busses. Data masking and switching hardware is used to allow individual data words or groups of words to be transferred between the registers and memory. The data assembly unit acts as an intelligent cache controller to perform look-ahead operations to insure exactly those data words that are needed by the functional units are available in a much smaller cache when they are needed. Other aspects of the invention include a memory and logic structure and an associated method to extract data blocks from memory to accelerate, for example, operations related to image compression and decompression. New techniques and structures are also provided to minimize the amount of instruction cache needed to execute programs at full speed from a DRAM-oriented program memory.
摘要翻译：嵌入式DRAM（动态随机存取存储器）处理器架构包括一组DRAM阵列，一组寄存器文件，一组功能单元和数据组合单元。数据组合单元包括一组行地址寄存器，并响应命令来激活和停用DRAM行并且控制数据在整个系统中的移动。利用本发明，大容量SRAM（静态随机存取存储器）高速缓存和传统的缓存策略被流水线数据组合方法替代，使得功能单元执行寄存器到寄存器操作，并且使得数据组装单元执行所有负载/ 存储操作使用非常宽的数据总线。数据屏蔽和切换硬件用于允许各个数据字或字组在寄存器和存储器之间传输。数据组装单元充当智能高速缓存控制器，以执行预先操作，以确保功能单元在需要时在更小的缓存中可用的那些数据字。本发明的其他方面包括存储器和逻辑结构以及从存储器提取数据块以加速例如与图像压缩和解压缩有关的操作的相关方法。还提供了新技术和结构，以最小化从面向DRAM的程序存储器全速执行程序所需的指令高速缓存量。

74. 发明授权

US06378065B1 Apparatus with context switching capability 失效
标题翻译：具有上下文切换能力的装置
公开(公告)号：US06378065B1
公开(公告)日：2002-04-23
申请号：US09069030
申请日：1998-04-27
申请人： Roger D. Arnold , Alfred Eder
发明人： Roger D. Arnold , Alfred Eder
IPC分类号： G06F900
CPC分类号： G06F9/30141 , G06F9/30116 , G06F9/30123 , G06F9/462 , G11C7/00
摘要： The present invention relates to a data processing unit, comprising at least one register having at least one read port and one write port. The register has at least two memory cells each having a write line and a read line, a first switch having inputs and one output for coupling said read line of one of said memory cells with said read port, second switch for coupling said write line of one of said memory cells with said write port.
摘要翻译：本发明涉及一种数据处理单元，包括至少一个具有至少一个读端口和一个写端口的寄存器。寄存器具有至少两个具有写入线和读取线的存储器单元，具有输入的第一开关和用于将所述存储器单元之一的所述读取线与所述读取端口耦合的第一开关，用于将所述写入线所述存储单元中的一个具有所述写入端口。

75. 发明授权

US06374286B1 Real time processor capable of concurrently running multiple independent JAVA machines 失效
标题翻译：能够同时运行多台独立JAVA机器的实时处理器
公开(公告)号：US06374286B1
公开(公告)日：2002-04-16
申请号：US09056126
申请日：1998-04-06
申请人： John K. Gee , David A. Greve , David S. Hardin , Allen P. Mass , Michael H. Masters , Nick M. Mykris , Matthew M. Wilding
发明人： John K. Gee , David A. Greve , David S. Hardin , Allen P. Mass , Michael H. Masters , Nick M. Mykris , Matthew M. Wilding
IPC分类号： G06F952
CPC分类号： G06F9/30141 , G06F9/262 , G06F9/30101 , G06F9/30145 , G06F9/30167 , G06F9/45504 , G06F9/463 , G06F9/4825 , G06F9/4843
摘要： Multiple Java Virtual Machines (JVMs) operate on a single direct execution JAVA processor with each JVM operating in a separate time slice called a partition. Each JVM has its own data and control structures and is assigned a fixed area of memory. Each partition is also allotted a fixed period of time in which to operate, and, at the end of the allotted time, a context switch is forced to another JVM operating in the next partition. The context switch does not transfer control directly from one JVM to another JVM. Instead, at the end of a partition time period control is switched from the currently operating JVM to a “master JVM” during a time period called an “interstice.” The master JVM handles system interrupts and housekeeping duties. At the end of the interstice time period, the master JVM starts a proxy thread associated with the next JVM to become operational. The proxy thread handles JVM-specific interrupts and checks the status of the associated JVM. If the JVM appears operational the proxy thread transfers control to the JVM thread. Time intervals such as partition times and interstice times are enforced by hardware timers and memory accesses are checked by address comparison circuitry to prevent a system failure due to a malfunction in either the master JVM or another JVM.
摘要翻译：多个Java虚拟机（JVM）在单个直接执行JAVA处理器上运行，每个JVM都在称为分区的单独时间片中运行。每个JVM都有自己的数据和控制结构，并分配一个固定的内存区域。每个分区也被分配一段固定的操作时间段，并且在分配的时间结束时，上下文切换被强制到在下一个分区中操作的另一个JVM。上下文切换不会将控制直接从一个JVM传输到另一个JVM。相反，在分区时间段结束时，控制在称为“空格”的时间段内从当前操作的JVM切换到“主JVM”。主JVM处理系统中断和内务管理。在间隔时间段结束时，主JVM启动与下一个JVM相关联的代理线程以便运行。代理线程处理JVM特定的中断并检查关联的JVM的状态。如果JVM出现可操作，则代理线程将控制权转移到JVM线程。时间间隔（如分区时间和间隔时间）由硬件定时器执行，存储器访问由地址比较电路检查，以防止由于主JVM或其他JVM中的故障导致的系统故障。

76. 发明授权

US06351807B1 Data processing system utilizing multiple resister loading for fast domain switching 有权
标题翻译：数据处理系统利用多个寄存器加载快速切换
公开(公告)号：US06351807B1
公开(公告)日：2002-02-26
申请号：US09160904
申请日：1998-09-25
申请人： Ron W. Yoder , Russell W. Guenthner , William A. Shelly , Eric Earl Conway , Boubaker Shaiek , Claude Rabel
发明人： Ron W. Yoder , Russell W. Guenthner , William A. Shelly , Eric Earl Conway , Boubaker Shaiek , Claude Rabel
IPC分类号： G06F935
CPC分类号： G06F9/30043 , G06F9/30141
摘要： A processor (40) in a data processing system simultaneously loads multiple registers (60) with a single value for fast domain switching. A domain switch instruction asserts a register block write signal (112) along with the register write signal (116) when block writing the single value to the set of registers (60). Register address lines (110, 111) are decoded in two sets: a first set of decoded address lines (110) specifying a block of registers; and the second set (111) specifying one register in the block of registers. When the register block write signal (112) is asserted during a register write, the second set of decoded address lines (111) are ignored, and all registers in the block of registers (60) selected by the first set of decoded address lines (110) are simultaneously loaded with a common value. Additional drive requirements are solved either by adding a buffer (226) to each register bit, or by disabling (228) the feedback path (215) in each register bit during block writes.
摘要翻译：数据处理系统中的处理器（40）同时加载多个寄存器（60），其中单个值用于快速切换。当将单个值写入寄存器集合（60）时，域切换指令与寄存器写入信号（116）一起断言寄存器块写入信号（112）。寄存器地址线（110,111）被解码为两组：指定寄存器块的第一组解码地址线（110）并且第二组（111）在寄存器块中指定一个寄存器。当寄存器写入期间寄存器块写入信号（112）被置位时，第二组解码地址线（111）被忽略，并且由第一组解码地址线选择的寄存器块（60）中的所有寄存器 110）同时加载公共值。额外的驱动器要求通过在每个寄存器位中添加缓冲器（226）或在块写入期间通过禁用（228）每个寄存器位中的反馈路径（215）来解决。

77. 发明授权

US06269437B1 Duplicator interconnection methods and apparatus for reducing port pressure in a clustered processor 有权
标题翻译：用于降低集群处理器中端口压力的复制器互连方法和装置
公开(公告)号：US06269437B1
公开(公告)日：2001-07-31
申请号：US09274129
申请日：1999-03-22
申请人： Dean Batten , Paul Gerard D'Arcy , C. John Glossner , Sanjay Jinturkar , Kent E. Wires
发明人： Dean Batten , Paul Gerard D'Arcy , C. John Glossner , Sanjay Jinturkar , Kent E. Wires
IPC分类号： G06F1576
CPC分类号： G06F9/3891 , G06F9/30072 , G06F9/3012 , G06F9/30141 , G06F9/3824 , G06F9/3828 , G06F9/3885
摘要： The invention provides techniques for reducing the port pressure of a clustered processor. In an illustrative embodiment, the processor includes multiple clusters of execution units, with each of the clusters having a portion of a register file and a portion of a predicate file associated therewith, such that a given cluster is permitted to write to and read from its associated portions of the register and predicate files. A duplicator interconnection technique in accordance with the invention reduces port pressure by providing one or more global move units in the processor. A given global move unit uses an inter-cluster move instruction to copy a value from a portion of the register or predicate file associated with a source cluster to another portion of the register or predicate file associated with a destination cluster.
摘要翻译：本发明提供了用于降低集群处理器的端口压力的技术。在说明性实施例中，处理器包括执行单元的多个集群，其中每个集群具有寄存器文件的一部分和与其相关联的谓词文件的一部分，使得给定的集群被允许写入和读取它们寄存器和谓词文件的相关部分。根据本发明的复印机互连技术通过在处理器中提供一个或多个全局移动单元来降低端口压力。给定的全局移动单元使用群间移动指令将来自与源群集相关联的寄存器或谓词文件的一部分的值复制到与目的地群集相关联的寄存器或谓词文件的另一部分。

78. 发明授权

US06266762B1 Information processing apparatus 失效
标题翻译：信息处理装置
公开(公告)号：US06266762B1
公开(公告)日：2001-07-24
申请号：US09227471
申请日：1999-01-08
申请人： Hideyuki Aota , Keiichi Yoshioka
发明人： Hideyuki Aota , Keiichi Yoshioka
IPC分类号： G06F1340
CPC分类号： G06F9/3012 , G06F9/30101 , G06F9/30141
摘要： A general-use register set includes a plurality of registers in a central processing unit body. A register-bank memory has memory regions relevant to the plurality of registers and is connected to the central processing unit. An output signal of an address circuit included in the central processing unit is supplied to the register-bank memory. Alternatively, an output signal of a decoding circuit included in the central processing unit may be supplied to the register-bank memory. A signal for selecting either activation or deactivation of the register-bank memory is a signal which indicates a selection of the deactivation of the register-bank memory except in a case where data is written in the general-use register set and a case of a restoration operation after register bank switching. Instead, a signal for selecting either generating or non-generating of a clock signal for the register-bank memory may be a signal which indicates a selection of the non-generation of the clock signal for the register-bank memory except in a case where data is written in the general-use register set and in a case of a restoration operation after register bank switching.
摘要翻译：通用寄存器组包括在中央处理单元主体中的多个寄存器。寄存器组存储器具有与多个寄存器相关的存储器区域，并且连接到中央处理单元。包括在中央处理单元中的地址电路的输出信号被提供给寄存器组存储器。或者，包括在中央处理单元中的解码电路的输出信号可以被提供给寄存器组存储器。用于选择寄存器组存储器的激活或去激活的信号是指示除了在通用寄存器组中写入数据的情况下的寄存器组存储器的去激活的选择的信号，以及寄存器组切换后的恢复操作。相反，用于选择产生或不产生用于寄存器组存储器的时钟信号的信号可以是指示对于寄存器组存储器的非时钟信号的选择的信号，除了在数据被写入通用寄存器组中，并且在寄存器组切换之后的恢复操作的情况下。

79. 发明授权

US06189089B1 Apparatus and method for retiring instructions in excess of the number of accessible write ports 有权
标题翻译：退出指令超过可访问写入端口数量的装置和方法
公开(公告)号：US06189089B1
公开(公告)日：2001-02-13
申请号：US09227505
申请日：1999-01-06
申请人： Wade A. Walker , D. T. Matheny
发明人： Wade A. Walker , D. T. Matheny
IPC分类号： G06F940
CPC分类号： G06F9/30141 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3867
摘要： A superscalar microprocessor includes a reorder buffer to correctly handle dependency checking and multiple updates to the same destination. The reorder buffer stores instructions in program order, and retires instructions that have executed and the results obtained. When a instruction is retired, the results of the instruction are stored and the memory space in the reorder buffer is deallocated. The results of the retired instructions are stored to a register file via a retire bus. If the results of two or more retired instructions output to the same register in the register file, then only the newest instruction, the later instruction in the original program sequence, is stored to the program register. The register file has a plurality of write ports for the transfer of data via the retire bus. If two retired instructions output to the same register, then a write port is not utilized. The retire window is the number of instructions monitored for retirement. The present invention advantageously increases the size of the retire window. Accordingly, if two or more retired instructions output to the same register, an additional instruction from the retire window can be retired. The additional instruction utilizes the write port not used by the older of the instructions that output to the same register. Thereby, the reorder buffer is emptied at a faster rate and causes less instruction dispatch stalls.
摘要翻译：超标量微处理器包括一个重新排序缓冲器，用于正确地处理相关性检查和对同一目的地的多次更新。重排序缓冲器以程序顺序存储指令，并且退出执行的指令和获得的结果。当指令退出时，存储指令的结果，重新排序缓冲区中的存储空间被释放。退休指令的结果通过退出总线存储到寄存器文件中。如果两个或多个退出指令的结果输出到寄存器文件中的同一个寄存器，则只有最新的指令（原始程序序列中的后续指令）被存储到程序寄存器中。寄存器文件具有用于经由退出总线传送数据的多个写入端口。如果两个退出的指令输出到同一个寄存器，则不会使用写入端口。退休窗口是监控退休指示的次数。本发明有利地增加退休窗口的尺寸。因此，如果两个或多个退出的指令输出到同一个寄存器，退出窗口的附加指令可以退出。附加指令使用未被输出到同一寄存器的较旧的指令使用的写入端口。因此，重新排序缓冲器以更快的速率清空，并且导致较少的指令分派失速。

80. 发明授权

US06175892B1 Registers and methods for accessing registers for use in a single instruction multiple data system 失效
标题翻译：访问寄存器的寄存器和方法用于单指令多数据系统
公开(公告)号：US06175892B1
公开(公告)日：2001-01-16
申请号：US09099989
申请日：1998-06-19
申请人： Sharif Mohammad Sazzad , Larry Pearlstein
发明人： Sharif Mohammad Sazzad , Larry Pearlstein
IPC分类号： G06F1200
CPC分类号： G06F9/30032 , G06F9/30025 , G06F9/30036 , G06F9/30109 , G06F9/30141 , G11C7/1006
摘要： Methods and apparatus for implementing single instruction multiple data (SIMD) signal processing operations are described. The apparatus of the present invention include new registers and register arrays which allow data to be accessed at a word as well as sub-word or sub-register level. The registers and register arrays of the present invention may be used when implementing a system based on a SIMD architecture. Registers implemented in accordance with the present invention include a plurality of pass gates that allow an entire n-bit word stored in the register to be accessed and output as a single word or for a sub-word portion of a stored word to be accessed and output. During standard operation the registers are accessed on a word basis. However, during column access operations, e.g., when performing a transpose operation, access is performed on a sub-word basis. The ability to access the registers of the present invention on a word or sub-word level make implementing transpose and various other row/column data manipulation operations possible in a relatively straightforward manner without data buffering. In addition to the novel registers and register arrays of the present invention, various aspects of the present invention are directed to new and novel SIMD instructions, e.g., SIMD move, add, and move instructions, which support the specification of data to be processed as operands which identify rows or columns of register arrays as opposed to merely identifying registers as done with conventional commands. A transpose command is also supported.
摘要翻译：描述了实现单指令多数据（SIMD）信号处理操作的方法和装置。本发明的装置包括新的寄存器和寄存器阵列，其允许以字以及子字或子寄存器级别访问数据。当基于SIMD架构实现系统时，可以使用本发明的寄存器和寄存器阵列。根据本发明实现的寄存器包括多个通过门，其允许存储在寄存器中的整个n位字被访问并输出为单个字或要存储的字的子字部分被访问，输出。在标准操作期间，寄存器是以字为单位访问的。然而，在列访问操作期间，例如，当执行转置操作时，以子字为基础执行访问。在字或子字级别访问本发明的寄存器的能力使得实现转置和各种其他行/列数据操纵操作可以以相对直接的方式进行，而不需要数据缓冲。除了本发明的新型寄存器和寄存器阵列之外，本发明的各个方面涉及新的和新颖的SIMD指令，例如SIMD移动，添加和移动指令，其支持要处理的数据的规范为识别寄存器阵列的行或列的操作数，而不是像传统命令一样完成标识寄存器。还支持转置命令。

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