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1. 发明授权

US06351807B1 Data processing system utilizing multiple resister loading for fast domain switching 有权
标题翻译：数据处理系统利用多个寄存器加载快速切换
公开(公告)号：US06351807B1
公开(公告)日：2002-02-26
申请号：US09160904
申请日：1998-09-25
申请人： Ron W. Yoder , Russell W. Guenthner , William A. Shelly , Eric Earl Conway , Boubaker Shaiek , Claude Rabel
发明人： Ron W. Yoder , Russell W. Guenthner , William A. Shelly , Eric Earl Conway , Boubaker Shaiek , Claude Rabel
IPC分类号： G06F935
CPC分类号： G06F9/30043 , G06F9/30141
摘要： A processor (40) in a data processing system simultaneously loads multiple registers (60) with a single value for fast domain switching. A domain switch instruction asserts a register block write signal (112) along with the register write signal (116) when block writing the single value to the set of registers (60). Register address lines (110, 111) are decoded in two sets: a first set of decoded address lines (110) specifying a block of registers; and the second set (111) specifying one register in the block of registers. When the register block write signal (112) is asserted during a register write, the second set of decoded address lines (111) are ignored, and all registers in the block of registers (60) selected by the first set of decoded address lines (110) are simultaneously loaded with a common value. Additional drive requirements are solved either by adding a buffer (226) to each register bit, or by disabling (228) the feedback path (215) in each register bit during block writes.
摘要翻译：数据处理系统中的处理器（40）同时加载多个寄存器（60），其中单个值用于快速切换。当将单个值写入寄存器集合（60）时，域切换指令与寄存器写入信号（116）一起断言寄存器块写入信号（112）。寄存器地址线（110,111）被解码为两组：指定寄存器块的第一组解码地址线（110）并且第二组（111）在寄存器块中指定一个寄存器。当寄存器写入期间寄存器块写入信号（112）被置位时，第二组解码地址线（111）被忽略，并且由第一组解码地址线选择的寄存器块（60）中的所有寄存器 110）同时加载公共值。额外的驱动器要求通过在每个寄存器位中添加缓冲器（226）或在块写入期间通过禁用（228）每个寄存器位中的反馈路径（215）来解决。

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