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1. 发明授权

US07047396B1 Fixed length memory to memory arithmetic and architecture for a communications embedded processor system 有权
标题翻译：用于通信嵌入式处理器系统的固定长度存储器到存储器算术和架构
公开(公告)号：US07047396B1
公开(公告)日：2006-05-16
申请号：US09888295
申请日：2001-06-22
申请人： David A. Fotland , Roger D. Arnold , Tibet Mimaroglu
发明人： David A. Fotland , Roger D. Arnold , Tibet Mimaroglu
IPC分类号： G06F7/38
CPC分类号： G06F9/3016 , G06F7/49994 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30167 , G06F9/30192 , G06F9/34 , G06F9/3812
摘要： A method and system for fixed-length memory-to-memory processing of fixed-length instructions. Further, the present invention is a method and system for implementing a memory operand width independent of the ALU width. The arithmetic and register data are 32 bits, but the memory operand is variable in size. The size of the memory operand is specified by the instruction. Instructions in accordance with the present invention allow for multiple memory operands in a single fixed-length instruction. The instruction set is small and simple, so the implementation is lower cost than traditional processors. More addressing modes are provided for, thus creating a more efficient code. Semaphores are implemented using a single bit. Shift-and-merge instructions are used to access data across word boundaries.
摘要翻译：一种固定长度存储器到存储器处理固定长度指令的方法和系统。此外，本发明是用于实现与ALU宽度无关的存储器操作数宽度的方法和系统。算术和寄存器数据是32位，但存储器操作数的大小是可变的。存储器操作数的大小由指令指定。根据本发明的指令允许在单个固定长度指令中的多个存储器操作数。指令集小而简单，所以执行成本比传统处理器低。提供了更多的寻址模式，从而创建了更有效的代码。信号量使用单个位实现。移位和合并指令用于访问跨越边界的数据。

2. 发明授权

US06434689B1 Data processing unit with interface for sharing registers by a processor and a coprocessor 有权
公开(公告)号：US06434689B1
公开(公告)日：2002-08-13
申请号：US09189111
申请日：1998-11-09
申请人： Rod G. Fleck , Roger D. Arnold , Bruce Holmer , Danielle G. Lemay
发明人： Rod G. Fleck , Roger D. Arnold , Bruce Holmer , Danielle G. Lemay
IPC分类号： G06F1500
摘要： An apparatus is described that comprises a data processing unit and at least one coprocessor. The data processing unit comprises a register file having registers, a memory, a plurality of execution units, a coprocessor interface for coupling the at least one coprocessor with the data processing unit, and a pipeline configuration for processing instructions having a fetch stage for fetching an instruction from the memory, a decode stage for decoding an operational code from the instruction, an execution stage for activating one of the execution units, and a write-back stage for God writing back from the execution unit. The data processing unit comprises read-and write-lines coupling the register file with the coprocessor for exchanging operands, at least one control line indicating that the coprocessor is busy, and a plurality of control lines from the decode stage for controlling the coprocessor which are operated upon detection of a coprocessor instruction. The coprocessor is using the registers from the register file during execution of the coprocessor instruction. The coprocessor comprises a decode unit for decoding the coprocessor instruction and a plurality of coprocessor execution units that share the decode unit, the decode unit selects one of the coprocessor execution units upon the coprocessor instruction, and the selected one of the coprocessor execution units performs the coprocessor instruction.

3. 发明授权

US6128641A Data processing unit with hardware assisted context switching capability 失效
标题翻译：具有硬件辅助上下文切换功能的数据处理单元
公开(公告)号：US6128641A
公开(公告)日：2000-10-03
申请号：US928252
申请日：1997-09-12
申请人： Rod G. Fleck , Roger D. Arnold , Bruce Holmer , Vojin G. Oklobdzija , Eric Chesters
发明人： Rod G. Fleck , Roger D. Arnold , Bruce Holmer , Vojin G. Oklobdzija , Eric Chesters
IPC分类号： G06F9/30 , G06F9/46 , G06F9/48 , G06F9/00
CPC分类号： G06F9/30043 , G06F9/30054 , G06F9/462
摘要： The present invention relates to a method of context switching from a first task to a second task in a data processing unit having a register file with a plurality of general purpose registers and a context switch register, a memory comprising a previous context save area and an unused context save area. The memory is coupled with the register file and an instruction control unit with a program counter register and a program status word register coupled with the memory and the register file. The method comprises the steps of acquiring a new save area from said unused save area, storing the context of the first task in said new area, linking the new area with said previous context save area.
摘要翻译：本发明涉及一种在具有多个通用寄存器和上下文切换寄存器的寄存器文件的数据处理单元中的从第一任务到第二任务的上下文切换的方法，包括先前的上下文保存区域的存储器和未使用的上下文保存区域。存储器与寄存器文件和具有程序计数器寄存器的指令控制单元和与存储器和寄存器文件耦合的程序状态字寄存器耦合。该方法包括以下步骤：从所述未使用的保存区域获取新的保存区域，将第一任务的上下文存储在所述新区域中，将新区域与所述先前的上下文保存区域相链接。

4. 发明授权

US07546442B1 Fixed length memory to memory arithmetic and architecture for direct memory access using fixed length instructions 有权
标题翻译：固定长度内存到内存运算和架构，用于使用固定长度指令进行直接内存访问
公开(公告)号：US07546442B1
公开(公告)日：2009-06-09
申请号：US11402089
申请日：2006-04-10
申请人： David A Fotland , Roger D Arnold , Tibet Mimaroglu
发明人： David A Fotland , Roger D Arnold , Tibet Mimaroglu
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F7/49994 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30167 , G06F9/30192 , G06F9/34 , G06F9/3812
摘要： A method and system for fixed-length memory-to-memory processing of fixed-length instructions. Further, the present invention is a method and system for implementing a memory operand width independent of the ALU width. The arithmetic and register data are 32 bits, but the memory operand is variable in size. The size of the memory operand is specified by the instruction. Instructions in accordance with the present invention allow for multiple memory operands in a single fixed-length instruction. The instruction set is small and simple, so the implementation is lower cost than traditional processors. More addressing modes are provided for, thus creating a more efficient code. Semaphores are implemented using a single bit. Shift-and-merge instructions are used to access data across word boundaries.
摘要翻译：一种固定长度存储器到存储器处理固定长度指令的方法和系统。此外，本发明是用于实现与ALU宽度无关的存储器操作数宽度的方法和系统。算术和寄存器数据是32位，但是存储器操作数的大小是可变的。存储器操作数的大小由指令指定。根据本发明的指令允许在单个固定长度指令中的多个存储器操作数。指令集小而简单，所以执行成本比传统处理器低。提供了更多的寻址模式，从而创建了更有效的代码。信号量使用单个位实现。移位和合并指令用于访问跨越边界的数据。

5. 发明授权

US07360203B2 Program tracing in a multithreaded processor 有权
标题翻译：在多线程处理器中进行程序跟踪
公开(公告)号：US07360203B2
公开(公告)日：2008-04-15
申请号：US10774193
申请日：2004-02-06
申请人： Robert E. Ober , Daniel F. Martin , Roger D. Arnold , Erik K. Norden
发明人： Robert E. Ober , Daniel F. Martin , Roger D. Arnold , Erik K. Norden
IPC分类号： G06F9/45
CPC分类号： G06F9/3851 , G06F9/3824 , G06F9/3826 , G06F9/3861
摘要： A multithreaded processor includes a thread ID for each set of fetched bits in an instruction fetch and issue unit. The thread ID attaches to the instructions and operands of the set of fetched bits. Pipeline stages in the multithreaded processor stores the thread ID associated with each operand or instruction in the pipeline stage. The thread ID are used to maintain data coherency and to generate program traces that include thread information for the instructions executed by the multithreaded processor.
摘要翻译：多线程处理器包括在指令获取和发布单元中的每组提取位的线程ID。线程ID附加到获取位集合的指令和操作数。多线程处理器中的管道级存储与流水线级中的每个操作数或指令相关联的线程ID。线程ID用于维护数据一致性并生成包含由多线程处理器执行的指令的线程信息的程序跟踪。

6. 发明授权

US06859873B2 Variable length instruction pipeline 有权
公开(公告)号：US06859873B2
公开(公告)日：2005-02-22
申请号：US09878145
申请日：2001-06-08
申请人： Erik K. Norden , Roger D. Arnold , Robert E. Ober , Neil S. Hastie
发明人： Erik K. Norden , Roger D. Arnold , Robert E. Ober , Neil S. Hastie
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3824 , G06F9/3867
摘要： A variable length instruction pipeline includes optional expansion stages that can be included in the variable length instruction pipeline to avoid pipeline stalls. The expansion stages are removed from the variable length instruction pipeline when not needed to reduce the length of the pipeline, which reduces latency and other problems associated with long pipelines. For example, in one embodiment of the present invention, a variable length instruction pipeline includes a first pipeline stage, a first expansion stage, and a second pipeline stage. The second pipeline stage is configured to selectively receive instructions from the first pipeline stage or the first expansion stage if the first expansion stage holds an instruction.

7. 发明授权

US4583725A Patient support frame for posterior lumbar laminectomy 失效
标题翻译：后腰椎椎板切除术患者支架
公开(公告)号：US4583725A
公开(公告)日：1986-04-22
申请号：US708403
申请日：1985-03-05
申请人： Roger D. Arnold
发明人： Roger D. Arnold
IPC分类号： A61G13/12 , A61G13/00
CPC分类号： A61G13/12 , A61G13/0054 , A61G13/123 , A61G2200/325
摘要： A patient support frame for use on an operating table during posterior lumbar laminectomy surgery comprises a frame for attachment to said table and a pair of iliac crest supports slidably mounted on said frame. The iliac crest supports are adjustable to engage the iliacs, or hipbones, of the patient whereby the prone patient is supported so that the abdomen does not touch the table and is substantially without pressure thereon.
摘要翻译：在后腰椎板切除手术期间用于手术台的患者支撑框架包括用于附接到所述桌子的框架和可滑动地安装在所述框架上的一对髂骨顶部支撑件。髂嵴支撑是可调节的，以接合患者的髂骨或髋骨，由此倾斜患者被支撑，使得腹部不接触桌子并且基本上没有压力。

8. 发明授权

US07774585B2 Interrupt and trap handling in an embedded multi-thread processor to avoid priority inversion and maintain real-time operation 有权
标题翻译：嵌入式多线程处理器中的中断和陷阱处理，以避免优先级倒置并保持实时操作
公开(公告)号：US07774585B2
公开(公告)日：2010-08-10
申请号：US10712473
申请日：2003-11-12
申请人： Robert E. Ober , Roger D. Arnold , Daniel F. Martin , Erik K. Norden
发明人： Robert E. Ober , Roger D. Arnold , Daniel F. Martin , Erik K. Norden
IPC分类号： G06F9/00
CPC分类号： G06F9/4812 , G06F9/462 , G06F13/26
摘要： A real-time, multi-threaded embedded system includes rules for handling traps and interrupts to avoid problems such as priority inversion and re-entrancy. By defining a global interrupt priority value for all active threads and only accepting interrupts having a priority higher than the interrupt priority value, priority inversion can be avoided. Switching to the same thread before any interrupt servicing, and disabling interrupts and thread switching during interrupt servicing can simplify the interrupt handling logic. By storing trap background data for traps and servicing traps only in their originating threads, trap traceability can be preserved. By disabling interrupts and thread switching during trap servicing, unintended trap re-entrancy and servicing disruption can be prevented.
摘要翻译：一个实时的多线程嵌入式系统包括处理陷阱和中断的规则，以避免诸如优先级倒置和重入的问题。通过为所有活动线程定义全局中断优先级值，并且仅接受优先级高于中断优先级值的中断，可以避免优先级反转。在任何中断服务之前切换到同一个线程，并且在中断服务期间禁用中断和线程切换可以简化中断处理逻辑。通过仅在其始发线程中存储陷阱和维护陷阱的陷阱后台数据，可以保留陷阱跟踪性。通过在陷阱维护期间禁用中断和线程切换，可以防止意外的陷阱重入和服务中断。

9. 发明授权

US07263599B2 Thread ID in a multithreaded processor 有权
标题翻译：多线程处理器中的线程ID
公开(公告)号：US07263599B2
公开(公告)日：2007-08-28
申请号：US10774226
申请日：2004-02-06
申请人： Erik K. Norden , Robert E. Ober , Roger D. Arnold , Daniel F. Martin
发明人： Erik K. Norden , Robert E. Ober , Roger D. Arnold , Daniel F. Martin
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3808
摘要： A multithreaded processor includes a thread ID for each set of fetched bits in an instruction fetch and issue unit. The thread ID attaches to the instructions and operands of the set of fetched bits. Pipeline stages in the multithreaded processor stores the thread ID associated with each operand or instruction in the pipeline stage. The thread ID are used to maintain data coherency and to generate program traces that include thread information for the instructions executed by the multithreaded processor.
摘要翻译：多线程处理器包括在指令获取和发布单元中的每组提取位的线程ID。线程ID附加到获取位集合的指令和操作数。多线程处理器中的管道级存储与流水线级中的每个操作数或指令相关联的线程ID。线程ID用于维护数据一致性并生成包含由多线程处理器执行的指令的线程信息的程序跟踪。

10. 发明授权

US07062606B2 Multi-threaded embedded processor using deterministic instruction memory to guarantee execution of pre-selected threads during blocking events 有权
标题翻译：多线程嵌入式处理器使用确定性指令存储器来保证在阻塞事件期间预先选择的线程的执行
公开(公告)号：US07062606B2
公开(公告)日：2006-06-13
申请号：US10431996
申请日：2003-05-07
申请人： Robert E. Ober , Roger D. Arnold , Daniel Martin , Erik K. Norden
发明人： Robert E. Ober , Roger D. Arnold , Daniel Martin , Erik K. Norden
IPC分类号： G06F12/00
CPC分类号： G06F9/3802 , G06F9/3851 , G06F12/126 , G06F2212/2515 , Y02D10/13
摘要： A multi-threaded embedded processor that includes an on-chip deterministic (e.g., scratch or locked cache) memory that persistently stores all instructions associated with one or more pre-selected high-use threads. The processor executes general (non-selected) threads by reading instructions from an inexpensive external memory, e.g., by way of an on-chip standard cache memory, or using other potentially slow, non-deterministic operation such as direct execution from that external memory that can cause the processor to stall while waiting for instructions to arrive. When a cache miss or other blocking event occurs during execution of a general thread, the processor switches to the pre-selected thread, whose execution with zero or minimal delay is guaranteed by the deterministic memory, thereby utilizing otherwise wasted processor cycles until the blocking event is complete.
摘要翻译：一种多线程嵌入式处理器，其包括持续存储与一个或多个预选高使用线程相关联的所有指令的片上确定性（例如，划伤或锁定的高速缓存）存储器。处理器通过从便宜的外部存储器读取指令（例如，通过片上标准高速缓冲存储器）或使用其他潜在的慢速非确定性操作（例如来自该外部存储器的直接执行）来执行通用（未选择）线程这可能导致处理器在等待指令到达时停止。当在一般线程的执行期间出现高速缓存未命中或其他阻塞事件时，处理器切换到预先选择的线程，该线程的执行以零或最小延迟由确定性存储器保证，从而利用其他浪费的处理器周期，直到阻塞事件做完了。

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