专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06829303B1 Methods and apparatus for decoding images using dedicated hardware circuitry and a programmable processor 失效
标题翻译：使用专用硬件电路和可编程处理器对图像进行解码的方法和装置
公开(公告)号：US06829303B1
公开(公告)日：2004-12-07
申请号：US09442363
申请日：1999-11-17
申请人： Larry Pearlstein , Sharif Mohammad Sazzad
发明人： Larry Pearlstein , Sharif Mohammad Sazzad
IPC分类号： H04N712
CPC分类号： H04N19/423 , H04N19/43 , H04N19/44 , H04N19/61
摘要： Video decoder methods and apparatus are described. In accordance with the invention, hardware decoder circuitry, e.g., intra-coded image decoding circuitry and motion vector reconstruction circuitry, is used in combination with a general purpose processor, e.g., Pentium processor, to perform video decoding operations. The video decoder hardware circuitry of the present invention is responsible for performing non-memory intensive functions. The general purpose processor or a general purpose processor operating in conjunction with a graphics processor are used to perform memory intensive video decoding operations such as motion compensated predictions. The video decoding hardware circuitry of the present invention can be implemented as a separate physical device, e.g., chip, or can be implemented on the same physical chip as a general purpose processor with which it works. By using the video decoding hardware circuitry of the present invention in combination with a CPU, a computer system's ability to perform video decoding operations can be significantly increased at little cost in terms of additional hardware.
摘要翻译：描述视频解码器方法和装置。根据本发明，硬件解码器电路，例如帧内编码图像解码电路和运动矢量重构电路，与通用处理器（例如奔腾处理器）结合使用，以执行视频解码操作。本发明的视频解码器硬件电路负责执行非存储器密集型功能。与图形处理器结合操作的通用处理器或通用处理器用于执行存储密集型视频解码操作，例如运动补偿预测。本发明的视频解码硬件电路可以被实现为单独的物理设备，例如芯片，或者可以在与其工作的通用处理器相同的物理芯片上实现。通过使用本发明的视频解码硬件电路与CPU的组合，计算机系统的执行视频解码操作的能力可以在额外的硬件方面以很小的成本显着增加。

2. 发明授权

US06175892B1 Registers and methods for accessing registers for use in a single instruction multiple data system 失效
标题翻译：访问寄存器的寄存器和方法用于单指令多数据系统
公开(公告)号：US06175892B1
公开(公告)日：2001-01-16
申请号：US09099989
申请日：1998-06-19
申请人： Sharif Mohammad Sazzad , Larry Pearlstein
发明人： Sharif Mohammad Sazzad , Larry Pearlstein
IPC分类号： G06F1200
CPC分类号： G06F9/30032 , G06F9/30025 , G06F9/30036 , G06F9/30109 , G06F9/30141 , G11C7/1006
摘要： Methods and apparatus for implementing single instruction multiple data (SIMD) signal processing operations are described. The apparatus of the present invention include new registers and register arrays which allow data to be accessed at a word as well as sub-word or sub-register level. The registers and register arrays of the present invention may be used when implementing a system based on a SIMD architecture. Registers implemented in accordance with the present invention include a plurality of pass gates that allow an entire n-bit word stored in the register to be accessed and output as a single word or for a sub-word portion of a stored word to be accessed and output. During standard operation the registers are accessed on a word basis. However, during column access operations, e.g., when performing a transpose operation, access is performed on a sub-word basis. The ability to access the registers of the present invention on a word or sub-word level make implementing transpose and various other row/column data manipulation operations possible in a relatively straightforward manner without data buffering. In addition to the novel registers and register arrays of the present invention, various aspects of the present invention are directed to new and novel SIMD instructions, e.g., SIMD move, add, and move instructions, which support the specification of data to be processed as operands which identify rows or columns of register arrays as opposed to merely identifying registers as done with conventional commands. A transpose command is also supported.
摘要翻译：描述了实现单指令多数据（SIMD）信号处理操作的方法和装置。本发明的装置包括新的寄存器和寄存器阵列，其允许以字以及子字或子寄存器级别访问数据。当基于SIMD架构实现系统时，可以使用本发明的寄存器和寄存器阵列。根据本发明实现的寄存器包括多个通过门，其允许存储在寄存器中的整个n位字被访问并输出为单个字或要存储的字的子字部分被访问，输出。在标准操作期间，寄存器是以字为单位访问的。然而，在列访问操作期间，例如，当执行转置操作时，以子字为基础执行访问。在字或子字级别访问本发明的寄存器的能力使得实现转置和各种其他行/列数据操纵操作可以以相对直接的方式进行，而不需要数据缓冲。除了本发明的新型寄存器和寄存器阵列之外，本发明的各个方面涉及新的和新颖的SIMD指令，例如SIMD移动，添加和移动指令，其支持要处理的数据的规范为识别寄存器阵列的行或列的操作数，而不是像传统命令一样完成标识寄存器。还支持转置命令。

3. 发明授权

US08760574B2 Image processing methods and systems for frame rate conversion 有权
标题翻译：用于帧速率转换的图像处理方法和系统
公开(公告)号：US08760574B2
公开(公告)日：2014-06-24
申请号：US12433686
申请日：2009-04-30
申请人： Larry Pearlstein , Samir Hulyalkar
发明人： Larry Pearlstein , Samir Hulyalkar
IPC分类号： H04N7/01
CPC分类号： G06T3/4007 , G09G5/006 , G09G2340/0435 , H04N7/0132 , H04N7/0135
摘要： An image processing method for frame rate conversion, comprising: receiving a stream of input pictures at an input frame rate, at least some of the input pictures being new pictures, the new pictures appearing within the stream of input pictures at an underlying new picture rate; generating interpolated pictures from certain ones of the input pictures; outputting a stream of output pictures at an output frame rate, the stream of output pictures including a blend of the new pictures and the interpolated pictures, the interpolated pictures appearing in the stream of output pictures at an average interpolated picture rate; and causing a variation in the average interpolated picture rate in response to detection of a variation in the underlying new picture rate.
摘要翻译：一种用于帧速率转换的图像处理方法，包括：以输入帧速率接收输入图像流，所述输入图像中的至少一些是新图像，所述新图像以基本新图像速率出现在所述输入图像流内 ; 从某些输入图像生成内插图像; 以输出帧速率输出输出图像流，输出图像流包括新图像和内插图像的混合，内插图像以平均内插图像速率出现在输出图像流中; 并且响应于底层新图像速率的变化的检测而导致平均内插图像速率的变化。

4. 发明授权

US07782938B2 Methods for reduced cost insertion of video subwindows into compressed video 失效
标题翻译：将视频子窗口成本插入压缩视频的方法
公开(公告)号：US07782938B2
公开(公告)日：2010-08-24
申请号：US10617605
申请日：2003-07-11
申请人： Larry Pearlstein
发明人： Larry Pearlstein
IPC分类号： H04B1/66
CPC分类号： H04N19/51 , H04N19/55 , H04N21/23892
摘要： Methods and apparatus for encoding image data to facilitate subsequent insertion of local image data. Also methods and apparatus for inserting image data, e.g., at local broadcast stations, without having to fully decode a received encoded bitstream. The encoding methods involve treating images to be encoded as a plurality of distinct, non-overlapping image regions or segments for encoding purposes. Image segments which are designated for use for local data insertion are not used as reference data for motion compensated prediction purposes when generating motion vectors to represent image areas, e.g., the area representing the main picture, which are outside the local data insertion segments. Because image segments which may be replaced are not used as reference data for image segments which will not be replaced, unintentional prediction errors which might otherwise result from replacing one or more image segments as part of a local data insertion operation are avoided.
摘要翻译：用于编码图像数据以便于随后插入局部图像数据的方法和装置。以及用于例如在本地广播站插入图像数据的方法和装置，而不必完全解码所接收的编码比特流。编码方法涉及将图像编码为用于编码目的的多个不同的，不重叠的图像区域或片段。指定用于本地数据插入的图像段在生成用于表示图像区域（例如，表示主图像的区域）的运动矢量时不用作用于运动补偿预测目的的参考数据，其在本地数据插入段之外。由于可以替换的图像段不被用作不被替换的图像段的参考数据，因此避免了由于将一个或多个图像段替换为本地数据插入操作的一部分而导致的意外预测误差。

5. 发明申请

US20090316041A1 METHOD AND APPARATUS FOR PROCESSING IMAGE DATA 失效
标题翻译：用于处理图像数据的方法和装置
公开(公告)号：US20090316041A1
公开(公告)日：2009-12-24
申请号：US12144018
申请日：2008-06-23
申请人： Larry Pearlstein , Richard K. Sita
发明人： Larry Pearlstein , Richard K. Sita
IPC分类号： H04N5/917
CPC分类号： H04N5/91 , H04N5/765 , H04N19/184
摘要： A method and apparatus of processing image data comprises receiving a video data signal where each pixel is represented by one or more digitized components, each digitized component being represented by a first set of binary digits and a second set of binary digits. The first set of binary digits is stored in a first memory plane and the second set of binary digits is stored in a second memory plane. The first set of binary digits is extracted and undergoes first and second processing. The second set of binary digits is extracted and undergoes second processing.
摘要翻译：处理图像数据的方法和装置包括：接收视频数据信号，其中每个像素由一个或多个数字化分量表示，每个数字化分量由第二组二进制数字和第二组二进制数字表示。第一组二进制数字存储在第一存储器平面中，第二组二进制数字被存储在第二存储器平面中。提取第一组二进制数字并进行第一和第二处理。提取第二组二进制数字并进行第二次处理。

6. 发明申请

US20090290789A1 METHOD AND APPARATUS FOR REDUCED COMPLEXITY VIDEO PROCESSING VIA SPECIAL CHROMA HANDLING 有权
标题翻译：通过特殊色彩处理降低复杂视频处理的方法和装置
公开(公告)号：US20090290789A1
公开(公告)日：2009-11-26
申请号：US12126321
申请日：2008-05-23
申请人： Kathleen Burns , Larry Pearlstein
发明人： Kathleen Burns , Larry Pearlstein
IPC分类号： G06K9/00
CPC分类号： H04N9/643 , G09G3/2003 , G09G5/02 , G09G5/028 , G09G5/04 , G09G5/363
摘要： A method and apparatus for reduced complexity video and image processing with special chroma handling are disclosed. Frame-type decisions are made on a video stream made up of a sequence of frames. A first subset of the frames are selected to be monochrome and generated without chroma data. A second subset of the frames are selected to be in color and generated with chroma components. In one embodiment, the first subset of frames includes odd frames and the second subset of frames includes even frames in the video stream. Under higher video frame rates, the lack of color in every other frame is not visible to the end viewer. Accordingly, subsequent processing of the output video stream permits luma-only processing of many frames in the video stream, extensively reducing the amount of computation.
摘要翻译：公开了一种用于降低复杂度的具有特殊色度处理的视频和图像处理的方法和装置。在由一系列帧组成的视频流上进行帧型决定。帧的第一子集被选择为单色并且没有色度数据生成。帧的第二子集被选择为彩色并由色度分量生成。在一个实施例中，帧的第一子集包括奇数帧，并且帧的第二子集包括视频流中的偶数帧。在更高的视频帧速率下，每个其他帧中缺少颜色对于终端观看者是不可见的。因此，输出视频流的后续处理允许视频流中许多帧的仅亮度处理，从而大大减少了计算量。

7. 发明授权

US07573938B2 Methods and apparatus for decoding and displaying different resolution video signals 失效
标题翻译：用于解码和显示不同分辨率视频信号的方法和装置
公开(公告)号：US07573938B2
公开(公告)日：2009-08-11
申请号：US11839367
申请日：2007-08-15
申请人： Jill MacDonald Boyce , Larry Pearlstein
发明人： Jill MacDonald Boyce , Larry Pearlstein
IPC分类号： H04N7/24 , H04N5/445
CPC分类号： H04N19/00 , G06T3/40 , G06T3/4007 , G06T3/4084 , G11B5/0086 , G11B15/125 , G11B15/1875 , G11B15/4673 , H04N5/4401 , H04N5/45 , H04N5/46 , H04N5/78263 , H04N9/8042 , H04N9/8227 , H04N19/13 , H04N19/30 , H04N19/40 , H04N19/42 , H04N19/423 , H04N19/59 , H04N19/61 , H04N19/91 , H04N21/23106 , H04N21/2343 , H04N21/236 , H04N21/2662 , H04N21/4316 , H04N21/4325 , H04N21/434 , H04N21/4382 , H04N21/4402 , H04N21/440254 , H04N21/440263 , H04N21/4621
摘要： Methods and apparatus for implementing a reduced cost HDTV/SDTV video decoder are disclosed. The described joint video decoder is capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.
摘要翻译：公开了实现降低成本的HDTV / SDTV视频解码器的方法和装置。所描述的联合视频解码器能够以大约分辨率的标准清晰度电视图像解码HDTV图像，并且可以用于解码HDTV和/或SDTV图像。所描述的视频解码器可以用作画中画解码器电路的一部分，用于在不提供多个全分辨率视频解码器的情况下提供画中画能力。解码器电路复杂度的降低通过使用多种数据简化技术来实现，包括使用预备器，下采样和截取像素值。

8. 发明授权

US07132963B2 Methods and apparatus for processing variable length coded data 有权
标题翻译：用于处理可变长度编码数据的方法和装置
公开(公告)号：US07132963B2
公开(公告)日：2006-11-07
申请号：US11046048
申请日：2005-01-28
申请人： Larry Pearlstein , Richard Sita , Richard Selvaggi
发明人： Larry Pearlstein , Richard Sita , Richard Selvaggi
IPC分类号： H03M7/40
CPC分类号： H03M7/40
摘要： An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.
摘要翻译：用于处理可变长度编码数据的装置包括系数缓冲器单元和若干查找表。系数缓冲单元包括系数存储器和索引寄存器，用于存储系数存储器中存储的系数的非零性质的指示。有利地，可以改变查找表以适应用于处理可变长度编码数据的装置，以处理遵守特定标准的编码或解码视频。此外，查找表可以适于加速对转义码的存在的确定和随后的转义码的处理。

9. 发明申请

US20060095712A1 SIMD processor having enhanced operand storage interconnects 有权
公开(公告)号：US20060095712A1
公开(公告)日：2006-05-04
申请号：US10940150
申请日：2004-09-13
申请人： Richard Selvaggi , Larry Pearlstein
发明人： Richard Selvaggi , Larry Pearlstein
IPC分类号： G06F15/00
CPC分类号： G06F9/30014 , G06F7/509 , G06F7/544 , G06F7/5443 , G06F9/30036 , G06F9/3885 , G06F2207/3828
摘要： A SIMD processor includes an ALU having data interconnects facilitating the concurrent processing of overlapping data portions of at least one operand store. Such interconnects facilitate the calculation of shift-invariant convolutions, and sum of absolute differences between an operand in the operand store and another operand.

10. 发明申请

US20060059484A1 Method and apparatus for managing tasks in a multiprocessor system 有权
标题翻译：用于管理多处理器系统中的任务的方法和装置
公开(公告)号：US20060059484A1
公开(公告)日：2006-03-16
申请号：US10939804
申请日：2004-09-13
申请人： Richard Selvaggi , Larry Pearlstein
发明人： Richard Selvaggi , Larry Pearlstein
IPC分类号： G06F9/46
CPC分类号： G06F9/4843 , G06F9/544
摘要： In a multiprocessor system, a task control processor may be placed in the path connecting each execution processor to a system bus. Such task control processors may detect the completion of a first task on an associated execution processor and, responsively, generate commands to lead to the initiation of a second task on the same, or another, execution processor. Such task completion detection and task initiation by the task control processors removes, from a central processor or the execution processors, the burden of performing such tasks, thereby improving the efficiency of the entire system.
摘要翻译：在多处理器系统中，可以将任务控制处理器放置在将每个执行处理器连接到系统总线的路径中。这样的任务控制处理器可以检测相关联的执行处理器上的第一任务的完成，并且响应地产生命令以导致在同一个或另一个执行处理器上启动第二个任务。任务控制处理器的这种任务完成检测和任务启动从中央处理器或执行处理器移除执行这些任务的负担，从而提高整个系统的效率。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式