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71. 发明授权

US07474558B2 Gated diode nonvolatile memory cell array 有权
标题翻译：门极二极管非易失性存储单元阵列
公开(公告)号：US07474558B2
公开(公告)日：2009-01-06
申请号：US11865616
申请日：2007-10-01
申请人： Yi Ying Liao , Wen Jer Tsai , Chih Chieh Yeh
发明人： Yi Ying Liao , Wen Jer Tsai , Chih Chieh Yeh
IPC分类号： G11C11/36
CPC分类号： G11C11/36 , B82Y10/00 , G11C16/02 , G11C2216/06 , H01L27/1021 , H01L29/8616
摘要： A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.
摘要翻译：具有电荷存储结构的门控二极管非易失性存储单元包括具有附加栅极端子的二极管结构。示例性实施例包括单独的存储器单元，这种存储器单元的阵列，操作存储单元或存储单元阵列的方法及其制造方法。

72. 发明授权

US07439085B2 Method and apparatus for electroluminescence 有权
标题翻译：电致发光的方法和装置
公开(公告)号：US07439085B2
公开(公告)日：2008-10-21
申请号：US11749006
申请日：2007-05-15
申请人： Chih Chieh Yeh , Shaw Hung Ku , Tahui Wang , Chih Yuan Lu
发明人： Chih Chieh Yeh , Shaw Hung Ku , Tahui Wang , Chih Yuan Lu
IPC分类号： H01L21/00
CPC分类号： H01L33/02 , H01L33/0004
摘要： Methods and apparatuses for causing electroluminescence with charge trapping structures are disclosed. Various embodiments relate to methods and apparatuses for causing electroluminescence with charge carriers of one type provided to the charge trapping structure by a forward biased p-n structure or a reverse biased p-n structure.
摘要翻译：公开了用电荷捕获结构进行电致发光的方法和装置。各种实施方案涉及用于通过正向偏置p-n结构或反向偏置p-n结构提供给电荷俘获结构的一种类型的电荷载体进行电致发光的方法和装置。

73. 发明授权

US07269062B2 Gated diode nonvolatile memory cell 有权
标题翻译：门极二极管非易失性存储单元
公开(公告)号：US07269062B2
公开(公告)日：2007-09-11
申请号：US11298288
申请日：2005-12-09
申请人： Yi Yang Liao , Wen Jer Tsai , Chih Chieh Yeh
发明人： Yi Yang Liao , Wen Jer Tsai , Chih Chieh Yeh
IPC分类号： G11C11/36
CPC分类号： G11C11/36 , B82Y10/00 , G11C8/10 , G11C16/02 , G11C2216/06 , H01L27/1021 , H01L29/8616
摘要： A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.
摘要翻译：具有电荷存储结构的门控二极管非易失性存储单元包括具有附加栅极端子的二极管结构。示例性实施例包括单独的存储器单元，这种存储器单元的阵列，操作存储单元或存储单元阵列的方法及其制造方法。

74. 发明授权

US07230277B2 Method and apparatus for electroluminescence 有权
标题翻译：电致发光的方法和装置
公开(公告)号：US07230277B2
公开(公告)日：2007-06-12
申请号：US11086898
申请日：2005-03-22
申请人： Chih Chieh Yeh , Shao Hong Ku , Tahui Wang , Chih Yuan Lu
发明人： Chih Chieh Yeh , Shao Hong Ku , Tahui Wang , Chih Yuan Lu
IPC分类号： H01L27/108
CPC分类号： H01L33/02 , H01L33/0004
摘要： Methods and apparatuses for causing electroluminescence with charge trapping structures are disclosed. Various embodiments relate to methods and apparatuses for causing electroluminescence with charge carriers of one type provided to the charge trapping structure by a forward biased p-n structure or a reverse biased p-n structure.
摘要翻译：公开了用电荷捕获结构进行电致发光的方法和装置。各种实施方案涉及用于通过正向偏置p-n结构或反向偏置p-n结构提供给电荷俘获结构的一种类型的电荷载体进行电致发光的方法和装置。

75. 发明授权

US07180123B2 Method for programming programmable eraseless memory 有权
标题翻译：编程可编程擦除存储器的方法
公开(公告)号：US07180123B2
公开(公告)日：2007-02-20
申请号：US10642249
申请日：2003-08-15
申请人： Chih Chieh Yeh , Han Chao Lai , Wen Her Tsai , Tao Cheng Lu , Chih Yuan Lu
发明人： Chih Chieh Yeh , Han Chao Lai , Wen Her Tsai , Tao Cheng Lu , Chih Yuan Lu
IPC分类号： H01L29/76
CPC分类号： G11C11/5692 , G11C17/14 , G11C2211/5634 , H01L23/5252 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： A method for programming a memory cell is based on applying stress to a memory cell, comprising a first electrode, a second electrode and an inter-electrode layer, to induce a progressive change in a property of the inter-electrode layer. The method includes a verify step including generating a signal, such as a cell current, indicating the value of the property in the selected memory cell. Then, the signal is compared with a reference signal to verify programming of the desired data. Because of the progressive nature of the change, many levels of programming can be achieved. The many levels of programming can be applied for programming a single cell more than once, without an erase process, to programming multiple bits in a single cell, and to a combination of multiple bit and multiple time of programming.
摘要翻译：用于对存储单元进行编程的方法是基于向包括第一电极，第二电极和电极间层的存储单元施加应力，以引起电极间层的性能的逐渐变化。该方法包括验证步骤，包括生成指示所选择的存储单元中的属性的值的诸如单元电流的信号。然后，将信号与参考信号进行比较，以验证所需数据的编程。由于变革的渐进性，可以实现多层次的编程。多个编程级别可以应用于单个单元的编程，而不需要擦除处理，以编程单个单元中的多个位，以及多个位和多个编程时间的组合。

76. 发明授权

US07132350B2 Method for manufacturing a programmable eraseless memory 有权
标题翻译：制造可编程擦除存储器的方法
公开(公告)号：US07132350B2
公开(公告)日：2006-11-07
申请号：US10641897
申请日：2003-08-15
申请人： Chih Chieh Yeh , Han Chao Lai , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
发明人： Chih Chieh Yeh , Han Chao Lai , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
IPC分类号： H01L21/479 , H01L21/326
CPC分类号： G11C11/5692 , H01L27/101
摘要： A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.
摘要翻译：一种用于制造电可编程非易失性存储单元的方法包括在衬底上形成第一电极，在第一电极上形成具有特征在于应力的响应逐渐变化的特性的材料的电极间层，并形成第二电极在材料的电极间层之上。电极间层包括在第一和第二电极之间的介电层，例如超薄氧化物。可编程电阻或其他属性通过强调介电层来表示存储的数据来建立。存储器单元的实施例适于存储每个单元的多个数据位和/或适于在不进行擦除处理的情况下编程多于一次。

77. 发明授权

US07130215B2 Method and apparatus for operating a non-volatile memory device 有权
公开(公告)号：US07130215B2
公开(公告)日：2006-10-31
申请号：US11024339
申请日：2004-12-28
申请人： Chih Chieh Yeh
发明人： Chih Chieh Yeh
IPC分类号： G11C11/34
CPC分类号： H01L27/11568 , G11C16/0416 , G11C16/0466 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/26 , H01L27/115
摘要： A nonvolatile memory cell with a charge trapping structure coupled in series is read, by measuring current that flows between the body region of the nonvolatile memory cell and the contact region of the nonvolatile memory cell. The charge storage state of the charge trapping structure affects the measured current.

78. 发明申请

US20060140006A1 Method and apparatus for operating a non-volatile memory device 有权
标题翻译：用于操作非易失性存储器件的方法和装置
公开(公告)号：US20060140006A1
公开(公告)日：2006-06-29
申请号：US11024339
申请日：2004-12-28
申请人： Chih Chieh Yeh
发明人： Chih Chieh Yeh
IPC分类号： G11C16/06 , G11C16/26 , G11C16/34
CPC分类号： H01L27/11568 , G11C16/0416 , G11C16/0466 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/26 , H01L27/115
摘要： A nonvolatile memory cell with a charge trapping structure coupled in series is read, by measuring current that flows between the body region of the nonvolatile memory cell and the contact region of the nonvolatile memory cell. The charge storage state of the charge trapping structure affects the measured current.
摘要翻译：通过测量在非易失性存储单元的主体区域和非易失性存储单元的接触区域之间流动的电流来读取具有串联耦合的电荷俘获结构的非易失性存储单元。电荷捕获结构的电荷存储状态影响测量的电流。

79. 发明授权

US07057938B2 Nonvolatile memory cell and operating method 有权
标题翻译：非易失性存储单元和操作方法
公开(公告)号：US07057938B2
公开(公告)日：2006-06-06
申请号：US10756777
申请日：2004-01-14
申请人： Chih Chieh Yeh , Hung Yueh Chen , Yi Ying Liao , Wen Jer Tsai , Tao Cheng Lu
发明人： Chih Chieh Yeh , Hung Yueh Chen , Yi Ying Liao , Wen Jer Tsai , Tao Cheng Lu
IPC分类号： G11C16/00
CPC分类号： G11C16/10 , G11C16/0475 , H01L21/28282 , H01L29/66833 , H01L29/792 , H01L29/7923
摘要： One embodiment of the present invention provides a system having a nonvolatile memory comprising a p type semiconductor substrate, an oxide layer over the p type semiconductor substrate, a nitride layer over the oxide layer, an additional oxide layer over the nitride layer, a gate over the additional oxide layer, two N+ junctions in the p type semiconductor layer, a source and drain respectively formed in the two N+ junctions, a first bit and a second bit in the nonvolatile memory, and accordingly at least two states of operation (i.e., erase and program) therefor. That is, one bit in the nonvolatile memory can either be in an erase state or program state. For erasing a bit, electrons are injected at the gate of the nonvolatile memory. For programming a bit, electric holes are injected or electrons are reduced for that bit. The present invention also provides a method for sensing and reading at least one bit in a nonvolatile memory comprising applying a bias voltage to the memory, detecting a threshold voltage or read current, comparing the threshold voltage with a reference voltage or comparing the read current with a reference current, and identifying the at least one bit as erased or programmed.
摘要翻译：本发明的一个实施例提供一种具有非易失性存储器的系统，其包括ap型半导体衬底，p型半导体衬底上的氧化物层，氧化物层上方的氮化物层，氮化物层上的附加氧化物层，分别形成在两个N +结中的源极和漏极，非易失性存储器中的第一位和第二位，以及相应地至少两个操作状态（即擦除）的附加氧化物层，p型半导体层中的两个N +结，和程序）。也就是说，非易失性存储器中的一位可以处于擦除状态或程序状态。为了擦除一点，电子注入非易失性存储器的栅极。为了编程一点，注入电孔或减少电子的位。本发明还提供了一种用于感测和读取非易失性存储器中的至少一个位的方法，包括向存储器施加偏置电压，检测阈值电压或读取电流，将阈值电压与参考电压进行比较，或将读取的电流与参考电流，并将所述至少一个位识别为擦除或编程。

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